W39V040BPZ原理图各脚功能电路原理芯片引脚定义引脚图及功能-中国IC网-芯三七

W39V040B Data Sheet

512K × 8 CMOS FLASH MEMORY

WITH LPC INTERFACE

Table of Contents-

1.

2.

3.

4.

5.

6.

GENERAL DESCRIPTION ......................................................................................................... 3

FEATURES................................................................................................................................. 3

PIN CONFIGURATIONS............................................................................................................. 4

BLOCK DIAGRAM ...................................................................................................................... 4

PIN DESCRIPTION..................................................................................................................... 4

FUNCTIONAL DESCRIPTION.................................................................................................... 5

6.1 Interface Mode Selection and Description......................................................................... 5

6.2 Read (Write) Mode ............................................................................................................ 5

6.3 Reset Operation................................................................................................................. 5

6.4 Boot Block Operation and Hardware Protection at Initial- #TBL & #WP........................... 5

6.5 Sector Erase Command .................................................................................................... 5

6.6 Program Operation ............................................................................................................ 6

6.7 Hardware Data Protection ................................................................................................. 6

6.8 WRITE OPERATION STATUS.......................................................................................... 6

7.

8.

9.

REGISTER FOR LPC MODE ..................................................................................................... 8

7.1 General Purpose Inputs Register for LPC Mode............................................................... 8

7.2 Identification Input Pins ID[3:0].......................................................................................... 8

7.3 Product Identification Registers......................................................................................... 8

TABLE OF OPERATING MODES .............................................................................................. 9

8.1 Operating Mode Selection - Programmer Mode................................................................ 9

8.2 Operating Mode Selection - LPC Mode............................................................................. 9

8.3 LPC Cycle Definition.......................................................................................................... 9

TABLE OF COMMAND DEFINITION ....................................................................................... 10

9.1 Embedded Programming Algorithm ................................................................................ 11

9.2 Embedded Erase Algorithm............................................................................................. 12

9.3 Embedded #Data Polling Algorithm................................................................................. 13

9.4 Embedded Toggle Bit Algorithm...................................................................................... 14

9.5 Software Product Identification and Boot Block Lockout Detection Acquisition Flow ..... 15

10.

ELECTRICAL CHARACTERISTICS......................................................................................... 16

10.1

10.2

10.3

10.4

10.5

10.6

10.7

Absolute Maximum Ratings......................................................................................... 16

Programmer interface Mode DC Operating Characteristics ....................................... 16

LPC Interface Mode DC Operating Characteristics .................................................... 17

Power-up Timing ......................................................................................................... 17

Capacitance................................................................................................................. 17

Programmer Interface Mode AC Characteristics ........................................................ 18

Read Cycle Timing Parameters .................................................................................. 19

Publication Release Date: April 14, 2005

- 1 -

Revision A3

W39V040B

10.8

10.9

Write Cycle Timing Parameters................................................................................... 19

Data Polling and Toggle Bit Timing Parameters ......................................................... 19

11.

TIMING WAVEFORMS FOR PROGRAMMER INTERFACE MODE ....................................... 20

11.1

11.2

11.3

11.4

11.5

11.6

Read Cycle Timing Diagram ....................................................................................... 20

Write Cycle Timing Diagram........................................................................................ 20

Program Cycle Timing Diagram.................................................................................. 21

#DATA Polling Timing Diagram................................................................................... 21

Toggle Bit Timing Diagram.......................................................................................... 22

Sector Erase Timing Diagram ..................................................................................... 22

12.

13.

LPC INTERFACE MODE AC CHARACTERISTICS................................................................. 23

12.1

12.2

12.3

AC Test Conditions ..................................................................................................... 23

Read/Write Cycle Timing Parameters......................................................................... 23

Reset Timing Parameters............................................................................................ 23

TIMING WAVEFORMS FOR LPC INTERFACE MODE........................................................... 24

13.1

13.2

13.3

13.4

13.5

13.6

13.7

13.8

Read Cycle Timing Diagram ....................................................................................... 24

Write Cycle Timing Diagram........................................................................................ 24

Program Cycle Timing Diagram.................................................................................. 25

#DATA Polling Timing Diagram................................................................................... 26

Toggle Bit Timing Diagram.......................................................................................... 27

Sector Erase Timing Diagram ..................................................................................... 28

FGPI Register/Product ID Readout Timing Diagram .................................................. 29

Reset Timing Diagram................................................................................................. 29

14.

15.

16.

ORDERING INFORMATION..................................................................................................... 30

HOW TO READ THE TOP MARKING...................................................................................... 30

PACKAGE DIMENSIONS......................................................................................................... 31

16.1

16.2

32L PLCC.................................................................................................................... 31

32L STSOP ................................................................................................................. 31

17.

VERSION HISTORY................................................................................................................. 32

Publication Release Date: April 14, 2005

- 2 -

Revision A3

W39V040B

1. GENERAL DESCRIPTION

The W39V040B is a 4-megabit, 3.3-volt only CMOS flash memory organized as 512K × 8 bits. For

flexible erase capability, the 4Mbits of data are divided into 8 uniform sectors of 64 Kbytes. The device

can be programmed and erased in-system with a standard 3.3V power supply. A 12-volt VPP is

required for accelerated program. The unique cell architecture of the W39V040B results in fast

program/erase operations with extremely low current consumption. This device can operate at two

modes, Programmer bus interface mode, Low pin count (LPC) bus interface mode. As in the

Programmer interface mode, it acts like the traditional flash but with a multiplexed address inputs. But

in the LPC interface mode, this device complies with the Intel LPC specification. The device can also be

programmed and erased using standard EPROM programmers.

2. FEATURES

•

Single 3.3-volt operations:

− 3.3-volt Read

− 3.3-volt Erase

•

Hardware protection:

− #TBL supports 64-Kbyte Boot Block

hardware protection

− #WP supports the whole chip except Boot

− 3.3-volt Program

Block hardware protection

•

Fast Program operation:

− Byte-by-Byte programming: 9 µS (typ.)

(VPP = 12V)

− Byte-by-Byte programming: 12 µS (typ.)

(VPP = Vcc)

•

Low power consumption

− Active current: 15 mA (typ. for LPC read

mode)

•

Automatic program and erase timing with

internal VPP generation

•

Fast Erase operation:

− Sector erase 0.6 Sec. (typ.)

End of program or erase detection

− Toggle bit

− Data polling

Latched address and data

TTL compatible I/O

•

Fast Read access time: Tkq 11 nS

Endurance: 10K cycles (typ.)

Twenty-year data retention

8 Even sectors with 64K bytes

Any individual sector can be erased

•

Available packages: 32L PLCC, 32L STSOP

32L PLCC Lead free, 32L STSOP Lead free

Publication Release Date: April 14, 2005

Revision A3

- 3 -

W39V040B

3. PIN CONFIGURATIONS

4. BLOCK DIAGRAM

#WP

7FFFF

#TBL

CLK

64K BYTES BLOCK 7

LPC

70000

6FFFF

Interface

LAD[3:0]

#LFRAM

64K BYTES BLOCK 6

60000

5FFFF

MODE

#INIT

#RESET

64K BYTES BLOCK 5

64K BYTES BLOCK 4

50000

4FFFF

40000

3FFFF

64K BYTES BLOCK 3

64K BYTES BLOCK 2

R/#C

A[10:0]

DQ[7:0]

30000

2FFFF

Program-

mer

Interface

20000

1FFFF

10000

0FFFF

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

64K BYTES BLOCK 1

64K BYTES BLOCK 0

1

#OE(#INIT)

NC

#OE

#WE

RY/#BY

2

#WE(#LFRAM

RY/#BY(RSV)

DQ7(RSV)

NC

3

NC

4

SS

V

5

00000

DQ6(RSV)

MODE

6

A10(FGPI4)

DQ5(RSV)

7

R/#C(CLK)

DQ4(RSV)

DQ3(LAD3)

8

DD

V

32L STSOP

9

Vpp

SS

V

10

11

12

13

14

15

16

DQ2(LAD2)

DQ1(LAD1)

#RESET

A9(FGPI3)

A8(FGPI2)

A7(FGPI1)

A6(FGPI0)

A5(#WP)

DQ0(LAD0)

A0(ID0)

A1(ID1)

A2(ID2)

A3(ID3)

5. PIN DESCRIPTION

A4(#TBL)

INTERFACE

SYM.

PIN NAME

PGM LPC

MODE

#RESET

#INIT

*

Interface Mode Selection

Reset

A

1

0

^

A

8

^

R

/

A

9

^

#

C

^

#

F

G

P

I

F

G

P

I

F

G

P

I

R

E

S

E

T

Initialize

C

L

K

v

V

P

V

D

#TBL

Top Boot Block Lock

Write Protect

CLK Input

General Purpose Inputs

2

v

3

v

4

v

#WP

4

3

2

1

32 31 30

CLK

A7(FGPI1)

A6(FGPI0)

A5(#WP)

A4(#TBL)

A3(ID3)

5

6

29

28

27

26

25

24

23

22

21

MODE

SS

FGPI[4:0]

V

7

8

Identification Inputs They

Are Internal Pull Down to

Vss

NC

V ^DD

#OE(#INIT)

#WE(#LFRAM)

RY/#BY(RSV)

DQ7(RSV)

ID[3:0]

*

9

32L PLCC

10

11

12

13

A2(ID2)

A1(ID1)

LAD[3:0]

#LFRAM

R/#C

*

Address/Data Inputs

LPC Cycle Initial

Row/Column Select

Address Inputs

Data Inputs/Outputs

Output Enable

Write Enable

A0(ID0)

DQ0(LAD0)

14 15 16 17 18 19 20

*

A[10:0]

DQ[7:0]

#OE

D

Q

1

D

Q

2

D

Q

5

D

Q

3

D

Q

4

D

Q

6

V

S

^

L

R

S

V

v

L

R

S

V

v

R

S

V

v

A

D

2

v

D

3

v

1

v

#WE

RY/#BY

VDD

Ready/ Busy

*

Power Supply

VSS

Ground

Accelerate Program Power

VPP

*

Supply

RSV

NC

*

Reserved Pins

No Connection

Publication Release Date: April 14, 2005

Revision A3

- 4 -

W39V040B

6. FUNCTIONAL DESCRIPTION

6.1 Interface Mode Selection and Description

This device can operate in two interface modes, one is Programmer interface mode, and the other is

LPC interface mode. The Mode pin of the device provides the control between these two interface

modes. These interface modes need to be configured before power up or return from #RESET. When ic

(Mode) pin is set to VDD, the device will be in the Programmer mode; while the Mode pin is set to low

state (or leaved no connection), it will be in the LPC mode. In Programmer mode, this device just

behaves like traditional flash parts with 8 data lines. But the row and column address inputs are

multiplexed. The row address are mapped to the higher internal address A[18:11]. And the column

address are mapped to the lower internal address A[10:0]. For LPC mode, it complies with the LPC

Interface Specification, through the LAD[3:0] to communicate with the system chipset .

6.2 Read (Write) Mode

In Programmer interface mode, the read (write) operation of the W39V040B is controlled by #OE

(#WE). The #OE (#WE) is held low for the host to obtain (write) data from (to) the outputs (inputs).

#OE is the output control and is used to gate data from the output pins. The data bus is in high

impedance state when #OE is high. As for in the LPC interface mode, the read or write is determined

by the "START CYCLE ". Refer to the LPC cycle definition and timing waveforms for further details.

6.3 Reset Operation

The #RESET input pin can be used in some application. When #RESET pin is at high state, the

device is in normal operation mode. When #RESET pin is at low state, it will halt the device and all

outputs will be at high impedance state. As the high state re-asserted to the #RESET pin, the device

will return to read or standby mode, it depends on the control signals.

6.4 Boot Block Operation and Hardware Protection at Initial- #TBL & #WP

There is a hardware method to protect the top boot block and other sectors. Before power on

programmer, tie the #TBL pin to low state and then the top boot block will not be programmed/erased. If

#WP pin is tied to low state before power on, the other sectors will not be programmed/erased.

In order to detect whether the boot block feature is set on or not, users can perform software command

sequence: enter the product identification mode (see Command Codes for Identification/Boot Block

Lockout Detection for specific code), and then read from address 7FFF2(hex). You can check the

DQ2/DQ3 at the address 7FFF2 to see whether the #TBL/#WP pin is in low or high state. If the DQ2 is

“0”, it means the #TBL pin is tied to high state. In such condition, whether boot block can be

programmed/erased or not will depend on software setting. On the other hand, if the DQ2 is “1”, it

means the #TBL pin is tied to low state, then boot block is locked no matter how the software is set.

Like the DQ2, the DQ3 inversely mirrors the #WP state. If the DQ3 is “0”, it means the #WP pin is in

high state, then all the sectors except the boot block can be programmed/erased. On the other hand, if

the DQ3 is “1”, then all the sectors except the boot block are programmed/erased inhibited.

To return to normal operation, perform a three-byte command sequence (or an alternate single-byte

command) to exit the identification mode. For the specific code, see Command Codes for

Identification/Boot Block Lockout Detection.

6.5 Sector Erase Command

Sector erase is a six-bus cycles operation. There are two "unlock" write cycles, followed by writing the

"set-up" command. Two more "unlock" write cycles then follows by the Sector erase command. The

Publication Release Date: April 14, 2005

- 5 -

Revision A3

W39V040B

Sector address (any address location within the desired Sector) is latched on the rising edge of R/#C in

programmer mode, while the command (30H) is latched on the rising edge of #WE.

Sector erase does not require the user to program the device prior to erase. When erasing a Sector,

the remaining unselected sectors are not affected. The system is not required to provide any controls or

timings during these operations.

The automatic Sector erase begins after the erase command is completed, right from the rising edge of

the #WE pulse for the last Sector erase command pulse and terminates when the data on DQ7, Data

Polling, is "1" at which time the device returns to the read mode. Data Polling must be performed at an

address within any of the sectors being erased.

Refer to the Erase Command flow Chart using typical command strings and bus operations.

6.6 Program Operation

The W39V040B is programmed on a byte-by-byte basis. Program operation can only change logical

data "1" to logical data "0." The erase operation, which changed entire data in main memory and/or

boot block from "0" to "1", is needed before programming.

The program operation is initiated by a 4-byte command cycle (see Command Codes for Byte

Programming). The device will internally enter the program operation immediately after the

byte-program command is entered. The internal program timer will automatically time-out (9µS typ. -

TBP) once it is completed and then return to normal read mode. Data polling and/or Toggle Bits can be

used to detect end of program cycle.

6.7 Hardware Data Protection

The integrity of the data stored in the W39V040B is also hardware protected in the following ways:

(1) Noise/Glitch Protection: A #WE pulse of less than 5 nS in duration will not initiate a write cycle.

(2) VDD Power Up/Down Detection: The programming and read operation are inhibited when VDD is

less than 2.0V typical.

(3) Write Inhibit Mode: Forcing #OE low or #WE high will inhibit the write operation. This prevents

inadvertent writes during power-up or power-down periods.

6.8 WRITE OPERATION STATUS

The device provides several bits to determine the status of a program or erase operation: DQ5, DQ6,

and DQ7. Each of DQ7 and DQ6 provides a method for determining whether a program or erase

operation is complete or in progress. The device also offers a hardware-based output signal, RY/#BY in

programmer mode, to determine whether an Embedded Program or Erase operation is in progress or

has been completed.

DQ7: #Data Polling

The #Data Polling bit, DQ7, indicates whether an Embedded Program or Erase algorithm is in progress

or completed. Data Polling is valid after the rising edge of the final #WE pulse in the command

sequence.

During the Embedded Program algorithm, the device outputs on DQ7 and the complement of the data

programmed to DQ7. Once the Embedded Program algorithm has completed, the device outputs the

data programmed to DQ7. The system must provide the program address to read valid status

information on DQ7. If a program address falls within a protected sector, #Data Polling on DQ7 is active

for about 1µS, and then the device returns to the read mode.

During the Embedded Erase algorithm, #Data Polling produces “0” on DQ7. Once the Embedded

Publication Release Date: April 14, 2005

- 6 -

Revision A3

W39V040B

Erase algorithm has completed, #Data Polling produces “1” on DQ7. An address within any of the

sectors selected for erasure must be provided to read valid status information on DQ7.

Just before the completion of an Embedded Program or Erase operation, DQ7 may change

asynchronously with DQ0-DQ6 while Output Enable (#OE) is set to low. That is, the device may

change from providing status information to valid data on DQ7. Depending on when it samples the DQ7

output, the system may read the status or valid data. Even if the device has completed the program or

erase operation and DQ7 has valid data, the data outputs on DQ0-DQ6 may be still invalid. Valid data

on DQ7-DQ0 will appear on successive read cycles.

RY/#BY: Ready/#Busy

The RY/#BY is a dedicated, open-drain output pin which indicates whether an Embedded Algorithm is in

progress or complete. The RY/#BY status is valid after the rising edge of the final #WE pulse in the command

sequence. Since RY/#BY is an open-drain output, several RY/#BY pins can be tied together in parallel with a

pull-up resistor to V_DD

.

When the output is low (Busy), the device is actively erasing or programming. When the output is high

(Ready), the device is in the read mode or standby mode.

DQ6: Toggle Bit

Toggle Bit on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or

complete. Toggle Bit I may be read at any address, and is valid after the rising edge of the final #WE

pulse in the command sequence (before the program or erase operation), and during the sector erase

time-out.

During an Embedded Program or Erase algorithm operation, successive read cycles to any address

cause DQ6 to toggle. The system may use either #OE to control the read cycles. Once the operation

has completed, DQ6 stops toggling.

The system can use DQ6 to determine whether a sector is actively erasing. If the device is actively

erasing (i.e., the Embedded Erase algorithm is in progress), DQ6 toggles. If a program address falls

within a protected sector, DQ6 toggles for about 1 µs after the program command sequence is written,

and then returns to reading array data.

DQ5: Exceeded Timing Limits

DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit.

DQ5 produces “1” under these conditions which indicates that the program or erase cycle was not

successfully completed.

The device may output “1” on DQ5 if the system tries to program “1” to a location that was previously

programmed to “0.” Only the erase operation can change “0” back to “1.” Under this condition, the

device stops the operation, and while the timing limit has been exceeded, DQ5 produces “1.”

Under both these conditions, the system must write the reset command to return to the read mode.

Multi-Chip Operation

Multiple devices can be wired on the single LPC bus. There are four ID pins can be used to support up

to 16 devices. But in order not to violate the BIOS ROM memory space defined by Intel, Winbond

W39V040A will only used 3 ID pins to allow up to 8 devices, 4Mbytes for BIOS code and 4Mbytes for

registers memory space.

Publication Release Date: April 14, 2005

- 7 -

Revision A3

W39V040B

7. REGISTER FOR LPC MODE

There are two kinds of registers on this device, the General Purpose Input Registers and Product

Identification Registers. Users can access these registers through respective address in the 4Gbytes

memory map. There are detail descriptions in the sections below.

7.1 General Purpose Inputs Register for LPC Mode

This register reads the FGPI[4:0] pins on the W39V040B.This is a pass-through register which can read

via memory address FBC0100(hex). Since it is pass-through register, there is no default value.

GPI Register Table

BIT

7 − 5

FUNCTION

Reserved

4

3

2

1

0

Read FGPI4 pin status

Read FGPI3 pin status

Read FGPI2 pin status

Read FGPI1 pin status

Read FGPI0 pin status

7.2 Identification Input Pins ID[3:0]

These pins are part of mechanism that allows multiple parts to be used on the same bus. The boot

device should be 0000b. And all the subsequent parts should use the up-count strapping. Note that a

1M byte ROM will occupy two Ids. For example: a 1MByte ROM's ID is 0000b, the next ROM's ID is

0010b. These pins all are pulled down with internal resistor.

7.3 Product Identification Registers

In the LPC interface mode, a read from FBC, 0000(hex) can output the manufacturer code, DA(hex). A

read from FBC, 0001(hex) can output the device code 54(hex).

There is an alternative software method (six commands bytes) to read out the Product Identification in

both the Programmer interface mode and the LPC interface mode. Thus, the programming equipment

can automatically matches the device with its proper erase and programming algorithms.

In the software access mode, a six-byte (or JEDEC 3-byte) command sequence can be used to access

the product ID for programmer interface mode. A read from address 0000(hex) outputs the

manufacturer code, DA(hex). A read from address 0001(hex) outputs the device code, 54(hex). The

product ID operation can be terminated by a three-byte command sequence or an alternate one-byte

command sequence (see Command Definition table for detail).

Publication Release Date: April 14, 2005

- 8 -

Revision A3

W39V040B

8. TABLE OF OPERATING MODES

8.1 Operating Mode Selection - Programmer Mode

PINS

ADDRESS

MODE

#OE

VIL

VIH

X

#WE

VIH

VIL

X

#RESET

VIH

DQ.

Read

AIN

X

Dout

Write

VIH

Din

Standby

VIL

High Z

VIL

X

VIH

X

High Z/DOUT

High Z

Write Inhibit

VIH

X

VIH

Output Disable

VIH

8.2 Operating Mode Selection - LPC Mode

Operation modes in LPC interface mode are determined by "START Cycle" when it is selected. When it

is not selected, its outputs (LAD[3:0]) will be disable. Please reference to the "LPC Cycle Definition".

8.3 LPC Cycle Definition

NO. OF

FIELD

DESCRIPTION

CLOCKS

Start

1

"0000b" appears on LPC bus to indicate the initial

"010Xb" indicates memory read cycle; while "011xb" indicates

memory write cycle. "X" mean don't have to care.

Turned Around Time

Cycle Type & Dir

TAR

1

2

Address Phase for Memory Cycle. LPC supports the 32 bits address

protocol. The addresses transfer most significant nibble first and

least significant nibble last. (i.e. Address[31:28] on LAD[3:0] first ,

and Address[3:0] on LAD[3:0] last.)

Addr.

8

Synchronous to add wait state. "0000b" means Ready, "0101b"

means Short Wait, "0110b" means Long Wait, "1001b" for DMA only,

"1010b" means error, other values are reserved.

Data Phase for Memory Cycle. The data transfer least significant

nibble first and most significant nibble last. (i.e. DQ[3:0] on LAD[3:0]

first, then DQ[7:4] on LAD[3:0] last.)

Sync.

Data

N

2

Publication Release Date: April 14, 2005

- 9 -

Revision A3

W39V040B

9. TABLE OF COMMAND DEFINITION

COMMAND

NO. OF

1ST CYCLE

2ND CYCLE 3RD CYCLE 4TH CYCLE 5TH CYCLE 6TH CYCLE

DESCRIPTION

Cycles (1)

Addr. Data

Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data

Read

1

6

4

3

1

A_IN

D_OUT

AA

Sector Erase

5555

2AAA

55

5555

80

5555

AA

D_IN

2AAA

55

SA⁽⁵⁾

30

Byte Program

AA

A0 A_IN

90

Product ID Entry

Product ID Exit ⁽⁴⁾

AA

F0

XXXX F0

Notes:

1. The cycle means the write command cycle not the LPC clock cycle.

2. The Column Address / Row Address are mapped to the Low / High order Internal Address. i.e. Column Address

A[10:0] are mapped to the internal A[10:0], Row Address A[7:0] are mapped to the internal A[18:11]

3. Address Format: A14−A0 (Hex); Data Format: DQ7-DQ0 (Hex)

4. Either one of the two Product ID Exit commands can be used.

5. SA: Sector Address

SA = 7XXXXh for Unique Sector7 (Boot Sector)

SA = 6XXXXh for Unique Sector6

SA = 5XXXXh for Unique Sector5

SA = 3XXXXh for Unique Sector3

SA = 2XXXXh for Unique Sector2

SA = 1XXXXh for Unique Sector1

SA = 0XXXXh for Unique Sector0

SA = 4XXXXh for Unique Sector4

Publication Release Date: April 14, 2005

Revision A3

- 10 -

W39V040B

9.1 Embedded Programming Algorithm

Start

Write Program Command Sequence

(see below)

#Data Polling/ Toggle bit

Programming Completed

Program Command Sequence (Address/Command):

5555H/AAH

2AAAH/55H

5555H/A0H

Program Address/Program Data

Publication Release Date: April 14, 2005

Revision A3

- 11 -

W39V040B

9.2 Embedded Erase Algorithm

Start

Write Erase Command Sequence

(see below)

#Data Polling or Toggle Bit

Erasure Completed

Individual Sector Erase

Command Sequence

(Address/Command):

5555H/AAH

2AAAH/55H

5555H/80H

5555H/AAH

2AAAH/55H

Sector Address/30H

Publication Release Date: April 14, 2005

Revision A3

- 12 -

W39V040B

9.3 Embedded #Data Polling Algorithm

Start

Read Byte

(DQ0 - DQ7)

Address = SA

Yes

DQ7 = Data

?

No

DQ5 = 1

Yes

Read Byte

(DQ0 - DQ7)

Address = SA

Yes

DQ7 = Data

No

Fail

Pass

Note: SA = Valid address for programming .During a sector erase operation, a valid address is an

address within any sector selected for erasure.

Publication Release Date: April 14, 2005

Revision A3

- 13 -

W39V040B

9.4 Embedded Toggle Bit Algorithm

Start

Read Byte

(DQ0-DQ7)

Read Byte

(DQ0-DQ7)

No

Toggle Bit

=Toggle ?

Yes

No

DQ5 = 1 ?

Yes

Read Byte

(DQ0-DQ7) twin

No

Toggle Bit

=Toggle ?

Program/Erase

Operation complete

Program/Erase

Operation Not

Complete, Write

Reset Command

Note: Recheck toggle bit because it may stop toggling as DQ5 changes to “1”.

Publication Release Date: April 14, 2005

Revision A3

- 14 -

W39V040B

9.5 Software Product Identification and Boot Block Lockout Detection Acquisition

Flow

Product

Identification

Entry (1)

Product

Identification

and Boot Block

Lockout Detection

Mode (3)

Identification Exit(6)

Load data AA

to

Load data AA

to

address 5555

(2)

(4)

Load data 55

to

Load data 55

to

Read address = 00000

data = DA

address 2AAA

Load data 90

to

Load data F0

to

Read address = 00001

data = 54

address 5555

Read address = 7FFF2

Pause 10 S

µ

Pause 10 S

µ

Check DQ[3:0] of data

outputs

(5)

Normal Mode

Notes for software product identification/boot block lockout detection:

(1) Data Format: DQ7−DQ0 (Hex); Address Format: A14−A0 (Hex)

(2) A1−A18 = VIL; manufacture code is read for A0 = VIL; device code is read for A0 = VIH.

(3) The device does not remain in identification and boot block lockout detection mode if power down.

(4) The DQ[3:2] to indicate the sectors protect status as below:

DQ2

DQ3

0

1

64Kbytes Boot Block Unlocked by

Whole Chip Unlocked by #WP hardware

#TBL hardware trapping

trapping Except Boot Block

64Kbytes Boot Block Locked by #TBL Whole Chip Locked by #WP hardware

hardware trapping trapping Except Boot Block

(5) The device returns to standard operation mode.

(6) Optional 1-write cycle (write F0 (hex.) at XXXX address) can be used to exit the product identification/boot block lockout

detection.

Publication Release Date: April 14, 2005

- 15 -

Revision A3

W39V040B

10. ELECTRICAL CHARACTERISTICS

10.1 Absolute Maximum Ratings

PARAMETER

Operating Temperature

RATING

0 to +70

UNIT

°C

Storage Temperature

-65 to +150

-0.5 to +4.0

-0.5 to VDD +0.5

-0.5 to +13

°C

V

Power Supply Voltage to VSS Potential

D.C. Voltage on Any Pin to Ground Potential

VPP Voltage

Transient Voltage (<20 nS) on Any Pin to Ground Potential

-1.0 to VDD +0.5

Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings May adversely affect the life and reliability

of the device.

10.2 Programmer interface Mode DC Operating Characteristics

(VDD = 3.3V ± 0.3V, VSS = 0V, TA = 0 to 70° C)

LIMITS

MIN. TYP.

PARAMETER

SYM.

TEST CONDITIONS

UNIT

MAX.

In Read or Write mode, all DQs open

Address inputs = 3.0V/0V, at f = 3 MHz

Power Supply

Icc

ILI

-

15

-

30

mA

Current

Input Leakage

Current

Output Leakage

Current

VIN = VSS to VDD

90

µA

ILO VOUT = VSS to VDD

-

Input Low Voltage

Input High Voltage

Output Low Voltage

VIL

-

-0.5

2.0

-

0.8

VDD +0.5

0.45

V

VIH

VOL IOL = 2.1 mA

Output High Voltage VOH IOH = -0.1mA

2.4

-

Publication Release Date: April 14, 2005

Revision A3

- 16 -

W39V040B

10.3 LPC Interface Mode DC Operating Characteristics

(VDD = 3.3V ± 0.3V, VSS= 0V, TA = 0 to 70° C)

LIMITS

TYP.

PARAMETER

SYM.

TEST CONDITIONS

UNIT

MIN.

MAX.

Power Supply Current

Read

All Iout = 0A, CLK = 33 MHz,

in LPC mode operation.

Icc

-

15

25

mA

Power Supply Current

Program/Erase

CLK = 33 MHz,

-

18

20

30

50

in LPC mode operation.

LPC4 = 0.9 VDD, CLK = 33 MHz,

Standby Current 1

Isb1

Isb2

uA

all inputs = 0.9 VDD / 0.1 VDD

no internal operation

LPC4 = 0.1 VDD, CLK = 33 MHz,

Standby Current 2

Input Low Voltage

Input Low Voltage of

#INIT

Input High Voltage

Input High Voltage of

#INIT Pin

-

3

10

mA

all inputs = 0.9 VDD /0.1 VDD

no internal operation.

VIL

VILI

VIH

VIHI

-

-0.5

-

0.3 VDD

0.2 VDD

V

0.5 VDD

1.35 V

VDD +0.5

Output Low Voltage

Output High Voltage

VOL IOL = 1.5 mA

VOH IOH = -0.5 mA

-

0.1 VDD

-

V

0.9 VDD

10.4 Power-up Timing

PARAMETER

Power-up to Read Operation

Power-up to Write Operation

SYMBOL

TPU. READ

TPU. WRITE

TYPICAL

100

UNIT

µS

5

mS

10.5 Capacitance

(VDD = 3.3V, TA = 25° C, f = 1 MHz)

PARAMETER

I/O Pin Capacitance

Input Capacitance

SYMBOL

CI/O

CONDITIONS

VI/O = 0V

MAX.

12

6

UNIT

pf

CIN

VIN = 0V

Publication Release Date: April 14, 2005

Revision A3

- 17 -

W39V040B

10.6 Programmer Interface Mode AC Characteristics

AC Test Conditions

PARAMETER

CONDITIONS

Input Pulse Levels

Input Rise/Fall Time

Input/Output Timing Level

Output Load

0V to 0.9 VDD

< 5 nS

1.5V/1.5V

1 TTL Gate and CL = 30 pF

AC Test Load and Waveform

+3.3V

1.8K

Ω

D

OUT

Input

Output

30 pF

0.9VDD

(Including Jig and

Scope)

1.3K

1.5V

Ω

1.5V

0V

Test Point

Publication Release Date: April 14, 2005

Revision A3

- 18 -

W39V040B

Programmer Interface Mode AC Characteristics, continued

10.7 Read Cycle Timing Parameters

(VDD = 3.3V ± 0.3V, VSS = 0V, TA = 0 to 70° C)

W39V040B

MIN. MAX.

PARAMETER

SYMBOL

UNIT

Read Cycle Time

TRC

TAS

350

50

-

0

-

nS

Row / Column Address Set Up Time

Row / Column Address Hold Time

Address Access Time

Output Enable Access Time

#OE Low to Active Output

#OE High to High-Z Output

Output Hold from Address Change

TAH

TAA

TOE

TOLZ

TOHZ

TOH

150

75

-

0

35

-

10.8 Write Cycle Timing Parameters

PARAMETER

Reset Time

Address Setup Time

Address Hold Time

R/#C to Write Enable High Time

#WE Pulse Width

#WE High Width

Data Setup Time

Data Hold Time

#OE Hold Time

Byte programming Time

Sector Erase Cycle Time (Note 2)

Program/Erase Valid to RY/#BY Delay

SYMBOL

TRST

TAS

TAH

TCWH

TWP

TWPH

TDS

TDH

TOEH

TBP

TPEC

MIN.

TYP.

-

MAX.

-

UNIT

µS

nS

µS

S

1

50

100

50

0

-

200

6

-

90

12

0.6

-

TBUSY

-

nS

Notes: 1. All AC timing signals observe the following guidelines for determining setup and hold times:

(a) High level signal's reference level is input high and (b) low level signal's reference level is input low.

Ref. to the AC testing condition.

2. Exclude 00H pre-program prior to erasure. (In the pre-programming step of the embedded erase algorithm,

all bytes are programmed to 00H before erasure

10.9 Data Polling and Toggle Bit Timing Parameters

W39V040B

PARAMETER

SYMBOL

UNIT

MIN.

MAX.

350

-

#OE to Data Polling Output Delay

#OE to Toggle Bit Output Delay

Toggle or Polling interval (for sector erase only) (Note1)

TOEP

TOET

-

50

nS

mS

Note1: Minimum timing interval between Toggle-check or Polling-check is required for sector erase only

Publication Release Date: April 14, 2005

Revision A3

- 19 -

W39V040B

11. TIMING WAVEFORMS FOR PROGRAMMER INTERFACE MODE

11.1 Read Cycle Timing Diagram

#RESET

T

RST

TRC

Row Address

Column Address

Row Address

A[10:0]

R/#C

Column Address

T

AS

T

AS

T

AH

VIH

#WE

#OE

T

AA

OH

T

TOE

TOHZ

T

OLZ

High-Z

DQ[7:0]

Data Valid

11.2 Write Cycle Timing Diagram

T

RST

#RESET

A[10:0]

Column Address

Row Address

T

AS

T

AS

T

AH

T

AH

R/

#C

T

CWH

T

OEH

#OE

#WE

T

WP

WPH

T

DH

T

DS

DQ[7:0]

Data Valid

Publication Release Date: April 14, 2005

Revision A3

- 20 -

W39V040B

Timing Waveforms for Programmer Interface Mode, continued

11.3 Program Cycle Timing Diagram

Byte Program Cycle

A[10:0]

2AAA

55

5555

Programmed Address

(Internal A[18:0])

DQ[7:0]

5555

A0

Data-In

AA

R/#C

#OE

#WE

T_WPH

BP

T

WP

T

Internal Write Start

Byte 0

Byte 1

Byte 2

Byte 3

RY/#BY

T_BUSY

Note: The internal address A[18:0] are converted from external Column/Row address.

Column/Row Address are mapped to the Low/High order internal address.

i.e. Column Address A[10:0] are mapped to the internal A[10:0],

Row Address A[7:0] are mapped to the internal A[18:11].

11.4 #DATA Polling Timing Diagram

A[10:0]

(Internal A[18:0])

An

R/#C

#WE

#OE

TOEP

X

DQ7

X

BP

T

RY/#BY

BUSY

T

Publication Release Date: April 14, 2005

Revision A3

- 21 -

W39V040B

Timing Waveforms for Programmer Interface Mode, continued

11.5 Toggle Bit Timing Diagram

A[10:0]

R/#C

#WE

#OE

T_OET

DQ6

T_BP

RY/#BY

11.6 Sector Erase Timing Diagram

Six-byte code for 3.3V-only

Sector Erase

A[10:0]

5555

AA

2AAA

55

(Internal A[18:0])

DQ[7:0]

5555

80

5555

AA

2AAA

55

SA

30

R/#C

#OE

#WE

T

WP

T

PEC

T

WPH

Internal Erase starts

SB0

SB2

SB3

SB5

SB4

SB1

RY/#BY

Note: The internal address A[18:0] are converted from external Column/Row addres

Column/Row Address are mapped to the Low/High order internal address

i.e. Column Address A[10:0] are mapped to the internal A[10:0]

T

BUSY

Row Address A[7:0] are mapped to the internal A[18:11].

SA = Sector Address, Please ref. to the "Table of Command Definition"

Publication Release Date: April 14, 2005

Revision A3

- 22 -

W39V040B

12. LPC INTERFACE MODE AC CHARACTERISTICS

12.1 AC Test Conditions

PARAMETER

Input Pulse Levels

Input Rise/Fall Slew Rate

Input/Output Timing Level

Output Load

CONDITIONS

0.6 VDD to 0.2 VDD

1 V/nS

0.4VDD / 0.4VDD

1 TTL Gate and CL = 10 pF

12.2 Read/Write Cycle Timing Parameters

(VDD = 3.3V ± 0.3V, VSS = 0V, TA = 0 to 70° C)

PARAMETER

SYMBOL

W39V040B

UNIT

MIN.

30

7

0

2

MAX.

-

11

Clock Cycle Time

Input Set Up Time

Input Hold Time

TCYC

TSU

THD

TKQ

nS

Clock to Data Valid

Note: Minimum and Maximum time have different load. Please refer to PCI specification.

12.3 Reset Timing Parameters

PARAMETER

VDD stable to Reset Active

Clock Stable to Reset Active

Reset Pulse Width

Reset Active to Output Float

Reset Inactive to Input Active

SYMBOL

TPRST

TKRST

TRSTP

TRSTF

TRST

MIN.

1

100

-

TYP.

MAX.

-

50

-

UNIT

mS

µS

nS

-

10

µS

Note: All AC timing signals observe the following guidelines for determining setup and hold times:

(a) High level signal's reference level is input high and (b) low level signal's reference level is input low.

Please refer to the AC testing condition.

Publication Release Date: April 14, 2005

Revision A3

- 23 -

W39V040B

13. TIMING WAVEFORMS FOR LPC INTERFACE MODE

13.1 Read Cycle Timing Diagram

T

CYC

CLK

#RESET

#LFRAM

LAD[3:0]

T

KQ

SU HD

Memory

Read

Address

A[31:28] A[27:24] A[23:20] A[19:16]

TAR

Next Start

0000b

Start

Sync

1111b Tri-State 0000b

2 Clocks

Data

D[3:0]

Cycle

0000b

TAR

010Xb

A[15:12] A[11:8] A[7:4]

Load Address in 8 Clocks

A[3:0]

D[7:4]

1 Clock Data out 2 Clocks

1 Clock 1 Clock

1 Clock

13.2 Write Cycle Timing Diagram

T

CYC

CLK

#RESET

T

#LFRAM

SU HD

Memory

Write

TAR

Sync

0000b

Address

Next Start

0000b

Start

Data

D[7:4]

Cycle

0000b

011Xb A[31:28] A[27:24] A[23:20] A[19:16]

LAD[3:0]

TAR

A[7:4]

1111b

A[15:12] A[11:8]

A[3:0]

Tri-State

D[3:0]

2 Clocks

1 Clock

1 Clock 1 Clock

Load Address in 8 Clocks

Load Data in 2 Clocks

1 Clock

Publication Release Date: April 14, 2005

Revision A3

- 24 -

W39V040B

Timing Waveforms, for LPC Interface Mode, continued

13.3 Program Cycle Timing Diagram

CLK

#RESET

#LFRAM

Memory

Write

Start next

Data

TAR

Sync

Address

XXXXb

Cycle

command

1st Start

0000b

1111b

Load Data "AA" in 2 Clocks

0000b

TAR

XXXXb

Tri-State

LAD[3:0]

011Xb

XXXXb

0101b

1010b

XXXXb

X101b

2 Clocks

1 Clock

1 Clock 1 Clock

Load Address "5555" in 8 Clocks

1 Clock

Write the 1st command to the device in LPC mode.

CLK

#RESET

#LFRAM

LAD[3:0]

Memory

Write

Start next

command

Data

TAR

Address

XXXXb

Sync

0000b

Cycle

2nd Start

0000b

TAR

XXXXb

1111b

2 Clocks

011Xb

XXXXb

1010b

0101b

Tri-State

XXXXb

X010b

Load Data "55"

in 2 Clocks

1 Clock

1 Clock 1 Clock

Load Address "2AAA" in 8 Clocks

1 Clock

Write the 2nd command to the device in LPC mode.

CLK

#RESET

#LFRAM

LAD[3:0]

Memory

Write

Start next

command

Data

TAR

Sync

0000b

Address

Cycle

3rd Start

0000b

TAR

XXXXb

0000b

1010b

1111b

Tri-State

011Xb

XXXXb

0101b

XXXXb

X101b

Load Data "A0"

in 2 Clocks

2 Clocks

1 Clock

1 Clock 1 Clock

Load Address "5555" in 8 Clocks

1 Clock

Write the 3rd command to the device in LPC mode.

CLK

#RESET

#LFRAM

LAD[3:0]

Internal

program start

Memory

Write

Address

A[19:16]

Data

TAR

Sync

0000b

4th Start Cycle

0000b

011Xb

A[31:28]

A[27:24]

A[23:20]

TAR

Internal

D[3:0]

D[7:4]

1111b

2 Clocks

A[15:12]

A[11:8]

A[7:4]

A[3:0]

Tri-State

program start

Load Din in 2 Clocks

1 Clock

1 Clock 1 Clock

Load Ain in 8 Clocks

Write the 4th command(target location to be programmed) to the device in LPC mode.

Publication Release Date: April 14, 2005

Revision A3

- 25 -

W39V040B

Timing Waveforms for LPC Interface Mode, continued

13.4 #DATA Polling Timing Diagram

CLK

#RESET

#LFRAM

Memory

Write

Start next

Data

TAR

Sync

Address

A[19:16]

Cycle

command

1st Start

0000b

Dn[3:0] Dn[7:4]

TAR

An[15:12]

An[7:4]

An[3:0]

1111b

2 Clocks

0000b

LAD[3:0]

011Xb

A[31:28]

XXXXb

An[31:28]

A[27:24]

XXXXb

An[27:24]

A[23:20]

An[11:8]

Tri-State

Load Data "Dn"

in 2 Clocks

1 Clock

1 Clock 1 Clock

Load Address "An" in 8 Clocks

Write the last command(program or erase) to the device in LPC mode.

CLK

#RESET

#LFRAM

LAD[3:0]

Memory

Read

Address

TAR

Tri-State

Next Start

0000b

Start

Sync

Data

Cycle

0000b

XXAn[17:16]

An[3:0]

XXXXb

An[15:12]

An[11:8]

An[7:4]

010Xb

1111b

0000b

XXXXb Dn7,xxx

2 Clocks

Read the DQ7 to see if the internal write complete or not.

1 Clock

Data out 2 Clocks

1 Clock 1 Clock

Load Address in 8 Clocks

1 Clock

CLK

#RESET

#LFRAM

LAD[3:0]

Memory

Read

Start

Address

An[19:16]

TAR

Next Start

0000b

Sync

Data

Cycle

0000b

010Xb

Tri-State 0000b

XXXXb

1 Clock

Data out 2 Clocks

Dn7,xxx

An[23:20]

An[15:12]

An[11:8]

An[7:4]

An[3:0]

1111b

1 Clock

2 Clocks

When internal write complete, the DQ7 will equal to Dn7.

Load Address in 8 Clocks

1 Clock

Publication Release Date: April 14, 2005

Revision A3

- 26 -

W39V040B

Timing Waveforms for LPC Interface Mode, continued

13.5 Toggle Bit Timing Diagram

CLK

#RESET

#LFRAM

Memory

Write

Start next

Data

Dn[3:0] Dn[7:4]

TAR

Sync

Address

Cycle

command

1st Start

0000b

XXAn[17:16]

An[7:4]

An[3:0]

An[15:12]

TAR

LAD[3:0]

011Xb

XXXXb

An[11:8]

1111b

Tri-State

0000b

XXXXb

Load Data "Dn"

in 2 Clocks

2 Clocks

1 Clock

1 Clock 1 Clock

Load Address "An" in 8 Clocks

1 Clock

Write the last command(program or erase) to the device in LPC mode.

CLK

#RESET

#LFRAM

LAD[3:0]

Memory

Read

Address

XXXXb

TAR

Next Start

0000b

Start

Data

X,D6,XXb

XXXXb

Sync

Cycle

0000b

010Xb

XXXXb

1111b

Tri-State 0000b

2 Clocks

Read the DQ6 to see if the internal write complete or not.

1 Clock Data out 2 Clocks

1 Clock 1 Clock

Load Address in 8 Clocks

1 Clock

CLK

#RESET

#LFRAM

LAD[3:0]

Memory

Read

Start

Address

XXXXb

TAR

Next Start

0000b

Sync

Data

X,D6,XXb

Cycle

0000b

010Xb

XXXXb

Tri-State 0000b

XXXXb

1111b

XXXXb

1 Clock Data out 2 Clocks

1 Clock

2 Clocks

When internal write complete, the DQ6 will stop toggle.

Load Address in 8 Clocks

1 Clock

Publication Release Date: April 14, 2005

Revision A3

- 27 -

W39V040B

Timing Waveforms for LPC Interface Mode, continued

13.6 Sector Erase Timing Diagram

CLK

#RESET

#LFRAM

Memory

Write

Start next

command

Data

1010b 1010b

TAR

Tri-State

2 Clocks

Sync

Cycle

Address

XXXXb

1st Start

0000b

1111b

0000b

TAR

LAD[3:0]

XXXXb

011Xb

XXXXb

0101b

XXXXb

X101b

Load Data "AA"

in 2 Clocks

1 Clock

1 Clock 1 Clock

Load Address "5555" in 8 Clocks

1 Clock

Write the 1st command to the device in LPC mode.

CLK

#RESET

#LFRAM

LAD[3:0]

Memory

Write

Start next

command

Address

XXXXb

Data

0101b 0101b

TAR

Sync

Cycle

2nd Start

0000b

TAR

XXXXb

1111b

2 Clocks

0000b

Tri-State

011Xb

XXXXb

1010b

XXXXb

X010b

Load Data "55"

in 2 Clocks

Load Address "2AAA" in 8 Clocks

1 Clock

1 Clock 1 Clock

Write the 2nd command to the device in LPC mode.

CLK

#RESET

#LFRAM

LAD[3:0]

Memory

Write

Start next

command

Data

TAR

1111b

2 Clocks

Sync

Cycle

Address

3rd Start

0000b

011Xb

0000b

TAR

XXXXb

Tri-State

XXXXb

0101b

0101b 0000b

1000b

XXXXb

X101b

Load Data "80"

in 2 Clocks

1 Clocks

1 Clocks1 Clocks

Load Address "5555" in 8 Clocks

1 Clocks

Write the 3rd command to the device in LPC mode.

CLK

#RESET

#LFRAM

LAD[3:0]

Memory

Write

Start next

command

Address

XXXXb

Data

1010b

TAR

Sync

4th Start Cycle

0000b

011Xb

TAR

XXXXb

1111b

2 Clocks

0000b

XXXXb

0101b

1010b

Tri-State

XXXXb

X101b

Load Data "AA"

in 2 Clocks

1 Clock

Load Address "5555" in 8 Clocks

1 Clock

Write the 4th command to the device in LPC mode.

CLK

#RESET

#LFRAM

LAD[3:0]

Memory

Write

Start next

command

Data

TAR

1111b

2 Clocks

Sync

Address

5th Start Cycle

TAR

0000b

011Xb

0000b

XXXXb

Tri-State

XXXXb XXXXb

XXXXb

X010b

1010b

0101b

1010b

Load Data "55"

in 2 Clocks

1 Clock

1 Clock 1 Clock

Load Address "2AAA" in 8 Clocks

1 Clock

Write the 5th command to the device in LPC mode.

CLK

#RESET

Internal

#LFRAM

LAD[3:0]

erase start

Memory

Write

Address

SA[18:16]

Data

0011b

TAR

Sync

Cycle

6th Start

0000b

Internal

TAR

XXXXb

0000b

1111b

Tri-State

0000b

XXXXb XXXXb XXXXb

011Xb

XXXXb

erase start

Load Data "30"

in 2 Clocks

2 Clocks

1 Clock

1 Clock 1 Clock

Load Sector Address in 8 Clocks

Write the 6th command(target sector to be erased) to the device in LPC mode.

Publication Release Date: April 14, 2005

Revision A3

- 28 -

W39V040B

Timing Waveforms for LPC Interface Mode, continued

13.7 FGPI Register/Product ID Readout Timing Diagram

CLK

#RESET

#LFRAM

Memory

Read

Address

XXXXb

TAR

Tri-State

2 Clocks

Next Start

0000b

Start

Data

Sync

Cycle

0000b

0001b

D[3:0]

D[7:4]

TAR

1111b

1110b

0000b

LAD[3:0]

010Xb

1111b

1011b

1111b

0000b

Load Address "FFBC0100(hex)" in 8 Clocks

& "FFBC0000(hex)/FFBC0001(hex) for product ID

1 Clock Data out 2 Clocks

1 Clock 1 Clock

1 Clock

Note: Read the DQ[4:0] to capture the states(High or Low) of the GPI[4:0] input pins. The DQ[7:5] are reserved bits.

13.8 Reset Timing Diagram

VDD

CLK

T

PRST

T

KRST

T

RSTP

#RESET

T

RST

T

RST

LAD[3:0]

#LFRAM

Publication Release Date: April 14, 2005

Revision A3

- 29 -

W39V040B

14. ORDERING INFORMATION

ACCESS

POWER SUPPLY

STANDBY VDD

CURRENT MAX.

TIME

(nS)

CURRENT MAX.

PART NO.

PACKAGE

(mA)

30

(mA)

W39V040BP

W39V040BQ

11

10

32L PLCC

32L STSOP

32L PLCC

Lead free

W39V040BPZ

W39V040BQZ

11

30

10

32L STSOP

Lead free

Notes:

1. Winbond reserves the right to make changes to its products without prior notice.

2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in

applications where personal injury might occur as a consequence of product failure.

15. HOW TO READ THE TOP MARKING

Example: The top marking of 32-pin STSOP W39V040BQZ

W39V040BQZ

2138977A-A12

345OBFA

1^stline: Winbond logo

2^ndline: the part number: W39V040BQZ (Z: Lead free part)

3^rdline: the lot number

4^thline: the tracking code: 345 O B FA

149: Packages made in ’03, week 45

O: Assembly house ID: A means ASE, O means OSE, ...etc.

B: ic revision; A means version A, B means version B, ...etc.

FA: Process code

Publication Release Date: April 14, 2005

- 30 -

Revision A3

W39V040B

16. PACKAGE DIMENSIONS

16.1 32L PLCC

Dimension in Inches

Min. Nom. Max. Min. Nom. Max.

Dimension in mm

Symbol

H _E

E

0.140

3.56

A

0.020

0.105

0.026

0.016

0.008

0.50

2.67

0.66

0.41

0.20

A

b

1

2

1

4

1

32

30

0.110

0.028

0.018

0.010

0.550

0.450

0.050

0.510

0.410

0.590

0.490

0.090

0.115

0.032

0.022

0.014

2.80

0.71

2.93

0.81

0.56

0.35

0.46

b

5

29

0.25

c

0.547

0.447

0.044

0.490

0.390

0.585

0.485

0.075

0.553

0.453

0.056

0.530

0.430

0.595

0.495

0.095

0.004

13.89

11.35

1.12

14.05

11.51

1.42

13.97

11.43

1.27

D

E

e

12.45

9.91

12.95

13.46

10.92

15.11

12.57

2.41

G

H

D

G ^D

10.41

14.99

12.45

2.29

E

D

E

D

H^D

14.86

12.32

1.91

L

0.10

y

0

10

0

10

θ

21

13

Notes:

1. Dimensions D & E do not include interlead flash.

2. Dimension b1 does not include dambar protrusion/intrusio

3. Controlling dimension: Inches

14

20

c

4. General appearance spec. should be based on final

visual inspection sepc.

L

A²

A

θ

e

1

b

b1

Seating Plane

y

E

G

16.2 32L STSOP

H_D

D

c

Dimension in Inches Dimension in mm

Symbol

Max.

1.20

Min. Nom. Max. Min. Nom.

e

0.047

A

0.002

0.035

0.006

0.041

0.05

0.95

0.17

0.10

0.15

1

A

E

2

0.040

1.00

0.22

A

1.05

0.27

b

0.007 0.009 0.010

b

0.004

0.008

-----

12.40

8.00

0.21

-----

0.488

c

D

E

H

0.315

0.551

0.020

14.00

D

0.50

0.60

0.80

e

0.50

0.70

0.020 0.024 0.028

0.031

L

θ

1

L

A

¹A

2

0.000

0.004

0.00

0

0.10

5

L

Y

0

3

5

3

θ

L

1

Publication Release Date: April 14, 2005

Revision A3

- 31 -

W39V040B

17. VERSION HISTORY

VERSION

DATE

PAGE

DESCRIPTION

A1

Nov. 26, 2004

-

Initial Issued

Delete 7.3 ~ 7.7 item

A2

A3

Jan.25, 2005

April 14, 2005

P8, P9, P10

P32

Block lock relate description

Add important notice

Important Notice

Winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment

intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation

instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or

sustain life. Further more, Winbond products are not intended for applications wherein failure of Winbond products

could result or lead to a situation wherein personal injury, death or severe property or environmental damage could

occur.

Winbond customers using or selling these products for use in such applications do so at their own risk and agree to

fully indemnify Winbond for any damages resulting from such improper use or sales.

Headquarters

Winbond Electronics Corporation America Winbond Electronics (Shanghai) Ltd.

27F, 2299 Yan An W. Rd. Shanghai,

200336 China

No. 4, Creation Rd. III,

Science-Based Industrial Park,

Hsinchu, Taiwan

2727 North First Street, San Jose,

CA 95134, U.S.A.

TEL: 1-408-9436666

TEL: 86-21-62365999

FAX: 86-21-62365998

TEL: 886-3-5770066

FAX: 1-408-5441798

FAX: 886-3-5665577

http://www.winbond.com.tw/

Taipei Office

Winbond Electronics Corporation Japan

7F Daini-ueno BLDG, 3-7-18

Shinyokohama Kohoku-ku,

Yokohama, 222-0033

Winbond Electronics (H.K.) Ltd.

Unit 9-15, 22F, Millennium City,

No. 378 Kwun Tong Rd.,

Kowloon, Hong Kong

9F, No.480, Rueiguang Rd.,

Neihu District, Taipei, 114,

Taiwan, R.O.C.

TEL: 886-2-8177-7168

FAX: 886-2-8751-3579

TEL: 81-45-4781881

TEL: 852-27513100

FAX: 81-45-4781800

FAX: 852-27552064

Please note that all data and specifications are subject to change without notice.

All the trade marks of products and companies mentioned in this data sheet belong to their respective owners.

Publication Release Date: April 14, 2005

Revision A3

- 32 -

型号:	W39V040BQ
是否Rohs认证：	不符合
生命周期：	Obsolete
零件包装代码：	TSOP
包装说明：	STSOP-32
针数：	32
Reach Compliance Code：	not_compliant
ECCN代码：	EAR99
HTS代码：	8542.32.00.51
风险等级：	5.91
最长访问时间：	11 ns
其他特性：	SYNCHRONOUS BURST MODE ALSO POSSIBLE
启动块：	TOP
命令用户界面：	NO
数据轮询：	YES
JESD-30 代码：	R-PDSO-G32
JESD-609代码：	e0
长度：	12.4 mm
内存密度：	4194304 bit
内存集成电路类型：	FLASH
内存宽度：	8
功能数量：	1
部门数/规模：	8
端子数量：	32
字数：	524288 words
字数代码：	512000
工作模式：	ASYNCHRONOUS
最高工作温度：	70 °C
最低工作温度：
组织：	512KX8
封装主体材料：	PLASTIC/EPOXY
封装代码：	TSSOP
封装等效代码：	TSSOP32,.56,20
封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
并行/串行：	PARALLEL
峰值回流温度（摄氏度）：	240
电源：	3.3 V
编程电压：	3.3 V
认证状态：	Not Qualified
就绪/忙碌：	YES
座面最大高度：	1.2 mm
部门规模：	64K
最大待机电流：	0.00005 A
子类别：	Flash Memories
最大压摆率：	0.03 mA
最大供电电压 (Vsup)：	3.6 V
最小供电电压 (Vsup)：	3 V
标称供电电压 (Vsup)：	3.3 V
表面贴装：	YES
技术：	CMOS
温度等级：	COMMERCIAL
端子面层：	Tin/Lead (Sn/Pb)
端子形式：	GULL WING
端子节距：	0.5 mm
端子位置：	DUAL
处于峰值回流温度下的最长时间：	30
切换位：	YES
类型：	NOR TYPE
宽度：	8 mm
Base Number Matches：	1

电子百科

产品导航

产品型号W39V040BPZ的概述

产品型号W39V040BPZ的Datasheet PDF文件预览

W39V040BPZ相关产品

W39V040BPZ相关文章

IC37:专业IC行业平台