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产品型号W49F002UP12B的概述

芯片W49F002UP12B概述 W49F002UP12B是一款广泛应用于嵌入式系统和消费电子产品中的高速Flash存储器。作为一款具有高性能和高容量特性的存储芯片，W49F002UP12B在存储数据和程序时提供了更为便利的解决方案。这款芯片具有200万字节的存储容量，可用于各种需要非易失性存储的场景，尤其适合微控制器和其他嵌入式系统中使用。芯片的详细参数 W49F002UP12B的关键技术参数包括： - 存储容量：容量为2 Mbit，等同于256 K字节。 - 存取时间：芯片提供的随机存取时间可达到70ns，这使得其在高速读写操作中表现出色。 - 电源电压：工作电压范围为2.7V至3.6V，使其适合于多种低功耗应用。 - 编程时间：编程时间为20µs，支持多次编程及数据更新。 - 擦除时间：整片擦除时间约为300ms。 - 耐磨性：支持最低10,000次的擦写周期，确保其在长时间使...

产品型号W49F002UP12B的Datasheet PDF文件预览

W49F002U

256K ´ 8 CMOS FLASH MEMORY

GENERAL DESCRIPTION

The W49F002U is a 2-megabit, 5-volt only CMOS flash memory organized as 256K 8 bits. The

device can be programmed and erased in-system with a standard 5V power supply. A 12-volt V is

not required. The unique cell architecture of the W49F002U results in fast program/erase operations

with extremely low current consumption (compared to other comparable 5-volt flash memory

products). The device can also be programmed and erased using standard EPROM programmers.

FEATURES

Two Main Memory Blocks (96K, 128K) Bytes

Low power consumption

Single 5-volt operations:

5-volt Read

5-volt Erase

5-volt Program

Active current: 25 mA (typ.)

Standby current: 20 A (typ.)

Automatic program and erase timing with

Fast Program operation:

internal V generation

- Byte-by-Byte programming: 35 mS (typ.)

End of program or erase detection

Fast Erase operation: 100 mS (typ.)

Fast Read access time: 70/90/120 nS

Endurance: 10K cycles (typ.)

Ten-year data retention

Toggle bit

Data polling

Latched address and data

Hardware data protection

TTL compatible I/O

One 16K byte Boot Block with Lockout

protection

JEDEC standard byte-wide pinouts

Available packages: 32-pin DIP and 32-pin

TSOP and 32-pin-PLCC

Two 8K byte Parameter Blocks

Publication Release Date: April 2000

Revision A2

- 1 -

W49F002U

PIN CONFIGURATIONS

BLOCK DIAGRAM

RESET

V_DD

A16

A15

A17

A14

A12

DQ0

A13

OUTPUT

BUFFER

CONTROL

DQ7

32-pin

DIP

A11

RESET

A10

DQ7

3FFFF

BOOT BLOCK

DQ0

DQ6

DQ5

DQ4

DQ3

16K BYTES

3C000

3BFFF

DQ1

DQ2

GND

PARAMETER

BLOCK1

DECODER

3A000

39FFF

8K BYTES

PARAMETER

BLOCK2

A17

8K BYTES

38000

37FFF

MAIN MEMORY

BLOCK1

96K BYTES

20000

31 30

1FFFF

MAIN MEMORY

BLOCK2

A14

A13

00000

128K BYTES

32-pin

PLCC

A11

A10

DQ7

DQ0

14 15 16 17 18 19 20

PIN DESCRIPTION

SYMBOL

PIN NAME

A10

A11

A13

A14

A17

Reset

RESET

DQ7

DQ6

DQ5

DQ4

DQ3

GND

Address Inputs

Data Inputs/Outputs

Chip Enable

A0 A17

VDD

DQ0 DQ7

32-pin

TSOP

RESET

A16

DQ2

DQ1

DQ0

A15

A12

Output Enable

Write Enable

Power Supply

Ground

GND

- 2 -

W49F002U

FUNCTIONAL DESCRIPTION

Read Mode

, both of which have to be low for

The read operation of the W49F002U is controlled by

and

the host to obtain data from the outputs.

is used for device selection. When

is high, the chip

is de-selected and only standby power will be consumed.

is the output control and is used to gate

is high.

data from the output pins. The data bus is in high impedance state when either

Refer to the timing waveforms for further details.

Reset Operation

The reset input pin can be used in some application. When RESET pin is at high state, the device is

RESET

in normal operation mode. When

pin is at low state, it will halts the device and all outputs are

at high impedance state. As the high state re-asserted to the RESET pin, the device will return to

read or standby mode, it depends on the control signals. When the system drives the RESET pin low

for at least a period of 500 nS, the device immediately terminates any operation in progress duration

of the RESET pulse. The other function for RESET pin is temporary reset the boot block. By

RESET

applying the 12V to

pin, the boot block can be reprogrammed even though the boot block

lockout function is enabled.

Boot Block Operation

There is one 16K-byte boot block in this device, which can be used to store boot code. It is located in

the last 16K bytes with the address range of the boot block is 3C000(hex) to 3FFFF(hex).See

Command Code sequence for Boot Block Lockout Enable for the specific code. Once this feature is

set the data for the designated block cannot be erased or programmed (programming lockout); other

memory locations can be changed with the regular programming method. Once the boot block

programming lockout feature is activated, the chip erase function can no longer erase the boot block.

RESET

There is one condition that the lockout feature can be overridden. Just apply 12V to

lockout feature will temporarily be inactivated and the block can be erased/programmed. Once the

RESET

pin, the

pin return to TTL level, the lockout feature will be activated again.

In order to detect whether the boot block feature is set on the 16K-bytes block, users can perform

software command code sequence: enter the product identification mode (see Command Codes for

Identification/Boot Block Lockout Detection for specific code), and then read from address "0002

(hex)". If the DQ of output data is "1," the boot block programming lockout feature is activated; if the

DQ0

output data is "0 ," the lockout feature is inactivated and the block can be

erased/programmed.

To return to normal operation, perform a three-byte command code sequence (or an alternate single-

byte command) to exit the identification mode. For the specific code, see Command Code for

Identification/Boot Block Lockout Detection.

Chip Erase Operation

The chip-erase mode can be initiated by a six-byte command code sequence. After the command

loading cycle, the device enters the internal chip erase mode, which is automatically timed and will be

completed as fast as 100 mS (typical). The host system is not required to provide any control or

timing during this operation. The entire memory array will be erased to FF hex. by the chip erase

Publication Release Date: April 2000

- 3 -

Revision A2

W49F002U

operation if the boot block programming lockout feature is not activated. Once the boot block lockout

feature is activated, the whole chip erase function will erase the two main memory blocks and the two

parameter blocks but not the boot block. The device will automatically return to normal read mode

after the erase operation. Data polling and/or Toggle Bits can be used to detect end of erase cycle.

Sector Erase Operation

There are four sectors: two main memory blocks and two parameters blocks which can be erased

individually by initiating a six-byte command code sequence. Sector address is latched on the falling

signal in the sixth cycle while the data input "30(hex)" is latched at the rising edge of

edge of

in this cycle. After the command loading cycle, the device enters the internal sector erase mode,

which is automatically timed and will be completed as fast as 100 mS (typical). The host system does

not require to provide any control or timing during this operation. The device will automatically return

to normal read mode after the erase operation. Data polling and/or Toggle Bits can be used to detect

the end of erase cycle.

When different sector address is loaded in the sixth cycle for sector erase command, the

correspondent sectors will be erased automatically; that these sections will be erased independedntly.

Table of Command Definition

For detail sector to be erased information, please refer to the

Program Operation

The W49F002U is programmed on a byte-by-byte basis. Program operation can only change logical

data "1" to logical data "0". The erase operation (changed entire data in two main memory blocks and

two parameter blocks and/or boot block from "0" to "1") is needed before programming.

The program operation is initiated by a 4-byte command code sequence (see Command Codes for

Byte Programming). The device will internally enter the program operation immediately after the byte-

program command is entered. The internal program timer will automatically time-out (50 S max. -

). Once completed, the device returns to normal read mode. Data polling and/or Toggle Bits can

be used to detect end of program cycle.

Hardware Data Protection

The integrity of the data stored in the W49F002U is also hardware protected in the following ways:

(1) Noise/Glitch Protection: A

pulse of less than 15 nS in duration will not initiate a write cycle.

(2) V Power Up/Down Detection: The programming operation is inhibited when V is less than

2.5V typical.

high will inhibit the write operation. This

(3) Write Inhibit Mode: Forcing

low,

high, or

prevents inadvertent writes during power-up or power-down periods.

(4) V power-on delay: When V has reached its sense level, the device will automatically time-out

5 mS before any write (erase/program) operation.

Data Polling (DQ )- Write Status Detection

The W49F002U includes a data polling feature to indicate the end of a program or erase cycle.

When the W49F002U is in the internal program or erase cycle, any attempt to read DQ of the last

byte loaded will receive the complement of the true data. Once the program or erase cycle is

completed, DQ will show the true data. Note that DQ will show logical "0" during the erase cycle,

and become logical "1" or true data when the erase cycle has been completed.

- 4 -

W49F002U

Toggle Bit (DQ6)- Write Status Detection

In addition to data polling, the W49F002U provides another method for determining the end of a

program cycle. During the internal program or erase cycle, any consecutive attempts to read DQ will

produce alternating 0's and 1's. When the program or erase cycle is completed, this toggling between

0's and 1's will stop. The device is then ready for the next operation.

Product Identification

The product ID operation outputs the manufacturer code and device code. Programming equipment

automatically matches the device with its proper erase and programming algorithms.

The manufacturer and device codes can be accessed by software or hardware operation. In the

software access mode, a three-byte (or JEDEC 3-byte) command sequence can be used to access

the product ID. A read from address 0000H outputs the manufacturer code DA(hex). A read from

address 0001H outputs the device code 0B(hex). The product ID operation can be terminated by a

three-byte command code sequence or an alternate one-byte command code sequence (see

Command Definition table).

low,

In the hardware access mode, access to the product ID is activated by forcing

high, and raising A9 to 12 volts.

and

TABLE OF OPERATING MODES

Operating Mode Selection

(V = 12V

5 )

MODE

PINS

ADDRESS

DQ.

RESET

CE OE WE

Read

Write

Dout

Din

Standby

High Z

Write Inhibit

High Z/DOUT

High Z

Output Disable

Reset Mode

Product ID

High Z

Manufacturer Code DA (Hex)

A0 = V ; A1- A17 = V ;

A9 = V

Device Code 0B (Hex)

A0 = V ; A1- A17 = V ;

A9 = V

Publication Release Date: April 2000

Revision A2

- 5 -

W49F002U

TABLE OF COMMAND DEFINITION⁽¹⁾

COMMAND

NO.

1ST

CYCLE

2ND

CYCLE

3RD

CYCLE

4TH

CYCLE

5TH

CYCLE

6TH

CYCLE

Cycles Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data

DESCRIPTION

IN OUT

Read

Chip Erase

5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 10

5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 SA⁽³⁾30

Sector Erase

Byte Program

5555 AA 2AAA 55 5555 A0 A

Boot Block Lockout

Product ID Entry

Product ID Exit ⁽²⁾

5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 40

5555 AA 2AAA 55 5555 90

5555 AA 2AAA 55 5555 F0

XXXX F0

Product ID Exit ⁽²⁾

Notes:

1. Address Format: A14 A0 (Hex); Data Format: DQ7-DQ0 (Hex)

2. Either one of the two Product ID Exit commands can be used.

3. SA means: Sector Address

If SA is within 3C000 to 3FFFF (Boot Block address range), and the Boot Block programming lockout feature is activated,

nothing will happen and the device will go back to read mode after 100nS.

If the Boot Block programming lockout feature is not activated, this command will erase Boot Block.

If SA is within 3A000 to 3BFFF (Parameter Block1 address range), this command will erase PB1.

If SA is within 38000 to 39FFF (Parameter Block2 address range), this command will erase PB2.

If SA is within 20000 to 37FFF (Main Memory Block1 address range), this command will erase MMB1.

If SA is within 00000 to 1FFFF (Main Memory Block2 address range), this command will erase MMB2.

- 6 -

W49F002U

Command Codes for Byte Program

COMMAND SEQUENCE

ADDRESS

5555H

DATA

AAH

55H

0 Write

1 Write

2 Write

3 Write

2AAAH

5555H

A0H

Programmed-address

Programmed-data

Byte Program Flow Chart

Byte Program

Command Flow

Load data AA

address 5555

Load data 55

address 2AAA

Load data A0

address 5555

Load data Din

programmed-

address

Pause T_BP

Exit

Notes for software program code:

Data Format: DQ7 DQ0 (Hex)

Address Format: A14 A0 (Hex)

Publication Release Date: April 2000

Revision A2

- 7 -

W49F002U

Command Codes for Chip Erase

BYTE SEQUENCE

1 Write

ADDRESS

5555H

DATA

AAH

55H

2 Write

2AAAH

5555H

3 Write

80H

4 Write

5555H

AAH

55H

5 Write

2AAAH

5555H

6 Write

10H

Chip Erase Acquisition Flow

Load data AA

address 5555

Load data 55

address 2AAA

Load data 80

address 5555

Load data AA

address 5555

Load data 55

address 2AAA

Load data 10

address 5555

Pause T

Exit

Notes for chip erase:

Data Format: DQ7 DQ0 (Hex)

Address Format: A14 A0 (Hex)

- 8 -

W49F002U

Command Codes for Sector Erase

BYTE SEQUENCE

1 Write

ADDRESS

5555H

2AAAH

5555H

2AAAH

SA*

DATA

AAH

55H

2 Write

3 Write

80H

4 Write

AAH

55H

5 Write

6 Write

30H

Sector Erase Acquisition Flow

Load data AA

address 5555

Load data 55

address 2AAA

Load data 80

address 5555

Load data AA

address 5555

Load data 55

address 2AAA

Load data 30

address SA*

Pause T

Exit

Notes for chip erase:

Data Format: DQ7 DQ0 (Hex)

Address Format: A14 A0 (Hex)

SA : For details, see the page 6 .

Publication Release Date: April 2000

Revision A2

- 9 -

W49F002U

Command Codes for Product Identification and Boot Block Lockout Detection

BYTE

SEQUENCE

SOFTWARE PRODUCT

IDENTIFICATION/BOOT BLOCK

LOCKOUT DETECTION ENTRY

SOFTWARE PRODUCT

IDENTIFICATION/BOOT BLOCK

LOCKOUT DETECTION EXIT(6)

ADDRESS

5555

DATA

ADDRESS

5555H

DATA

AAH

55H

1 Write

2 Write

3 Write

2AAA

2AAAH

5555H

5555

F0H

Pause 10 mS

Software Product Identification and Boot Block Lockout Detection Acquisition Flow

Product

Identification

Entry (1)

Product

Identification Exit(6)

Identification

and Boot Block

Lockout Detection

Mode (3)

Load data AA

address 5555

(2)

Load data 55

address 2AAA

Load data 55

address 2AAA

Read address = 0000

data = DA

(2)

(4)

Load data 90

Load data F0

Read address = 0001

address 5555

Read address = 0002

data =in DQ0= "1" / "0"

Pause 10

(5)

Normal Mode

Notes for software product identification/boot block lockout detection:

(1) Data Format: DQ7 DQ0 (Hex); Address Format: A14 A0 (Hex)

(2) A1 A17 = VIL; manufacture code is read for A0 = VIL; device code is read for A0 = VIH.

(3) The device does not remain in identification and boot block lockout detection mode if power down.

(4) If the output data in DQ0= " 1 " the boot block programming lockout feature is activated; if the output data in DQ0 = " 0 ,"

the lockout feature is inactivated and the boot block can be programmed.

(5) The device returns to standard operation mode.

(6) Optional 1-byte cycle (write F0 hex at XXXX address) can be used to exit the product identification/boot block lockout

detection.

- 10 -

W49F002U

Command Codes for Boot Block Lockout Enable

BYTE SEQUENCE

0 Write

ADDRESS

5555H

DATA

AAH

55H

1 Write

2AAAH

5555H

2 Write

80H

3 Write

5555H

AAH

55H

4 Write

2AAAH

5555H

5 Write

40H

Pause T

Boot Block Lockout Enable Acquisition Flow

Boot Block Lockout

Feature Set Flow

Load data AA

address 5555

Load data 55

address 2AAA

Load data 80

address 5555

Load data AA

address 5555

Load data 55

address 2AAA

Load data 40

address 5555

Pause T

Exit

Notes for boot block lockout enable:

Data Format: DQ7 DQ0 (Hex)

Address Format: A14 A0 (Hex)

Publication Release Date: April 2000

Revision A2

- 11 -

W49F002U

DC CHARACTERISTICS

Absolute Maximum Ratings

PARAMETER

RATING

UNIT

Power Supply Voltage to V Potential

-0.5 to +7.0

0 to +70

°C

Operating Temperature

Storage Temperature

-65 to +150

-0.5 to V +1.0

D.C. Voltage on Any Pin to Ground Potential except

Transient Voltage (<20 nS ) on Any Pin to Ground Potential

-1.0 to V +1.0

-0.5 to 12.5

Voltage on

Pin to Ground Potential

Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the

device.

DC Operating Characteristics

(VDD = 5.0V 10 , VSS = 0V, TA = 0 to 70 C)

PARAMETER

SYM.

TEST CONDITIONS

LIMITS

MIN. TYP.

UNIT

MAX.

Power Supply

Current

CE OE

= V ,

= V , all DQs open

IL IH

Address inputs = V /V , at f = 5 MHz

Standby V

= V , all DQs open

Current (TTL input)

IL IH

Other inputs = V /V

Standby V

100

= V -0.3V, all DQs open

Current

Other inputs = V -0.3V/GND

(CMOS input)

= GND to V

Input Leakage

Current

OUT

= GND to V

Output Leakage

Current

Input Low Voltage

Input High Voltage

Output Low Voltage

Output High Voltage

-0.3

2.0

0.8

+0.5

= 2.1 mA

0.45

= -0.4 mA

2.4

- 12 -

W49F002U

Power-up Timing

PARAMETER

SYMBOL

TYPICAL

UNIT

Power-up to Read Operation

Power-up to Write Operation

. READ

100

. WRITE

CAPACITANCE

(VDD = 5.0V, TA = 25 C, f = 1 MHz)

PARAMETER

I/O Pin Capacitance

Input Capacitance

SYMBOL

CONDITIONS

MAX.

UNIT

I/O

= 0V

AC CHARACTERISTICS

AC Test Conditions

PARAMETER

Input Pulse Levels

CONDITIONS

0V to 3.0V

< 5 nS

Input Rise/Fall Time

Input/Output Timing Level

Output Load

1.5V/1.5V

1 TTL Gate and C = 100 pF for 120 nS;

C = 30 pF for 70 nS /90 nS

AC Test Load and Waveform

+5V

1.8K

OUT

30 pF for 70nS / 90nS

100 pF for 120nS

(Including Jig and Scope)

1.3K

Input

Output

1.5V

Test Point

Publication Release Date: April 2000

Revision A2

- 13 -

W49F002U

AC Characteristics, continued

Read Cycle Timing Parameters

(VCC = 5.0V 10 , VCC = 0V, TA = 0 to 70 C)

PARAMETER

SYM. W49F002U-70 W49F002U-90 W49F002U-120 UNIT

MIN. MAX. MIN. MAX. MIN. MAX.

Read Cycle Time

120

Chip Enable Access Time

Address Access Time

Output Enable Access Time

120

CLZ

CE Low to Active Output

OE Low to Active Output

OLZ

CHZ

High to High-Z Output

OHZ

Output Hold from Address Change

Write Cycle Timing Parameters

PARAMETER

Address Setup Time

SYMBOL

MIN.

TYP.

MAX.

UNIT

Address Hold Time

and CE Setup Time

and CE Hold Time

High Setup Time

OES

OEH

OE High Hold Time

CE Pulse Width

100

Pulse Width

High Width

WPH

Data Setup Time

Data Hold Time

Byte Programming Time

Erase Cycle Time

0.1

0.2

Note: All AC timing signals observe the following guidelines for determining setup and hold times:

(a) High level signal's reference level is V and (b) low level signal's reference level is V .

- 14 -

W49F002U

AC Characteristics, continued

Data Polling and Toggle Bit Timing Parameters

PARAMETER

SYM. W49F002U-70 W49F002U-90 W49F002U-120 UNIT

MIN. MAX. MIN. MAX. MIN. MAX.

120

OEP

CEP

OET

CET

to Data Polling Output Delay

to Toggle Bit Output Delay

120

TIMING WAVEFORMS

Read Cycle Timing Diagram

Address A17-0

TOE

OHZ

OLZ

CLZ

CHZ

High-Z

DQ7-0

Data Valid

Publication Release Date: April 2000

Revision A2

- 15 -

W49F002U

Timing Waveforms, continued

WE Controlled Command Write Cycle Timing Diagram

Address A17-0

OES

OEH

WPH

DQ7-0

Data Valid

CE Controlled Command Write Cycle Timing Diagram

Address A17-0

TCPH

TCP

TOES

TOEH

TDS

High Z

DQ7-0

Data Valid

TDH

- 16 -

W49F002U

Timing Waveforms, continued

Program Cycle Timing Diagram

Byte Program Cycle

5555 Address

2AAA

Address A17-0

5555

Data-In

DQ7-0

TWPH

Internal Write Start

Byte 1

Byte 0

Byte 2

Byte 3

DATA Polling Timing Diagram

Address A17-0

TCEP

TOEH

OES

T_OEP

DQ7

TBP or TEC

Publication Release Date: April 2000

Revision A2

- 17 -

W49F002U

Timing Waveforms, continued

Toggle Bit Timing Diagram

Address A17-0

OES

OEH

DQ6

TBP orTEC

Boot Block Lockout Enable Timing Diagram

Six byte code for Boot Block

Lockout Feature Enable

Address A17-0

5555

2AAA

5555

2AAA

DQ7-0

WPH

SB0

SB2

SB3

SB5

SB4

SB1

- 18 -

W49F002U

Timing Waveforms, continued

Chip Erase Timing Diagram

Six-byte code for 5V-only software

chip erase

Address A17-0

5555

2AAA

5555

2AAA

DQ7-0

T_WP

SB0

T_EC

T_WPH

Internal Erase starts

SB2

SB3

SB5

SB4

SB1

Sector Erase Timing Diagram

Six-byte code for 5V-only software

Main Memory Erase

5555

2AAA

5555

2AAA

Address A17-0

DQ7-0

WPH

Internal Erase starts

SB0

SB2

SB3

SB5

SB4

SB1

SA = Sector Address

Publication Release Date: April 2000

Revision A2

- 19 -

W49F002U

ORDERING INFORMATION

PART NO.

ACCESS

TIME

POWER

SUPPLY

CURRENT

MAX.

STANDBY

VDD

CURRENT

MAX.

PACKAGE

CYCLE

(nS)

(mA)

( A)

W49F002U-70B

W49F002U-90B

W49F002U-12B

W49F002UT70B

W49F002UT90B

W49F002UT12B

W49F002UP70B

W49F002UP90B

W49F002UP12B

100 (CMOS) 32-pin DIP

10K

120

100 (CMOS)

10K

32-pin TSOP (8 mm ´ 20 mm)

120

32-pin TSOP (8 mm 20 mm)

100 (CMOS) 32-pin PLCC

120

Notes:

1. Winbond reserves the right to make changes to its products without prior notice.

2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in

applications where personal injury might occur as a consequence of product failure.

3. Winbond withholds a Boot Block options for Bottom Boot use. Please contact Winbond FAEs for detail information.

- 20 -

W49F002U

PACKAGE DIMENSIONS

32-pin P-DIP

Dimension in inches

Dimension in mm

Symbol

Min. Nom. Max. Min. Nom. Max.

0.210

5.33

0.010

0.150

0.25

3.81

0.41

1.22

A₁

0.155 0.160

3.94

0.46

1.27

0.25

4.06

0.56

1.37

0.36

0.016 0.018

0.022

0.054

0.050

0.048

0.008

0.010 0.014 0.20

1.650 1.660

41.91 42.16

E₁

e₁

15.49

14.10

2.79

0.610

15.24

0.590 0.600

14.99

13.84 13.97

0.545

0.550

0.555

0.110

0.090 0.100

2.29

2.54

3.30

0.120

0.140 3.05

0.130

3.56

0.630 0.650 0.670 16.00 16.51 17.02

0.085

e_A

2.16

Notes:

1.Dimensions D Max. & S include mold flash or

tie bar burrs.

2.Dimension E1 does not include interlead flash.

Base Plane

3.Dimensions D & E1 include mold mismatch and

are determined at the mold parting line.

4.Dimension B1 does not include dambar

protrusion/intrusion.

Seating Plane

5.Controlling dimension: Inches

6.General appearance spec. should be based on

final visual inspection spec.

e_A

32-pin PLCC

Dimension in Inches

Dimension in mm

Symbol

Min. Nom. Max. Min. Nom. Max.

H _E

0.140

3.56

0.020

0.105

0.026

0.016

0.008

0.50

2.67

0.66

0.41

0.20

A₁

A ₂

b ₁

0.110

0.028

0.018

0.010

0.550

0.450

0.050

0.51

0.115

0.032

0.022

0.014

2.80

0.71

2.93

0.81

0.56

0.35

0.46

0.25

0.547

0.447

0.044

0.490

0.390

0.585

0.485

0.075

0.553

0.453

0.056

0.530

0.430

0.595

0.495

0.095

0.004

13.89

11.35

1.12

14.05

11.51

1.42

13.97

11.43

1.27

12.9

12.45

9.91

13.46

10.92

15.11

12.57

2.41

G_D

G_E

H_D

H_E

G D

0.410

0.590

0.49

10.41

14.99

12.45

2.29

H D

14.86

12.32

1.91

0.090

0.10

Notes:

1. Dimensions D & E do not include interlead flash.

2. Dimension b1 does not include dambar protrusion/intrusion.

3. Controlling dimension: Inches

4. General appearance spec. should be based on final

visual inspection sepc.

b 1

Seating Plane

Publication Release Date: April 2000

Revision A2

- 21 -

W49F002U

Package Dimensions, continued

32-pin TSOP

H D

Dimension in Inches

Dimension in mm

Symbol

Max.

Min. Nom.

Max.

1.20

0.15

1.05

0.047

0.006

0.002

0.037

0.05

0.95

A ₁

0.041

0.009

1.00

0.20

0.039

0.007 0.008

0.17

0.12

0.23

0.17

0.005 0.006

0.720 0.724

0.15

0.007

0.728

0.10(0.004)

18.30 18.40 18.50

0.311 0.315

0.780 0.787

7.90

8.00

8.10

0.319

19.80

20.00

0.795

20.20

0.020

0.50

0.016 0.020

0.40

0.60

0.024

0.031

0.80

0.000

0.004

0.10

0.00

L₁

Note:

Controlling dimension: Millimeters

- 22 -

W49F002U

VERSION HISTORY

VERSION

DATE

PAGE

DESCRIPTION

Nov. 1999

Apr. 2000

1, 13- 15, 20

Renamed from W49F002/B/U/N

Add the 120 nS bin

Change Tbp(typ.) from 10 S to 35 S

Change Tec(max.) from 1 Sec to 0.2 Sec

Winbond Electronics (H.K.) Ltd.

Winbond Electronics North America Corp.

Headquarters

Rm. 803, World Trade Square, Tower II, Winbond Memory Lab.

123 Hoi Bun Rd., Kwun Tong,

No. 4, Creation Rd. III,

Science-Based Industrial Park,

Hsinchu, Taiwan

TEL: 886-3-5770066

FAX: 886-3-5796096

Winbond Microelectronics Corp.

Kowloon, Hong Kong

TEL: 852-27513100

FAX: 852-27552064

Winbond Systems Lab.

2727 N. First Street, San Jose,

CA 95134, U.S.A.

http://www.winbond.com.tw/

TEL: 408-9436666

FAX: 408-5441798

Voice & Fax-on-demand: 886-2-27197006

Taipei Office

11F, No. 115, Sec. 3, Min-Sheng East Rd.,

Taipei, Taiwan

TEL: 886-2-27190505

FAX: 886-2-27197502

Note: All data and specifications are subject to change without notice.

Publication Release Date: April 2000

Revision A2

- 23 -

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W49F002UP12B产品参数

型号:	W49F002UP12B
生命周期：	Obsolete
IHS 制造商：	WINBOND ELECTRONICS CORP
零件包装代码：	QFJ
包装说明：	QCCJ, LDCC32,.5X.6
针数：	32
Reach Compliance Code：	unknown
ECCN代码：	EAR99
HTS代码：	8542.32.00.51
风险等级：	5.58
Is Samacsys：	N
最长访问时间：	120 ns
其他特性：	HARDWARE DATA PROTECTION; 10-YEARS DATA RETENTION; ENDURANCE 10K CYCLES
启动块：	TOP
命令用户界面：	YES
数据轮询：	YES
数据保留时间-最小值：	10
耐久性：	10000 Write/Erase Cycles
JESD-30 代码：	R-PQCC-J32
长度：	13.97 mm
内存密度：	2097152 bit
内存集成电路类型：	FLASH
内存宽度：	8
功能数量：	1
部门数/规模：	1,2,1,1
端子数量：	32
字数：	262144 words
字数代码：	256000
工作模式：	ASYNCHRONOUS
最高工作温度：	70 °C
最低工作温度：
组织：	256KX8
封装主体材料：	PLASTIC/EPOXY
封装代码：	QCCJ
封装等效代码：	LDCC32,.5X.6
封装形状：	RECTANGULAR
封装形式：	CHIP CARRIER
并行/串行：	PARALLEL
电源：	5 V
编程电压：	5 V
认证状态：	Not Qualified
座面最大高度：	3.56 mm
部门规模：	16K,8K,96K,128K
最大待机电流：	0.0001 A
子类别：	Flash Memories
最大压摆率：	0.05 mA
最大供电电压 (Vsup)：	5.5 V
最小供电电压 (Vsup)：	4.5 V
标称供电电压 (Vsup)：	5 V
表面贴装：	YES
技术：	CMOS
温度等级：	COMMERCIAL
端子形式：	J BEND
端子节距：	1.27 mm
端子位置：	QUAD
切换位：	YES
类型：	NOR TYPE
宽度：	11.43 mm
Base Number Matches：	1

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