W78C032C40FL全新原装原理图各脚功能电路原理芯片引脚定义-中国IC网-芯三七

W78C32C/W78C032C DATA SHEET

8-BIT MICROCONTROLLER

Table of Contents-

1.

2.

3.

4.

5.

GENERAL DESCRIPTION ......................................................................................................... 2

FEATURES................................................................................................................................. 2

PIN CONFIGURATIONS ............................................................................................................ 3

PIN DESCRIPTION..................................................................................................................... 4

FUNCTIONAL DESCRIPTION ................................................................................................... 6

5.1

5.2

TIMERS 0, 1, AND 2....................................................................................................... 6

CLOCK............................................................................................................................ 6

5.2.1 CRYSTAL OSCILLATOR .................................................................................................6

5.2.2 EXTERNAL CLOCK .........................................................................................................6

5.3

POWER MANAGEMENT ............................................................................................... 6

5.3.1 IDLE MODE......................................................................................................................6

5.3.2 POWER-DOWN MODE....................................................................................................7

5.3.3 RESET .............................................................................................................................7

6.

ELECTRICAL CHARACTERISTICS........................................................................................... 8

6.1

6.2

6.3

ABSOLUTE MAXIMUM RATINGS................................................................................. 8

D.C. CHARACTERISTICS.............................................................................................. 8

A.C. CHARACTERISTICS.............................................................................................. 9

6.3.1 CLOCK INPUT WAVEFORM ...........................................................................................9

6.3.2 PROGRAM FETCH CYCLE...........................................................................................10

6.3.3 DATA READ CYCLE......................................................................................................10

6.3.4 DATA WRITE CYCLE ....................................................................................................11

6.3.5 PORT ACCESS CYCLE.................................................................................................11

7.

TIMING waveformS................................................................................................................... 12

7.1

7.2

7.3

7.4

PROGRAM FETCH CYCLE ......................................................................................... 12

DATA READ CYCLE .................................................................................................... 12

DATA WRITE CYCLE................................................................................................... 13

PORT ACCESS CYCLE............................................................................................... 13

8.

9.

TYPICAL APPLICATION CIRCUIT........................................................................................... 14

8.1

8.2

USING EXTERNAL PROGRAM MEMORY AND CRYSTAL....................................... 14

EXPANDED EXTERNAL DATA MEMORY AND OSCILLATOR ................................. 15

PACKAGE DIMENSIONS......................................................................................................... 16

9.1

9.2

9.3

40-PIN DIP.................................................................................................................... 16

44-PIN PLCC................................................................................................................ 16

44-PIN QFP .................................................................................................................. 17

10.

REVISION HISTORY................................................................................................................ 18

Publication Release Date: December 4, 2006

- 1 -

Revision A6

W78C32C/W78C032C

1. GENERAL DESCRIPTION

The W78C032C microcontroller supplies a wider frequency range than most 8-bit microcontrollers on

the market. It is compatible with the industry standard 80C32 microcontroller series.

The W78C032C contains four 8-bit bidirectional parallel ports, three 16-bit timer/counters, and a serial

port. These peripherals are supported by a six-source, two-level interrupt capability. There are 256

bytes of RAM, and the device supports ROMless operation for application programs.

The W78C032C microcontroller has two power reduction modes, idle mode and power-down mode,

both of which are software selectable. The idle mode turns off the processor clock but allows for

continued peripheral operation. The power-down mode stops the crystal oscillator for minimum power

consumption. The external clock can be stopped at any time and in any state without affecting the

1.processor.

2. FEATURES

x

8-bit CMOS microcontroller

Fully static design

Low standby current at full supply voltage

DC-40 MHz operation

256 bytes of on-chip scratchpad RAM

ROMless operation

64K bytes program memory address space

64K bytes data memory address space

Four 8-bit bidirectional ports

Three 16-bit timer/counters

One full duplex serial port

Boolean processor

Six-source, two-level interrupt capability

Built-in power management

Packages:

− Lead Free (RoHS) DIP 40:

W78C032C40DL

− Lead Free (RoHS) PLCC 44: W78C032C40PL

− Lead Free (RoHS) PQFP 44: W78C032C40FL

- 2 -

W78C32C/W78C032C

3. PIN CONFIGURATIONS

40-Pin DIP

1

Vcc

T2, P1.0

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

2

T2EX, P1.1

P0.0, AD0

P0.1, AD1

P0.2, AD2

P0.3, AD3

P0.4, AD4

P0.5, AD5

P0.6, AD6

P0.7, AD7

3

P1.2

P1.3

4

5

P1.4

6

P1.5

7

P1.6

8

P1.7

9

RST

10

11

12

13

14

15

16

17

18

19

20

RXD, P3.0

TXD, P3.1

EA

ALE

INT0, P3.2

PSEN

P2.7, A15

INT1, P3.3

T0, P3.4

T1, P3.5

P2.6, A14

P2.5, A13

P2.4, A12

P2.3, A11

P2.2, A10

P2.1, A9

WR, P3.6

RD, P3.7

XTAL2

XTAL1

P2.0, A8

Vss

44-Pin PLCC

44-Pin QFP

T

2

E

X

,

T

A

D

1

,

A

D

2

,

A

D

3

,

A

D

0

,

2

E

X

,

A

D

1

,

A

D

3

,

A

D

0

,

A

D

2

,

T

2

,

T

2

,

P

1

.

P

1

.

P

1

.

P

1

.

P

1

.

P

0

.

P

0

.

P

0

.

P

0

.

P

0

.

P

1

.

P

1

.

P

1

.

P

1

.

P

1

.

P

0

.

P

0

.

P

0

.

V

C

V

C

N

C

N

C

3

4

3

2

1

0

1

2

4

3

2

1

0

1

2

3

0

34

33

43 42 41 40 39 38 37 36

44

35

40

39

6

5

4

3

2

1 44 43 42

41

P0.4, AD4

P0.5, AD5

P0.6, AD6

P0.7, AD7

1

2

7

8

9

P1.5

P1.6

P1.7

RST

P0.4, AD4

P0.5, AD5

P0.6, AD6

P0.7, AD7

P1.5

P1.6

32

31

30

29

28

27

26

25

38

37

36

35

34

33

32

31

3

4

5

6

7

8

9

P1.7

10

11

12

13

14

15

RST

RXD,

EA

NC

ALE

RXD, P3.0

NC

TXD, P3.1

EA

NC

ALE

NC

TXD,

INT0,

INT1,

INT0, P3.2

INT1, P3.3

T0, P3.4

PSEN

P2.7, A15

PSEN

P2.7, A15

10

11

12

24

23

P2.6, A14

P2.5, A13

16

17

T0, P3.4

T1, P3.5

30

29

P2.6, A14

P2.5, A13

T1, P3.5

13 14 15 16 17 18 19 20 21 22

18 19 20 21 22 23 24 25 26 27 28

P

3

.

P

3

.

X

T

A

L

2

X

T

A

L

1

V

S

N

C

P

2

.

P

2

.

P

2

.

P

2

.

P

2

.

P

3

.

P

3

.

X

T

A

L

2

X

T

A

L

1

V

S

N

C

P

2

.

P

2

.

P

2

.

P

2

.

P

2

.

6

,

7

,

0

,

1

,

3

,

4

,

2

,

6

,

7

,

0

,

1

,

3

,

4

,

2

,

/

A

8

A

9

A

1

A

1

2

A

1

0

/

A

8

A

9

A

1

A

1

2

A

1

0

W R

R

D

R

D

Publication Release Date: December 4, 2006

Revision A6

- 3 -

W78C32C/W78C032C

4. PIN DESCRIPTION

P0.0−P0.7

Port 0, Bits 0 through 7. Port 0 is a bidirectional I/O port. This port also provides a multiplexed low

order address/data bus during accesses to external memory.

P1.0−P1.7

Port 1, Bits 0 through 7. Port 1 is a bidirectional I/O port with internal pull-ups. Pins P1.0 and P1.1 also

serve as T2 (Timer 2 external input) and T2EX (Timer 2 capture/reload trigger), respectively.

P2.0−P2.7

Port 2, Bits 0 through 7. Port 2 is a bidirectional I/O port with internal pull-ups. This port also provides

the upper address bits for accesses to external memory.

P3.0−P3.7

Port 3, Bits 0 through 7. Port 3 is a bidirectional I/O port with internal pull-ups. All bits have alternate

functions, which are described below:

P3.0

P3.1

P3.2

ALTERNATE FUNCTION

RXD Serial Receive Data

TXD Serial Transmit Data

INT0 External Interrupt 0

P3.3

INT1 External Interrupt 1

T0 Timer 0 Input

P3.4

P3.5

P3.6

T1 Timer 1 Input

WR Data Write Strobe

RD Data Read Strobe

P3.7

EA

External Address Input, active low. This pin forces the processor to execute out of external ROM. This

pin should be kept low for all W78C032C operations.

RST

Reset Input, active high. This pin resets the processor. It must be kept high for at least two machine

cycles in order to be recognized by the processor.

ALE

Address Latch Enable Output, active high. ALE is used to enable the address latch that separates the

address from the data on Port 0. ALE runs at 1/6th of the oscillator frequency. A single ALE pulse is

skipped during external data memory accesses. ALE goes to a high state during reset with a weak

pull-up.

- 4 -

W78C32C/W78C032C

PSEN

Program Store Enable Output, active low.

enables the external ROM onto the Port 0

PSEN

address/data bus during fetch and MOVC operations.

weak pull-up.

goes to a high state during reset with a

XTAL1

Crystal 1. This is the crystal oscillator input. This pin may be driven by an external clock.

XTAL2

Crystal 2. This is the crystal oscillator output. It is the inversion of XTAL1.

VSS, VCC

Power Supplies. These are the chip ground and positive supplies.

Publication Release Date: December 4, 2006

Revision A6

- 5 -

W78C32C/W78C032C

5. FUNCTIONAL DESCRIPTION

The W78C032C architecture consists of a core controller surrounded by various registers, four

general purpose I/O ports, 256 bytes of RAM, three timer/counters, and a serial port. The processor

supports 111 different instruction and references both a 64K program address space and a 64K data

storage space.

5.1 Timers 0, 1, and 2

Timers 0, 1, and 2 each consist of two 8-bit data registers. These are called TL0 and TH0 for Timer 0,

TL1 and TH1 for Timer 1, and TL2 and TH2 for Timer 2. The TCON and TMOD registers provide

control functions for timers 0, 1. The T2CON register provides control functions for Timer 2. RCAP2H

and RCAP2L are used as reload/capture registers for Timer 2.

The operations of Timer 0 and Timer 1 are the same as in the W78C31. Timer 2 is a special feature of

the W78C032C: it is a 16-bit timer/counter that is configured and controlled by the T2CON register.

Like Timers 0 and 1, Timer 2 can operate as either an external event counter or as an internal timer,

depending on the setting of bit C/T2 in T2CON. Timer 2 has three operating modes: capture, auto-

reload, and baud rate generator. The clock speed at capture or auto-reload mode is the same as that

of Timers 0 and 1.

5.2 Clock

The W78C032C is designed to be used with either a crystal oscillator or an external clock. Internally,

the clock is divided by two before it is used. This makes the W78C032C relatively insensitive to duty

cycle variations in the clock.

5.2.1 Crystal Oscillator

The W78C032C incorporates a built-in crystal oscillator. To make the oscillator work, a crystal must

be connected across pins XTAL1 and XTAL2. In addition, a load capacitor must be connected from

each pin to ground, and a resistor must also be connected from XTAL1 to XTAL2 to provide a DC bias

when the crystal frequency is above 24 MHz.

5.2.2 External Clock

An external clock should be connected to pin XTAL1. Pin XTAL2 should be left unconnected. The

XTAL1 input is a CMOS-type input, as required by the crystal oscillator. As a result, the external clock

signal should have an input one level of greater than 3.5 volts.

5.3 Power Management

5.3.1 Idle Mode

The idle mode is entered by setting the IDL bit in the PCON register. In the idle mode, the internal

clock to the processor is stopped. The peripherals and the interrupt logic continue to be clocked. The

processor will exit idle mode when either an interrupt or a reset occurs.

- 6 -

W78C32C/W78C032C

5.3.2 Power-down Mode

When the PD bit of the PCON register is set, the processor enters the power-down mode. In this

mode all of the clocks, including the oscillator are stopped. The only way to exit power-down mode is

by a reset.

5.3.3 Reset

The external RESET signal is sampled at S5P2. To take effect, it must be held high for at least two

machine cycles while the oscillator is running.

An internal trigger circuit in the reset line is used to deglitch the reset line when the W78C032C is

used with an external RC network. The reset logic also has a special glitch removal circuit that ignores

glitches on the reset line.

During reset, the ports are initialized to FFH, the stack pointer to 07H, PCON (with the exception of bit

4) to 00H, and all of the other SFR registers except SBUF to 00H. SBUF is not reset.

Publication Release Date: December 4, 2006

- 7 -

Revision A6

W78C32C/W78C032C

6. ELECTRICAL CHARACTERISTICS

6.1 Absolute Maximum Ratings

PARAMETER

DC Power Supply

SYMBOL

MIN.

-0.3

MAX.

+7.0

UNIT

V

VCC−VSS

VIN

Input Voltage

VSS -0.3

0

VCC +0.3

70

V

Operating Temperature

Storage Temperature

TA

°C

TST

-55

+150

Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability

of the device.

6.2 D.C. Characteristics

VCC−VSS = 5V ±10%, TA = 25° C, FOSC = 20 MHz unless otherwise specified.

SPECIFICATION

PARAMETER

SYM.

TEST CONDITIONS

UNIT

MIN.

TYP.

MAX.

Operating Voltage

Operating Current

VDD

IDD

-

4.5

5

5.5

V

No load

VDD = 5.5V

-

30

6

mA

Idle mode

VDD = 5.5V

Idle Current

IIDLE

IPWDN

IIN1

-

mA

μA

V

Power-down mode

VDD = 5.5V

Power Down Current

-

50

Input Current

P1, P3

VDD = 5.5V

-75

-

+10

+350

+10

0.45

-

VIN = 0V or VDD

Input Current

RST ^(*2)

VDD = 5.5V

VIN = VDD

IIN2

+184

Input Leakage Current

P0 ^(*1)

VDD = 5.5V

ILK

-10

-

0V<VIN<VDD

Output Low Voltage

P1, P2 ^(*1), P3

VDD = 4.5V

VOL1

VOL2

VOH1

IOL1 = +2 mA

Output Low Voltage

ALE, PSEN , P0 ^(*1)

VDD = 4.5V

-

V

IOL2 = +4 mA

VDD = 4.5V

Output High Voltage

P1, P3

2.4

V

IOH1 = -100 μA

Output High Voltage

VDD = 4.5V

IOH2 = -400 μA

ALE, PSEN , P0 ^(*1), P2

VOH2

VIL1

2.4

0

-

V

(*1)

Input Low Voltage

P1, P3

VDD = 4.5V

0.8

- 8 -

W78C32C/W78C032C

DC Characteristics, continued

SPECIFICATION

UNIT

PARAMETER

SYM.

TEST CONDITIONS

MIN.

TYP.

MAX.

Input Low Voltage

XTAL1, RST ^(*3)

VIL2

VIH1

VIH2

VDD = 4.5V

VDD = 5.5V

0

-

0.8

V

Input High Voltage

P1, P3

VDD

+0.2

2.4

3.5

-

Input High Voltage

XTAL1, RST ^(*3)

VDD

+0.2

Notes:

1. P0 and P2 are in external access mode.

2. RST pin has an internal pull-down resistor of about 30K Ω.

3. XTAL1 is a CMOS input and RST is a Schmitt trigger input.

6.3 A.C. Characteristics

The AC specifications are a function of the particular process used to manufacture the part, the ratings

of the I/O buffers, the capacitive load, and the internal routing capacitance. Most of the specifications

can be expressed in terms of multiple input clock periods (TCP), and actual parts will usually

experience less than a ±20 nS variation. The numbers below represent the performance expected

from a 0.5 micron CMOS process when using 2 and 4 mA output buffers.

6.3.1 Clock Input Waveform

XTAL1

T_CH

T_CL

F_OP,

T_CP

PARAMETER

Operating Speed

Clock Period

SYMBOL

FOP

MIN.

0

TYP.

MAX.

UNIT

MHz

nS

NOTES

-

40

-

1

2

3

TCP

25

10

Clock High

TCH

-

nS

Clock Low

TCL

-

nS

Notes:

1. The clock may be stopped indefinitely in either state.

2. The TCP specification is used as a reference in other specifications.

3. There are no duty cycle requirements on the XTAL1 input.

Publication Release Date: December 4, 2006

Revision A6

- 9 -

W78C32C/W78C032C

6.3.2 Program Fetch Cycle

PARAMETER

SYMBOL

TAAS

MIN.

1 TCP-Δ

-

TYP.

MAX.

UNIT

nS

NOTES

Address Valid to ALE Low

Address Hold after ALE Low

-

4

1, 4

4

TAAH

-

TAPL

-

ALE Low to PSEN Low

PSEN Low to Data Valid

Data Hold after PSEN High

Data Float after PSEN High

ALE Pulse Width

TPDA

TPDH

TPDZ

TALW

TPSW

-

2 TCP

1 TCP

-

2

0

-

3

0

-

2 TCP

3 TCP

4

2 TCP-Δ

3 TCP-Δ

-

PSEN Pulse Width

Notes:

1. P0.0−P0.7, P2.0−P2.7 remain stable throughout entire memory cycle.

2. Memory access time is 3 TCP.

3. Data have been latched internally prior to PSEN going high.

4. "Δ" ( due to buffer driving delay and wire loading) is 20 nS.

6.3.3 Data Read Cycle

PARAMETER

ALE Low to RD Low

RD Low to Data Valid

Data Hold after RD High

Data Float after RD High

RD Pulse Width

SYMBOL

TDAR

MIN.

TYP.

MAX.

3 TCP+Δ

4 TCP

2 TCP

-

UNIT

nS

NOTES

1, 2

1

-

3 TCP-Δ

TDDA

-

nS

TDDH

0

-

nS

TDDZ

nS

TDRD

6 TCP

nS

2

6 TCP-Δ

Notes:

1. Data memory access time is 8 TCP.

2. "Δ" (due to buffer driving delay and wire loading) is 20 nS.

- 10 -

W78C32C/W78C032C

6.3.4 Data Write Cycle

PARAMETER

SYMBOL

TDAW

MIN.

TYP.

MAX.

UNIT

nS

-

3 TCP-Δ

1 TCP-Δ

6 TCP-Δ

3 TCP+Δ

ALE Low to WR Low

Data Valid to WR Low

Data Hold from WR High

WR Pulse Width

TDAD

-

nS

TDWD

nS

TDWR

6 TCP

nS

Note: "Δ" ( due to buffer driving delay and wire loading) is 20 nS.

6.3.5 Port Access Cycle

PARAMETER

Port Input Setup to ALE Low

Port Input Hold from ALE Low

Port Output to ALE

SYMBOL

TPDS

MIN.

1 TCP

0

TYP.

MAX.

UNIT

nS

-

TPDH

nS

TPDA

1 TCP

nS

Note: Ports are read during S5P2, and output data becomes available at the end of S6P2. The timing data are referenced to

ALE, since it provides a convenient reference.

Publication Release Date: December 4, 2006

- 11 -

Revision A6

W78C32C/W78C032C

7. TIMING WAVEFORMS

7.1 Program Fetch Cycle

S1

S2

S3

S4

S5

S6

S1

S2

S3

S4

S5

S6

XTAL1

ALE

T_ALW

T_APL

PSEN

T_PSW

T_AAS

PORT 2

PORT 0

T_PDA

T_AAH

T

_PDH,T_PDZ

A0-A7

Code

A0-A7

Code

Data

A0-A7

7.2 Data Read Cycle

S4

S5

S6

S1

S2

S3

S4

S5

S6

S1

S2

S3

XTAL1

ALE

PSEN

PORT 2

A8-A15

A0-A7

DATA

PORT 0

RD

T_DDA

T_DAR

T_DDH,T_DDZ

T_DRD

- 12 -

W78C32C/W78C032C

Timing Waveforms, continued

7.3 Data Write Cycle

S4

S5

S6

S1

S2

S3

S4

S5

S6

S1

S2

S3

XTAL1

ALE

PSEN

A8-A15

PORT 2

PORT 0

WR

A0-A7

DATA OUT

T

DWD

T

DAD

T

DAW

T

DWR

7.4 Port Access Cycle

S5

S6

S1

XTAL1

ALE

T_PDS

T_PDH

T_PDA

PORT

DATA OUT

INPUT

SAMPLE

Publication Release Date: December 4, 2006

Revision A6

- 13 -

W78C32C/W78C032C

8. TYPICAL APPLICATION CIRCUIT

8.1 Using External Program Memory and Crystal

V

CC

AD0

31

19

39

38

37

36

2

5

6

9

AD0 3

A0

A1

A2

A3

11

12

13

15

16

17

18

19

AD0

A0

A1

A2

A3

A4

A5

A6

A7

10

9

D0 Q0

D1 Q1

D2 Q2

D3 Q3

D4 Q4

D5 Q5

D6 Q6

D7 Q7

P0.0

P0.1

P0.2

P0.3

P0.4

P0.5

P0.6

P0.7

A0

O0

O1

O2

O3

O4

O5

O6

O7

EA

AD1

AD2

AD3

4

AD1

AD2

AD1

AD2

AD3

AD4

AD5

AD6

AD7

A1

7

8

A2

XTAL1

AD3 8

7

10 u

A3

12 A4

15 A5

16 A6

35 AD4

13

14

17

AD4

AD5

AD6

6

A4

R

18

9

AD5

AD6

AD7

34

33

32

5

XTAL2

RST

A5

CRYSTAL

4

A6

19

A7

3

AD7 18

A7

8.2 K

A8 25

A9 24

A10 21

A8

1

GND

21 A8

22 A9

OC

G

P2.0

P2.1

P2.2

P2.3

P2.4

P2.5

P2.6

P2.7

A9

C1

C2

11

A10

A11

A12

A13

A14

A15

INT0

12

13

14

15

23

A11

A12

23

2

A10

A11

A12

A13

A14

24

INT1

T0

T1

74LS373

25

A13 26

A14 27

26

27

A15

1

P1.0

P1.1

P1.2

P1.3

P1.4

P1.5

P1.6

P1.7

28 A15

GND

20

22

2

3

4

5

6

7

8

CE

OE

RD

17

16

29

30

11

10

WR

27512

PSEN

ALE

TXD

RXD

W78C32C/W78C032C

Figure A

CRYSTAL

16 MHz

24 MHz

33 MHz

40 MHz

C1

30P

15P

10P

5P

C2

R

30P

15P

10P

5P

-

6.8K

Above table shows the reference values for crystal applications.

Note: C1, C2, R components refer to Figure A.

- 14 -

W78C32C/W78C032C

8.2 Expanded External Data Memory and Oscillator

V

CC

31

19

AD0 3

AD1 4

P0.0

P0.1

P0.2

P0.3

P0.4

P0.5

P0.6

P0.7

2

5

6

9

12

15

16

19

A0 10

11

12

13

15

16

17

18

19

AD0

AD1

AD2

AD3

AD4

AD5

AD6

AD7

A0

A1

A2

A3

A4

A5

A6

39 AD0

AD1

A0

A1

A2

A3

A4

A5

A6

A7

A8

A9

A10

A11

A12

A13

A14

D0

D1

D2

D3

D4

D5

D6

D7

D0 Q0

D1 Q1

D2 Q2

D3 Q3

D4 Q4

D5 Q5

D6 Q6

D7 Q7

EA

38

A1

A2

A3

A4

A5

A6

A7

A8 25

A9 24

9

7

8

AD2

AD3

AD4

AD5

AD6

AD7

37 AD2

XTAL1

OSCILLATOR

8

10 u

36 AD3

7

6

5

4

3

13

14

17

18

AD4

AD5

33 AD6

32 AD7

35

34

18

9

XTAL2

A7

8.2 K

RST

INT0

GND

1

A8

A9

P2.0 21

P2.1

P2.2 23 A10

P2.3

P2.4 25

P2.5 26

P2.6

OC

G

22

A10

A11

A12

A13

A14

11

21

23

2

26

1

12

13

14

15

A11

A12

24

74LS373

INT1

T0

T1

A13

27 A14

GND

1

20

22

27

CE

OE

WR

P2.7 28

P1.0

P1.1

P1.2

P1.3

P1.4

P1.5

P1.6

P1.7

2

3

4

5

6

7

8

RD

17

WR

16

29

30

11

10

20256

PSEN

ALE

TXD

RXD

W78C32C/W78C032C

Figure B

Publication Release Date: December 4, 2006

Revision A6

- 15 -

W78C32C/W78C032C

9. PACKAGE DIMENSIONS

9.1 40-pin DIP

Dimension in inchDimension in mm

Symbol

Min. Nom. Max. Min. Nom. Max.

5.334

0.210

A

B

c

0.010

0.150 0.155 0.160 3.81

0.254

1

2

3.937 4.064

0.016 0.018

0.406 0.457 0.559

1.219 1.27 1.372

0.022

0.054

0.050

0.048

0.008

1

0.010 0.014 0.203 0.254 0.356

D

2.055 2.070

52.58

15.494

13.97

52.20

15.24

D

E

40

21

0.610

0.590 0.600

14.986

13.72 13.84

0.540

0.545

0.550

0.110

E

e

L

a

1

0.090 0.100

0.120 0.130

0

2.286 2.54 2.794

1

0.140 3.048 3.302

3.556

15

1

E

15

0

17.01

2.286

0.630 0.650 0.670 16.00 16.51

0.090

e

A

S

1

20

Notes:

E

1. Dimension D Max. & S include mold flash or

tie bar burrs.

S

c

2. Dimension E1 does not include interlead flash.

3. Dimension D & E1 include mold mismatch and

are determined at the mold parting line.

A²

A

L

Base Plane

1

A

.

Seating Plane

4. Dimension B1 does not include dambar

protrusion/intrusion.

B

e₁

e_A

5. Controlling dimension: Inches.

6. General appearance spec. should be based on

final visual inspection spec.

a

B₁

9.2 44-pin PLCC

H_D

D

1

6

44

40

Dimension in inch Dimension in mm

Symbol

Nom.

Min.

Max. Min.

Max.

7

39

0.185

4.699

A

A₂

b

c

0.020

0.508

1

0.145 0.150

0.026 0.028

3.683 3.81 3.937

0.155

0.032 0.66

0.813

0.559

0.356

0.711

0.457

1

0.406

0.022

0.016 0.018

H_E

GE

E

0.008 0.010 0.014 0.203 0.254

16.46 16.59 16.71

1.27 BSC

0.648 0.653 0.658

D

E

e

0.648 0.653

0.658

0.050 BSC

0.590

0.680

0.090

14.99 15.49 16.00

17.27 17.53 17.78

17

29

0.610

0.630

G_D

0.610 0.630

0.690 0.700

0.100

G

E

18

28

H

D

c

H

L

y

E

2.54

2.794

0.10

0.110 2.296

0.004

L

Notes:

A²

A¹

A

1. Dimension D & E do not include interlead

flash.

2. Dimension b1 does not include dambar

protrusion/intrusion.

θ

e

b

3. Controlling dimension: Inches

4. General appearance spec. should be based

on final visual inspection spec.

b₁

Seating Plane

y

G_D

- 16 -

W78C32C/W78C032C

Package Dimensions, continued

9.3 44-pin QFP

H _D

D

Dimension in inch

Dimension in mm

Symbol

A

Min. Nom. Max. Min. Nom. Max.

34

44

---

0.5

0.002

0.01

0.02

0.25

2.05

0.05

1.90

0.25

1

A

0.075 0.081 0.087

2.20

0.45

A₂

b

c

D

E

e

33

1

0.01

0.014

0.006

0.394

0.031

0.018

0.010

0.398

0.35

0.101 0.152 0.254

0.004

0.390

10.00

9.9

10.1

0.952

13.45

0.95

1.905

0.08

7

0.398

0.036

0.530

10.00

0.80

0.390

0.025

E

H^E

0.635

12.95

0.65

0.510 0.520

13.2

0.8

H

D

E

0.520 0.530

0.025 0.031

0.510

H

L

y

11

0.037

0.051 0.063 0.075 1.295

1.6

1

0.003

7

12

22

e

b

θ

0

Notes:

1. Dimension D & E do not include interlead

flash.

c

2. Dimension b does not include dambar

protrusion/intrusion.

3. Controlling dimension: Millimeter

4. General appearance spec. should be based

on final visual inspection spec.

A

A₂

A₁

θ

L

See Detail F

y

Seating Plane

L

1

Detail F

Publication Release Date: December 4, 2006

Revision A6

- 17 -

W78C32C/W78C032C

10. REVISION HISTORY

VERSION

DATE

PAGE

DESCRIPTION

A2

A3

A4

A5

July 1999

-

2

Initial Issued

June, 2004

April 19, 2005

June 7, 2005

Revise part number in the item of packages

Add Important Notice

17

2

Add Lead Free (RoHS) parts

Remove block diagram

A6

December 4, 2006

2

Remove all Leaded package parts

Important Notice

Winbond products are not designed, intended, authorized or warranted for use as components

in systems or equipment intended for surgical implantation, atomic energy control

instruments, airplane or spaceship instruments, transportation instruments, traffic signal

instruments, combustion control instruments, or for other applications intended to support or

sustain life. Further more, Winbond products are not intended for applications wherein failure

of Winbond products could result or lead to a situation wherein personal injury, death or

severe property or environmental damage could occur.

Winbond customers using or selling these products for use in such applications do so at their

own risk and agree to fully indemnify Winbond for any damages resulting from such improper

use or sales.

- 18 -

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