W78E054B40PL全新原装原理图各脚功能电路原理芯片引脚定义-中国IC网-芯三七

W78E54B/W78E054B Data Sheet

8-BIT MICROCONTROLLER

Table of Contents-

1.

2.

3.

4.

5.

6.

GENERAL DESCRIPTION ......................................................................................................... 3

FEATURES................................................................................................................................. 3

PIN CONFIGURATIONS ............................................................................................................ 4

PIN DESCRIPTION..................................................................................................................... 5

BLOCK DIAGRAM ...................................................................................................................... 6

FUNCTIONAL DESCRIPTION ................................................................................................... 7

6.1

6.2

Timers 0, 1, and 2........................................................................................................... 7

New Defined Peripheral.................................................................................................. 7

6.2.1 INT2 / INT3 ...................................................................................................................7

6.2.2 PORT4 .............................................................................................................................8

6.2.3 Reduce EMI Emission ......................................................................................................8

Power-off Flag ................................................................................................................ 9

Watchdog Timer ............................................................................................................. 9

Clock............................................................................................................................. 11

Power Management...................................................................................................... 11

Reset............................................................................................................................. 11

6.3

6.4

6.5

6.6

6.7

7.

ON-CHIP FLASH EPROM CHARACTERISTICS..................................................................... 11

7.1

7.2

7.3

7.4

7.5

7.6

7.7

Read Operation ............................................................................................................ 11

Output Disable Condition.............................................................................................. 11

Program Operation ....................................................................................................... 11

Program Verify Operation............................................................................................. 12

Erase Operation............................................................................................................ 12

Erase Verify Operation ................................................................................................. 12

Program/Erase Inhibit Operation.................................................................................. 12

8.

9.

SECURITY BITS....................................................................................................................... 13

8.1

8.2

8.3

Lock Bit ......................................................................................................................... 13

MOVC Inhibit................................................................................................................. 13

Encryption..................................................................................................................... 13

ELECTRICAL CHARACTERISTICS......................................................................................... 14

9.1

9.2

9.3

Absolute Maximum Ratings.......................................................................................... 14

D.C. Characteristics...................................................................................................... 14

A.C. Characteristics...................................................................................................... 16

Publication Release Date: August 14, 2006

- 1 -

Revision A6

W78E54B/W78E054B

9.3.1 Clock Input Waveform ....................................................................................................16

9.3.2 Program Fetch Cycle......................................................................................................16

9.3.3 Data Read Cycle ............................................................................................................17

9.3.4 Data Write Cycle.............................................................................................................17

9.3.5 Port Access Cycle ..........................................................................................................17

9.3.6 Program Operation.........................................................................................................17

10.

TIMING WAVEFORMS............................................................................................................. 18

10.1 Program Fetch Cycle.................................................................................................... 18

10.2 Data Read Cycle........................................................................................................... 19

10.3 Data Write Cycle........................................................................................................... 19

10.4 Port Access Cycle......................................................................................................... 20

10.5 Program Operation ....................................................................................................... 20

11.

12.

TYPICAL APPLICATION CIRCUITS ........................................................................................ 21

11.1 Expanded External Program Memory and Crystal....................................................... 21

11.2 Expanded External Data Memory and Oscillator ......................................................... 22

PACKAGE DIMENSIONS......................................................................................................... 23

12.1 40-pin DIP..................................................................................................................... 23

12.2 44-pin PLCC ................................................................................................................. 23

12.3 44-pin PQFP ................................................................................................................. 24

13.

REVISION HISTORY................................................................................................................ 25

- 2 -

W78E54B/W78E054B

1. GENERAL DESCRIPTION

The W78E54B is an 8-bit microcontroller which can accommodate a wider frequency range with low

power consumption. The instruction set for the W78E54B is fully compatible with the standard 8051.

The W78E54B contains an 16K bytes Flash EPROM; a 256 bytes RAM; four 8-bit bi-directional and

bit-addressable I/O ports; an additional 4-bit I/O port P4; three 16-bit timer/counters; a hardware

watchdog timer and a serial port. These peripherals are supported by eight sources two-level interrupt

capability. To facilitate programming and verification, the Flash EPROM inside the W78E54B allows

the program memory to be programmed and read electronically. Once the code is confirmed, the user

can protect the code for security.

The W78E54B microcontroller has two power reduction modes, idle mode and power-down mode,

both of which are software selectable. The idle mode turns off the processor clock but allows for

continued peripheral operation. The power-down mode stops the crystal oscillator for minimum power

consumption. The external clock can be stopped at any time and in any state without affecting the

processor.

2. FEATURES

•

Fully static design 8-bit CMOS microcontroller

Wide supply voltage of 4.5V to 5.5V

256 bytes of on-chip scratchpad RAM

16 KB electrically erasable/programmable Flash EPROM

64 KB program memory address space

64 KB data memory address space

Four 8-bit bi-directional ports

•

One extra 4-bit bit-addressable I/O port, additional INT2 / INT3

(available on 44-pin PLCC/QFP package)

•

Three 16-bit timer/counters

One full duplex serial port(UART)

Watchdog Timer

Eight sources, two-level interrupt capability

EMI reduction mode

Built-in power management

Code protection mechanism

Packages:

− DIP 40:

W78E54B-40

− PLCC 44: W78E54BP-40

− PQFP 44: W78E54BF-40

− Lead Free (RoHS) DIP 40:

W78E054B40DL

− Lead Free (RoHS) PLCC 44: W78E054B40PL

− Lead Free (RoHS) PQFP 44: W78E054B40FL

Publication Release Date: August 14, 2006

Revision A6

- 3 -

W78E54B/W78E054B

3. PIN CONFIGURATIONS

40-Pin DIP (W78E54B)

1

2

3

4

5

6

7

8

VDD

T2, P1.0

T2EX, P1.1

P1.2

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

P0.0, AD0

P0.1, AD1

P0.2, AD2

P0.3, AD3

P0.4, AD4

P0.5, AD5

P0.6, AD6

P0.7, AD7

EA

ALE

PSEN

P2.7, A15

P2.6, A14

P2.5, A13

P2.4, A12

P2.3, A11

P2.2, A10

P2.1, A9

P1.3

P1.4

P1.5

P1.6

P1.7

RST

9

10

11

12

13

14

15

16

17

18

19

20

RXD, P3.0

TXD, P3.1

INT0, P3.2

INT1, P3.3

T0, P3.4

T1, P3.5

WR, P3.6

RD, P3.7

XTAL2

XTAL1

VSS

P2.0, A8

44-Pin PLCC (W78E54BP)

44-Pin QFP (W78E54BF)

/

T

2

E

X

,

I

T

2

E

X

,

I

A

D

1

,

A

D

2

,

A

D

3

,

A

D

0

,

N

T

3

,

A

D

3

,

A

D

0

,

A

D

1

,

A

D

2

,

N

T

3

,

T

2

,

T

2

,

P

0

.

P

1

.

P

1

.

P

1

.

P

1

.

P

1

.

P

0

.

P

0

.

P

0

.

P

4

.

P

1

.

P

1

.

P

1

.

P

1

.

P

1

.

P

0

.

P

0

.

P

0

.

P

0

.

P

4

.

V

D

V

D

4

3

2

1

0

1

2

3

0

2

3

4

3

2

1

0

1

2

0

34

33

43 42 41 40 39 38 37 36

44

35

40

39

6

5

4

3

2

1 44 43 42

41

P0.4, AD4

P0.5, AD5

P0.6, AD6

P0.7, AD7

EA

P4.1

ALE

PSEN

P2.7, A15

P2.6, A14

P2.5, A13

1

2

7

8

9

P1.5

P1.6

P1.7

RST

P0.4, AD4

P0.5, AD5

P0.6, AD6

P0.7, AD7

EA

P4.1

ALE

PSEN

P2.7, A15

P1.5

P1.6

P1.7

32

31

30

29

28

27

26

25

38

37

36

35

34

33

32

31

3

4

5

6

7

8

9

10

11

12

13

14

15

RST

RXD, P3.0

INT2, P4.3

TXD, P3.1

INT0, P3.2

INT1, P3.3

T0, P3.4

RXD, P3.0

INT2, P4.3

TXD, P3.1

INT0, P3.2

INT1, P3.3

T0, P3.4

T1, P3.5

10

24

16

17

30

P2.6, A14

P2.5, A13

11

23

29

T1, P3.5

13 14 15 16 17 18 19 20 21 22

12

18 19 20 21 22 23 24 25 26 27 28

P

3

.

P

3

.

X

T

A

L

2

X

T

A

L

1

V

S

P

2

.

P

2

.

P

2

.

P

2

.

P

2

.

P

4

.

P

3

.

P

3

.

X

T

A

L

2

X

T

A

L

1

V

S

P

2

.

P

2

.

P

2

.

P

2

.

P

2

.

P

4

.

6

,

7

,

0

,

1

,

3

,

4

,

2

,

0

6

,

7

,

0

,

1

,

2

,

3

,

4

,

0

/

A

8

A

9

A

1

A

1

2

A

1

0

/

A

8

A

9

A

1

A

1

2

A

1

0

W R

R

D

R

D

- 4 -

W78E54B/W78E054B

4. PIN DESCRIPTION

SYMBOL

DESCRIPTIONS

EXTERNAL ACCESS ENABLE: This pin forces the processor to execute out of

external ROM. It should be kept high to access internal ROM. The ROM address and

EA

data will not be presented on the bus if

EA

pin is high and the program counter is

within on-chip ROM area.

PROGRAM STORE ENABLE: PSEN enables the external ROM data onto the Port 0

address/ data bus during fetch and MOVC operations. When internal ROM access is

PSEN

performed, no PSEN strobe signal outputs from this pin.

ADDRESS LATCH ENABLE: ALE is used to enable the address latch that separates

ALE

RST

the address from the data on Port 0.

RESET: A high on this pin for two machine cycles while the oscillator is running resets

the device.

CRYSTAL1: This is the crystal oscillator input. This pin may be driven by an external

XTAL1

clock.

XTAL2

VSS

CRYSTAL2: This is the crystal oscillator output. It is the inversion of XTAL1.

GROUND: Ground potential

VDD

POWER SUPPLY: Supply voltage for operation.

PORT 0: Port 0 is a bi-directional I/O port which also provides a multiplexed low order

address/data bus during accesses to external memory. The Port 0 is also an open-

drain port and external pull-ups need to be connected while in programming.

P0.0−P0.7

PORT 1: Port 1 is a bi-directional I/O port with internal pull-ups. The bits have alternate

functions which are described below:

T2(P1.0): Timer/Counter 2 external count input

T2EX(P1.1): Timer/Counter 2 Reload/Capture control

P1.0−P1.7

P2.0−P2.7

PORT 2: Port 2 is a bi-directional I/O port with internal pull-ups. This port also provides

the upper address bits for accesses to external memory.

PORT 3: Port 3 is a bi-directional I/O port with internal pull-ups. All bits have alternate

functions, which are described below:

RXD(P3.0) : Serial Port receiver input

TXD(P3.1) : Serial Port transmitter output

INT0 (P3.2) : External Interrupt 0

P3.0−P3.7

P4.0−P4.3

INT1(P3.3) : External Interrupt 1

T0(P3.4) : Timer 0 External Input

T1(P3.5) : Timer 1 External Input

WR(P3.6) :External Data Memory Write Strobe

RD(P3.7) : External Data Memory Read Strobe

PORT 4: Another bit-addressable bidirectional I/O port P4. P4.3 and P4.2 are alternative

function pins. It can be used as general I/O port or external interrupt input sources

(INT2 /INT3 ).

Publication Release Date: August 14, 2006

- 5 -

Revision A6

W78E54B/W78E054B

5. BLOCK DIAGRAM

P1.0

Port

1

~

Port 1

Latch

P1.7

ACC

B

INT2

INT3

P0.0

~

Port 0

Latch

Interrupt

Port

0

T2

T1

P0.7

Timer

2

DPTR

Timer

0

Stack

Pointer

PSW

Temp Reg.

PC

ALU

Timer

1

Incrementor

Addr. Reg.

UART

P3.0

Port 3

Latch

Port

SFR RAM

Address

~

3

P3.7

Instruction

Decoder

&

Sequencer

256 bytes

RAM & SFR

P2.0

~

Port

2

Port 2

Latch

ROM

P2.7

Bus & Clock

Controller

Port 4

Latch

P4.0

~

Port

4

Watchdog

Timer

P4.3

Oscillator

Reset Block

Power control

Vss

Vcc

ALE PSEN

XTAL2

XTAL1

RST

- 6 -

W78E54B/W78E054B

6. FUNCTIONAL DESCRIPTION

The W78E54B architecture consists of a core controller surrounded by various registers, five general

purpose I/O ports, 256 bytes of RAM, three timer/counters, and a serial port. The processor supports

111 different opcodes and references both a 64K program address space and a 64K data storage

space.

6.1 Timers 0, 1, and 2

Timers 0, 1, and 2 each consist of two 8-bit data registers. These are called TL0 and TH0 for Timer 0,

TL1 and TH1 for Timer 1, and TL2 and TH2 for Timer 2. The TCON and TMOD registers provide

control functions for timers 0 and 1. The T2CON register provides control functions for Timer 2.

RCAP2H and RCAP2L are used as reload/capture registers for Timer 2.

The operations of Timer 0 and Timer 1 are the same as in the W78C51. Timer 2 is a special feature of

the W78E54B: it is a 16-bit timer/counter that is configured and controlled by the T2CON register. Like

Timers 0 and 1, Timer 2 can operate as either an external event counter or as an internal timer,

depending on the setting of bit C/T2 in T2CON. Timer 2 has three operating modes: capture, auto-

reload, and baud rate generator. The clock speed at capture or auto-reload mode is the same as that

of Timers 0 and 1.

6.2 New Defined Peripheral

In order to be more suitable for I/O, an extra 4-bit bit-addressable port P4 and two external interrupt

INT2 , INT3 has been added to either the PLCC or QFP 44-pin package. And description follows:

6.2.1 INT2 / INT3

Two additional external interrupts, INT2 and INT3 , whose functions are similar to those of external

interrupt 0 and 1 in the standard 80C52. The functions/status of these interrupts are

determined/shown by the bits in the XICON (External Interrupt Control) register. The XICON register is

bit-addressable but is not a standard register in the standard 80C52. Its address is at 0C0H. To

set/clear bits in the XICON register, one can use the "SETB (/CLR) bit" instruction. For example,

"SETB 0C2H" sets the EX2 bit of XICON.

XICON - external interrupt control (C0H)

PX3

EX3

IE3

IT3

PX2

EX2

IE2

IT2

PX3: External interrupt 3 priority high if set

EX3: External interrupt 3 enable if set

IE3: If IT3 = 1, IE3 is set/cleared automatically by hardware when interrupt is detected/serviced

IT3: External interrupt 3 is falling-edge/low-level triggered when this bit is set/cleared by software

PX2: External interrupt 2 priority high if set

EX2: External interrupt 2 enable if set

IE2: If IT2 = 1, IE2 is set/cleared automatically by hardware when interrupt is detected/serviced

IT2: External interrupt 2 is falling-edge/low-level triggered when this bit is set/cleared by software

Publication Release Date: August 14, 2006

- 7 -

Revision A6

W78E54B/W78E054B

Eight-source interrupt information

POLLING

ENABLE

REQUIRED

SETTINGS

INTERRUPT

TYPE

VECTOR

INTERRUPT SOURCE

ADDRESS

SEQUENCE WITHIN

PRIORITY LEVEL

EDGE/LEVEL

External Interrupt 0

Timer/Counter 0

External Interrupt 1

Timer/Counter 1

Serial Port

Timer/Counter 2

External Interrupt 2

External Interrupt 3

03H

0BH

13H

1BH

23H

2BH

33H

3BH

0 (highest)

IE.0

IE.1

IE.2

IE.3

IE.4

TCON.0

1

2

3

4

5

6

-

TCON.2

-

IE.5

XICON.2

XICON.6

XICON.0

XICON.3

7 (lowest)

6.2.2 PORT4

Another bit-addressable port P4 is also available and only 4 bits (P4<3:0>) can be used. This port

address is located at 0D8H with the same function as that of port P1, except the P4.3 and P4.2 are

alternative function pins. It can be used as general I/O pins or external interrupt input sources (INT2 ,

INT3 ).

Example:

P4

REG 0D8H

P4, #0AH

A, P4

MOV

SETB

CLR

; Output data "A" through P4.0−P4.3.

; Read P4 status to Accumulator.

; Set bit P4.0

P4.0

P4.1

; Clear bit P4.1

6.2.3 Reduce EMI Emission

Because of on-chip Flash EPROM, when a program is running in internal ROM space, the ALE will be

unused. The transition of ALE will cause noise, so it can be turned off to reduce the EMI emission if it

is useless. Turning off the ALE signal transition only requires setting the bit 0 of the AUXR SFR, which

is located at 08Eh. When ALE is turned off, it will be reactivated when the program accesses external

ROM/RAM data or jumps to execute an external ROM code. The ALE signal will turn off again after it

has been completely accessed or the program returns to internal ROM code space. The AO bit in the

AUXR register, when set, disables the ALE output. In order to reduce EMI emission from oscillation

circuitry, W78E54B allows user to diminish the gain of on-chip oscillator amplifiers by using

programmer to clear the B7 bit of security register. Once B7 is set to 0, a half of gain will be

decreased. Care must be taken if user attempts to diminish the gain of oscillator amplifier, reducing a

half of gain may affect the external crystal operating improperly at high frequency above 24 MHz. The

value of R and C1, C2 may need some adjustment while running at lower gain.

- 8 -

W78E54B/W78E054B

***AUXR - Auxiliary register (8EH)

-

AO

AO: Turn off ALE output.

6.3 Power-off Flag

***PCON - Power control (87H)

-

GF1

GF0

PD

IDL

-

POF

POF:

Power off flag. Bit is set by hardware when power on reset. It can be cleared by software

to determine chip reset is a warm boot or cold boot.

GF1, GF0: These two bits are general-purpose flag bits for the user.

PD:

IDL:

Power down mode bit. Set it to enter power down mode.

Idle mode bit. Set it to enter idle mode.

The power-off flag is located at PCON.4. This bit is set when VDD has been applied to the part. It can

be used to determine if a reset is a warm boot or a cold boot if it is subsequently reset by software.

6.4 Watchdog Timer

The Watchdog timer is a free-running timer which can be programmed by the user to serve as a

system monitor, a time-base generator or an event timer. It is basically a set of dividers that divide the

system clock. The divider output is selectable and determines the time-out interval. When the time-out

occurs, a system reset can also be caused if it is enabled. The main use of the Watchdog timer is as a

system monitor. This is important in real-time control applications. In case of power glitches or electro-

magnetic interference, the processor may begin to execute errant code. If this is left unchecked the

entire system may crash. The watchdog time-out selection will result in different time-out values

depending on the clock speed. The Watchdog timer will be disabled on reset. In general, software

should restart the Watchdog timer to put it into a known state. The control bits that support the

Watchdog timer are discussed below.

Watchdog Timer Control Register

Bit:

7

6

5

4

-

3

-

2

PS2

1

PS1

0

PS0

ENW CLRW WIDL

Mnemonic: WDTC

Address: 8FH

ENW : Enable watch-dog if set.

CLRW : Clear watch-dog timer and prescaler if set. This flag will be cleared automatically

WIDL : If this bit is set, watch-dog is enabled under IDLE mode. If cleared, watch-dog is disabled

under IDLE mode. Default is cleared.

PS2, PS1, PS0: Watch-dog prescaler timer select. Prescaler is selected when set PS2~0 as follows:

Publication Release Date: August 14, 2006

- 9 -

Revision A6

W78E54B/W78E054B

PS2 PS1 PS0

PRESCALER SELECT

0

1

0

1

0

1

0

1

0

1

0

1

0

1

2

4

8

16

32

64

128

256

The time-out period is obtained using the following equation:

1

OSC

× 2¹⁴×PRESCALER×1000×12 mS

Before Watchdog time-out occurs, the program must clear the 14-bit timer by writing 1 to WDTC.6

(CLRW). After 1 is written to this bit, the 14-bit timer, prescaler and this bit will be reset on the next

instruction cycle. The Watchdog timer is cleared on reset.

ENW

WIDL

IDLE

EXTERNAL

RESET

INTERNAL

14-BIT TIMER

RESET

PRESCALER

OSC

1/12

CLEAR

CLRW

Watchdog Timer Block Diagram

Typical Watch-Dog time-out period when OSC = 20 MHz

PS2 PS1 PS0 WATCHDOG TIME-OUT PERIOD

0

1

0

1

0

1

0

1

0

1

0

1

0

1

19.66 mS

39.32 mS

78.64 mS

157.28 mS

314.57 mS

629.14 mS

1.25 S

2.50 S

- 10 -

W78E54B/W78E054B

6.5 Clock

The W78E54B is designed to be used with either a crystal oscillator or an external clock. Internally,

the clock is divided by two before it is used. This makes the W78E54B relatively insensitive to duty

cycle variations in the clock. The W78E54B incorporates a built-in crystal oscillator. To make the

oscillator work, a crystal must be connected across pins XTAL1 and XTAL2. In addition, a load

capacitor must be connected from each pin to ground. An external clock source should be connected

to pin XTAL1. Pin XTAL2 should be left unconnected. The XTAL1 input is a CMOS-type input, as

required by the crystal oscillator.

6.6 Power Management

Idle Mode

The idle mode is entered by setting the IDL bit in the PCON register. In the idle mode, the internal

clock to the processor is stopped. The peripherals and the interrupt logic continue to be clocked. The

processor will exit idle mode when either an interrupt or a reset occurs.

Power-down Mode

When the PD bit of the PCON register is set, the processor enters the power-down mode. In this

mode all of the clocks are stopped, including the oscillator. The only way to exit power-down mode is

by a reset.

6.7 Reset

The external RESET signal is sampled at S5P2. To take effect, it must be held high for at least two

machine cycles while the oscillator is running. An internal trigger circuit in the reset line is used to

deglitch the reset line when the W78E54B is used with an external RC network. The reset logic also

has a special glitch removal circuit that ignores glitches on the reset line.

During reset, the ports are initialized to FFH, the stack pointer to 07H, PCON (with the exception of bit

4) to 00H, and all of the other SFR registers except SBUF to 00H. SBUF is not reset.

7. ON-CHIP FLASH EPROM CHARACTERISTICS

The W78E54B has several modes to program the on-chip Flash EPROM. All these operations are

configured by the pins RST, ALE, PSEN , A9CTRL(P3.0), A13CTRL(P3.1), A14CTRL(P3.2),

OECTRL(P3.3), CE (P3.6), OE (P3.7), A0(P1.0) and VPP( EA ). Moreover, the A15−A0(P2.7−P2.0,

P1.7−P1.0) and the D7−D0(P0.7−P0.0) serve as the address and data bus respectively for these

operations.

7.1 Read Operation

This operation is supported for customer to read their code and the Security bits. The data will not be

valid if the Lock bit is programmed to low.

7.2 Output Disable Condition

When the OE is set to high, no data output appears on the D7..D0.

7.3 Program Operation

Publication Release Date: August 14, 2006

- 11 -

Revision A6

W78E54B/W78E054B

This operation is used to program the data to Flash EPROM and the security bits. Program operation

is done when the Vpp is reach to Vcp (12.5V) level, CE set to low, and OE set to high.

7.4 Program Verify Operation

All the programming data must be checked after program operations. This operation should be

performed after each byte is programmed; it will ensure a substantial program margin.

7.5 Erase Operation

An erase operation is the only way to change data from 0 to 1. This operation will erase all the Flash

EPROM cells and the security bits from 0 to 1. This erase operation is done when the Vpp is reach to

Vep level, CE set to low, and OE set to high.

7.6 Erase Verify Operation

After an erase operation, all of the bytes in the chip must be verified to check whether they have been

successfully erased to 1 or not. The erase verify operation automatically ensures a substantial erase

margin. This operation will be done after the erase operation if Vpp = Vep (14.5V), CE is high and

OE is low.

7.7 Program/Erase Inhibit Operation

This operation allows parallel erasing or programming of multiple chips with different data. When

P3.6( CE ) = VIH, P3.7( OE ) = VIH, erasing or programming of non-targeted chips is inhibited. So,

except for the P3.6 and P3.7 pins, the individual chips may have common inputs.

P3.0

(A9

P3.1

(A13

P3.2

(A14

P3.3

(OE

P3.6

P3.7

EA

(V_PP)

P2, P1

(A15..A0) (D7..D0)

P0

OPERATIONS

NOTE

( CE ) ( OE )

CTRL) CTRL) CTRL) CTRL)

Read

Output Disable

Program

0

1

0

1

0

1

VCP

Address Data Out

X

Hi-Z

Address Data In

Address Data Out @3

Program Verify

Data In

0FFH

Address Data Out @5

A0:0,

Erase

1

0

1

VEP

VCP/

VEP

@4

others: X

Erase Verify

Program/Erase

Inhibit

1

0

1

0

1

X

Notes:

1. All these operations happen in RST = VIH, ALE = VIL and PSEN = VIH.

2. VCP = 12.5V, VEP = 14.5V, VIH = VDD, VIL = Vss.

3. The program verify operation follows behind the program operation.

4. This erase operation will erase all the on-chip Flash EPROM cells and the Security bits.

5. The erase verify operation follows behind the erase operation.

- 12 -

W78E54B/W78E054B

8. SECURITY BITS

During the on-chip Flash EPROM operation mode, the Flash EPROM can be programmed and

verified repeatedly. Until the code inside the Flash EPROM is confirmed OK, the code can be

protected. The protection of Flash EPROM and those operations on it are described below.

The W78E54B has a Security Register which can not be accessed in normal mode. These registers

can only be accessed from the Flash EPROM operation mode. Those bits of the Security Register can

not be changed once they have been programmed from high to low. They can only be reset through

erase-all operation. The Security Register is addressed in the Flash EPROM operation mode by

address #0FFFFh.

0000h

16KB On-chip ROM

Program Memory

3FFFh

Security Bits

B2 B1 B0

Reserved

B7

Reserved

B0 : Lock bit, logic 0 : active

B1 : MOVC inhibit,

logic 0 : the MOVC instruction in external memory

cannot access the code in internal memory.

logic 1 : no restriction.

B2 : Encryption

Security Register

logic 0 : the encryption logic enable

logic 1 : the encryption logic disable

0FFFFh

B7 : Osillator Control

logic 0 : 1/2 gain

logic 1 : Full gain

Default 1 for all security bits. Reserved bits must be kept in logic 1.

Special Setting Register

8.1 Lock Bit

This bit is used to protect the customer's program code in the W78E54B. It may be set after the

programmer finishes the programming and verifies sequence. Once this bit is set to logic 0, both the

Flash EPROM data and Special Setting Register can not be accessed again.

8.2 MOVC Inhibit

This bit is used to restrict the accessible region of the MOVC instruction. It can prevent the MOVC

instruction in external program memory from reading the internal program code. When this bit is set to

logic 0, a MOVC instruction in external program memory space will be able to access code only in the

external memory, not in the internal memory. A MOVC instruction in internal program memory space

will always be able to access the ROM data in both internal and external memory. If this bit is logic 1,

there are no restrictions on the MOVC instruction.

8.3 Encryption

This bit is used to enable/disable the encryption logic for code protection. Once encryption feature is

enabled, the data presented on port 0 will be encoded via encryption logic. Only whole chip erase will

reset this bit.

Publication Release Date: August 14, 2006

- 13 -

Revision A6

W78E54B/W78E054B

+5V

V

DD

PGM DATA

A0 to A7

P1

P0

A0 to A7

P1

P0

V

P3.0

P3.1

P3.2

P3.3

P3.6

P3.7

EA/Vpp

ALE

P3.0

P3.1

P3.2

P3.3

P3.6

P3.7

EA/Vpp

ALE

IL

IH

IL

IH

IL

V

CP

IL

CP

IL

RST

V

RST

V

IH

V

PSEN

X'tal1

X'tal2

Vss

X'tal1

X'tal2

Vss

A8 to A15

P2

Programming Configuration

Programming Verification

9. ELECTRICAL CHARACTERISTICS

9.1 Absolute Maximum Ratings

PARAMETER

DC Power Supply

Input Voltage

Operating Temperature

Storage Temperature

SYMBOL

VDD−VSS

VIN

MIN.

-0.3

VSS -0.3

MAX.

+7.0

VDD +0.3

70

UNIT

V

°C

TA

0

-55

TST

+150

Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability

of the device.

9.2 D.C. Characteristics

(VCC−VSS = 5V ±10%, TA = 25° C, unless otherwise specified.)

PECIFICATION

PARAMETER

Operating Voltage

SYMBOL

TEST CONDITIONS

UNIT

MIN.

MAX.

VDD

IDD

-

4.5

5.5

V

No load, VDD = 5.5V,

Operating Current

Idle Current

-

20

6

mA

µA

RST = 1

IIDLE

IPWDN

Idle mode VDD = 5.5V

Power-down mode

Power Down Current

50

VDD = 5.5V

Input Current

P1, P2, P3, P4

VDD = 5.5V

IIN1

ITL

-50

+10

-

µA

VIN = 0V or VDD

Logical 1-to-0 Transition

VDD = 5.5V

-550

Current P1, P2, P3 ^(*1), P4

VIN = 2.0V ^(*1)

- 14 -

W78E54B/W78E054B

DC Characteristics, continued

SPECIFICATION

PARAMETER

SYMBOL

IIN2

TEST CONDITIONS

UNIT

µA

V

MIN.

MAX.

Input Current

VDD = 5.5V

VIN = VDD

VDD = 5.5V

0V < VIN < VDD

VDD = 4.5V

IOL1 = +2 mA

VDD = 4.5V

IOL2 = +4 mA

-10

+300

RST ^(*2)

Input Leakage Current

ILK

-10

-

+10

0.45

-

P0, EA

Output Low Voltage

P1, P2, P3, P4

Output Low Voltage

VOL1

VOL2

VOH1

VOH2

VIL1

-

V

ALE, PSEN , P0 ^(*3)

Output High Voltage

P1, P2, P3, P4

VDD = 4.5V

IOH1 = -100 µA

VDD = 4.5V

2.4

0

V

Output High Voltage

-

V

ALE, PSEN , P0 ^(*3)

Input Low Voltage

(Except RST)

IOH2 = -400 µA

VDD = 4.5V

0.8

V

Input Low Voltage

VIL2

0

V

RST ^(*4)

Input Low Voltage

VIL3

VDD = 4.5V

0

0.8

V

XTAL1 ^(*4)

Input High Voltage

(Except RST)

Sink Current

VIH1

ISK1

2.4

4

VDD +0.2

12

V

mA

V

VDD = 4.5V

Vs = 0.45V

P1, P2, P3, P4

Input High Voltage

VIH2

VIH3

VDD = 4.5V

0.67 VDD

VDD +0.2

RST ^(*4)

Input High Voltage

VDD = 4.5V

0.67 VDD

V

XTAL1 ^(*4)

Sink Current

P0, ALE, PSEN

Source Current

P1, P2, P3, P4

Source Current

VDD = 4.5V

Vs = 0.45V

VDD = 4.5V

Vs = 2.4V

VDD = 4.5V

Vs = 2.4V

ISK2

ISR1

ISR2

8

-100

-8

16

-250

-14

mA

uA

(*3)

mA

(*3)

P0, ALE, PSEN

Notes:

*1. Pins P1, P2 and P3 source a transition current when they are being externally driven from 1 to 0. The transition current

reaches its maximum value when VIN is approximately 2V.

*2. RST pin has an internal pull-down resistor.

PSEN

*3. P0, ALE,

are in the external access memory mode.

*4. XTAL1 is a CMOS input and RST is a Schmitt trigger input.

Publication Release Date: August 14, 2006

Revision A6

- 15 -

W78E54B/W78E054B

9.3 A.C. Characteristics

The AC specifications are a function of the particular process used to manufacture the part, the

ratings of the I/O buffers, the capacitive load, and the internal routing capacitance. Most of the

specifications can be expressed in terms of multiple input clock periods (TCP), and actual parts will

usually experience less than a ±20 nS variation. The numbers below represent the performance

expected from a 0.6micron CMOS process when using 2 and 4 mA output buffers.

9.3.1 Clock Input Waveform

XTAL1

T

CH

T

CL

F

T

CP

OP,

PARAMETER

Operating Speed

Clock Period

Clock High

Clock Low

SYMBOL

FOP

MIN.

0

25

10

TYP.

MAX.

40

-

UNIT

MHz

nS

NOTES

-

1

2

3

TCP

TCH

TCL

-

Notes:

1. The clock may be stopped indefinitely in either state.

2. The TCP specification is used as a reference in other specifications.

3. There are no duty cycle requirements on the XTAL1 input.

9.3.2 Program Fetch Cycle

PARAMETER

Address Valid to ALE Low

Address Hold from ALE Low

SYMBOL

TAAS

TAAH

MIN.

1 TCP -∆

-

TYP.

MAX.

UNIT

nS

NOTES

-

4

1, 4

4

TAPL

nS

ALE Low to PSEN Low

TPDA

TPDH

TPDZ

TALW

TPSW

-

2 TCP

nS

2

3

PSEN Low to Data Valid

Data Hold after PSEN High

Data Float after PSEN High

ALE Pulse Width

0

-

1 TCP

2 TCP

3 TCP

-

4

2 TCP -∆

3 TCP -∆

PSEN Pulse Width

Notes:

1. P0.0−P0.7, P2.0−P2.7 remain stable throughout entire memory cycle.

2. Memory access time is 3 TCP.

3. Data have been latched internally prior to PSEN going high.

4. "∆" (due to buffer driving delay and wire loading) is 20 nS.

- 16 -

W78E54B/W78E054B

9.3.3 Data Read Cycle

PARAMETER

SYMBOL

TDAR

MIN.

TYP.

MAX.

3 TCP +∆

4 TCP

2 TCP

-

UNIT

nS

NOTES

1, 2

1

-

3 TCP -∆

ALE Low to RD Low

RD Low to Data Valid

Data Hold from RD High

Data Float from RD High

RD Pulse Width

TDDA

-

nS

TDDH

0

-

nS

TDDZ

nS

TDRD

6 TCP

nS

2

6 TCP -∆

Notes:

1. Data memory access time is 8 TCP.

2. "∆" (due to buffer driving delay and wire loading) is 20 nS.

9.3.4 Data Write Cycle

PARAMETER

ALE Low to WR Low

Data Valid to WR Low

Data Hold from WR High

WR Pulse Width

SYMBOL

TDAW

MIN.

TYP.

MAX.

UNIT

nS

-

3 TCP -∆

1 TCP -∆

6 TCP -∆

3 TCP +∆

TDAD

-

nS

TDWD

nS

TDWR

6 TCP

nS

Note: "∆" (due to buffer driving delay and wire loading) is 20 nS.

9.3.5 Port Access Cycle

PARAMETER

Port Input Setup to ALE Low

Port Input Hold from ALE Low

Port Output to ALE

SYMBOL

MIN.

1 TCP

0

TYP.

MAX.

UNIT

nS

TPDS

TPDH

TPDA

-

1 TCP

nS

Note: Ports are read during S5P2, and output data becomes available at the end of S6P2. The timing data are referenced to

ALE, since it provides a convenient reference.

9.3.6 Program Operation

PARAMETER

VPP Setup Time

SYMBOL

TVPS

TDS

MIN.

2.0

0

TYP.

MAX.

UNIT

µS

-

Data Setup Time

Data Hold Time

µS

TDH

µS

Address Setup Time

Address Hold Time

TAS

µS

TAH

µS

Publication Release Date: August 14, 2006

Revision A6

- 17 -

W78E54B/W78E054B

Program Operation, continued

PARAMETER

SYMBOL

MIN.

TYP.

MAX.

UNIT

CE Program Pulse Width for Program

Operation

TPWP

290

300

310

µS

OECTRL Setup Time

OECTRL Hold Time

TOCS

TOCH

TOES

2.0

-

µS

nS

OE Setup Time

TDFP

TOEV

0

-

130

150

OE High to Output Float

Data Valid from OE

nS

Note: Flash data can be accessed only in flash mode. The RST pin must pull in VIH status, the ALE pin must pull in VIL status,

and the PSEN pin must pull in VIH status.

10.TIMING WAVEFORMS

10.1 Program Fetch Cycle

S1

S2

S3

S4

S5

S6

S1

S2

S3

S4

S5

S6

XTAL1

ALE

T_ALW

T_APL

PSEN

T_PSW

T_AAS

PORT 2

PORT 0

T_PDA

T_AAH

T_PDH,T_PDZ

A0-A7

Code

A0-A7

Code

Data

A0-A7

- 18 -

W78E54B/W78E054B

Timing Waveforms, continued

10.2 Data Read Cycle

S4

S5

S6

S1

S2

S3

S4

S5

S6

S1

S2

S3

XTAL1

ALE

PSEN

PORT 2

A8-A15

DATA

A0-A7

PORT 0

RD

T

DDA

DAR

T

DDZ

DDH,

T

DRD

10.3 Data Write Cycle

S4

S5

S6

S1

S2

S3

S4

S5

S6

S1

S2

S3

XTAL1

ALE

PSEN

A8-A15

DATA OUT

PORT 2

PORT 0

WR

A0-A7

T_DWD

T_DAD

T_DWR

T_DAW

Publication Release Date: August 14, 2006

Revision A6

- 19 -

W78E54B/W78E054B

Timing Waveforms, continued

10.4 Port Access Cycle

S5

S6

S1

XTAL1

ALE

T_PDS

T_PDH

T_PDA

PORT

DATA OUT

INPUT

SAMPLE

10.5 Program Operation

Program

Verify

Read Verify

V

IH

P2, P1

(A15... A0)

Address Stable

Address Valid

V

IL

T_AS

V

P3.6

(CE)

IH

T

PWP

V

IL

T_AH

V

P3.3

IH

T

OCS

(OECTRL)

V

IL

T_OCH

P3.7

(OE)

V

IH

T

OES

V

IL

T_DFP

T_DH

V

IH

P0

(A7... A0)

OUT

D

Data In

Data Out

V

IL

T_DS

Vcp

T_OEV

Vpp

V

IH

T

VPS

- 20 -

W78E54B/W78E054B

11.TYPICAL APPLICATION CIRCUITS

11.1 Expanded External Program Memory and Crystal

V

DD

V

DD

31

19

AD0

39

AD0 3

11 AD0

2

A0

A1

A2

A3

A4

A5

A6

A7

A0

10

9

D0 Q0

D1 Q1

D2 Q2

D3 Q3

D4 Q4

D5 Q5

D6 Q6

D7 Q7

P0.0

P0.1

P0.2

P0.3

P0.4

P0.5

P0.6

P0.7

A0

O0

O1

O2

O3

O4

O5

O6

O7

EA

38 AD1

37 AD2

36 AD3

4

7

8

5 A1

6 A2

12

13

15

AD1

AD2

AD3

AD1

AD2

AD3

A1

8

A2

XTAL1

9

A3

A4

A5

A6

7

10 u

C1

A3

AD4

AD5

AD6

AD7

12

15

16

19

16 AD4

35

34

33

32

AD413

6

A4

R

18

9

14

17

AD5

5

AD5

XTAL2

RST

A5

CRYSTAL

18 AD6

19 AD7

AD617

4

A6

3

AD718

A7

8.2 K

A8 25

A9 24

A10 21

A8

1

GND

11

A8

21

22

23

24

25

OC

G

P2.0

P2.1

P2.2

P2.3

P2.4

P2.5

P2.6

P2.7

A9

C2

A9

A10

A11

A12

A13

A14

A15

INT0

A11

23

12

13

A10

A11

A12

A12 2

INT1

74373

A13

A14

A15

26

27

1

14

15

T0

26 A13

27 A14

28 A15

T1

1

2

3

4

5

6

7

8

P1.0

P1.1

P1.2

P1.3

P1.4

P1.5

P1.6

P1.7

GND

20

22

CE

OE

RD

WR

17

16

29

30

11

10

27512

PSEN

ALE

TXD

RXD

W78E54B

Figure A

CRYSTAL

16 MHz

24 MHz

33 MHz

40 MHz

C1

30P

15P

10P

5P

C2

30P

15P

10P

5P

R

-

6.8K

4.7K

Above table shows the reference values for crystal applications (full gain).

Note: C1, C2, R components refer to Figure A.

Publication Release Date: August 14, 2006

Revision A6

- 21 -

W78E54B/W78E054B

Typical Application Circuits, continued

11.2 Expanded External Data Memory and Oscillator

V

DD

V

DD

31

19

10

9

P0.0

P0.1

P0.2

P0.3

P0.4

P0.5

P0.6

P0.7

A0

A1

11

12

13

15

16

17

18

19

AD0

AD1

AD2

AD3

AD4

AD5

AD6

AD7

AD0

3

A0

A1

39 AD0

2

5

6

9

A0

A1

A2

A3

A4

A5

A6

A7

A8

A9

D0 Q0

D1 Q1

D2 Q2

D3 Q3

D4 Q4

D5 Q5

D6 Q6

D7 Q7

D0

D1

D2

D3

D4

D5

D6

D7

EA

XTAL1

AD1

AD1 4

AD2 7

AD3 8

38

A2 A2

8

37 AD2

36 AD3

OSCILLATOR

A3

10 u

7

A4

6

AD4

AD5

12 A4

35

34

13

AD4

18

9

5

15 A5 A5

XTAL2

AD514

17

33 AD6

32 AD7

A6

4

16

A6

A7

AD6

AD718

8.2 K

19 A7

3

A8 25

A9 24

RST

INT0

GND

1

11

21

A8

P2.0

P2.1

P2.2

P2.3

P2.4

P2.5

P2.6

P2.7

OC

G

A9

22

21

23

2

A10

A11

A12

A13

A10

A11

A12

12

13

14

15

23

24

25

26

27

28

A10

A11

A12

A13

A14

74373

INT1

T0

T1

26

A13

A14

CE

OE

A14 1

GND

20

1

2

3

4

5

6

7

8

P1.0

P1.1

P1.2

P1.3

P1.4

P1.5

P1.6

P1.7

22

27

RD

WR 16

17

WR

29

20256

PSEN

30

11

10

ALE

TXD

RXD

W78E54B

Figure B

- 22 -

W78E54B/W78E054B

12.PACKAGE DIMENSIONS

12.1 40-pin DIP

Dimension in inch Dimension in mm

Symbol

Min. Nom. Max. Min. Nom. Max.

5.334

0.210

A

B

c

D

E

e

L

a

0.010

0.150 0.155 0.160

0.254

3.81

1

2

3.937 4.064

0.016 0.018

0.406 0.457 0.559

1.219 1.27 1.372

0.203 0.254 0.356

0.022

0.054

0.050

0.010

2.055

0.048

0.008

1

0.014

D

2.070

52.58

15.494

13.97

2.794

3.556

15

52.20

15.24

40

21

0.610

0.590 0.600

14.986

13.72 13.84

0.540

0.545 0.550

1

0.110

0.090 0.100

2.286

3.048

0

2.54

0.120 0.130 0.140

15

3.302

E¹

0

0.630 0.650 0.670 16.00 16.51 17.01

0.090

e

S

A

2.286

1

20

Notes:

E

1. Dimension D Max. & S include mold flash or

tie bar burrs.

S

c

2. Dimension E1 does not include interlead flash.

3. Dimension D & E1 include mold mismatch and

A²

A

L

Base Plane

1

A

.

are determined at the mold parting line.

Seating Plane

4. Dimension B1 does not include dambar

protrusion/intrusion.

B

e₁

e_A

5. Controlling dimension: Inches.

6. General appearance spec. should be based on

final visual inspection spec.

a

B ₁

12.2 44-pin PLCC

H _D

D

6

1

44

40

Dimension in inch Dimension in mm

Min. Nom. Max. Min. Nom. Max.

Symbol

7

39

0.185

4.699

A

0.020

0.508

1

0.145 0.150 0.155 3.683 3.81 3.937

A₂

b ₁

b

0.026 0.028

0.016 0.018

0.032 0.66

0.406

0.813

0.559

0.356

0.711

0.457

0.022

H_E

GE

E

0.008 0.010 0.014 0.203 0.254

c

16.46 16.59 16.71

1.27 BSC

0.648 0.653 0.658

D

0.648 0.653

0.658

E

0.050 BSC

e

0.590

0.680

14.99 15.49 16.00

17.27 17.53 17.78

17

29

0.610

0.630

G_D

0.610 0.630

0.690 0.700

G

H

E

18

28

D

c

L ^E

y

0.090 0.100

2.54 2.794

0.10

0.110 2.296

0.004

L

Notes:

A²

A¹

A

1. Dimension D & E do not include interlead

flash.

θ

2. Dimension b1 does not include dambar

protrusion/intrusion.

e

b

b ¹

3. Controlling dimension: Inches

Seating Plane

y

4. General appearance spec. should be based

on final visual inspection spec.

G _D

Publication Release Date: August 14, 2006

Revision A6

- 23 -

W78E54B/W78E054B

Package Dimensions, continued

12.3 44-pin PQFP

H _D

D

Dimension in inch

Dimension in mm

Symbol

A

Min. Nom. Max. Min. Nom. Max.

34

44

---

0.5

0.002

0.01

0.02

0.25

2.05

0.05

1.90

0.25

1

A

0.075 0.081 0.087

2.20

0.45

0.254

A₂

b

c

33

1

0.01

0.014

0.006

0.394

0.031

0.018

0.010

0.398

0.35

0.101 0.152

0.004

0.390

10.00

9.9

10.1

0.952

13.45

0.95

1.905

0.08

7

D

E

e

0.398

0.036

0.530

10.00

0.80

0.390

0.025

E

H^E

0.635

12.95

0.65

0.510 0.520

13.2

0.8

H

D

E

0.520 0.530

0.025 0.031

0.510

H

L

y

11

0.037

0.051 0.063 0.075 1.295

0.003

1.6

1

12

22

e

b

7

θ

0

Notes:

1. Dimension D & E do not include interlead

c

flash.

2. Dimension b does not include dambar

protrusion/intrusion.

A

A₂

A₁

3. Controlling dimension: Millimeter

θ

4. General appearance spec. should be based

on final visual inspection spec.

L

See Detail F

y

Seating Plane

L

1

Detail F

- 24 -

W78E54B/W78E054B

13.REVISION HISTORY

VERSION

DATE

PAGE

DESCRIPTION

A3

A4

A5

A6

December, 2000

June, 2004

April 20, 2005

August 14, 2006

-

3

25

3

Formerly issued

Revise part number in the item of packages

Add Important Notice

Add lead-free(RoHS) parts

Important Notice

Winbond products are not designed, intended, authorized or warranted for use as components

in systems or equipment intended for surgical implantation, atomic energy control

instruments, airplane or spaceship instruments, transportation instruments, traffic signal

instruments, combustion control instruments, or for other applications intended to support or

sustain life. Further more, Winbond products are not intended for applications wherein failure

of Winbond products could result or lead to a situation wherein personal injury, death or

severe property or environmental damage could occur.

Winbond customers using or selling these products for use in such applications do so at their

own risk and agree to fully indemnify Winbond for any damages resulting from such improper

use or sales.

Headquarters

Winbond Electronics Corporation America Winbond Electronics (Shanghai) Ltd.

27F, 2299 Yan An W. Rd. Shanghai,

200336 China

2727 North First Street, San Jose,

CA 95134, U.S.A.

No. 4, Creation Rd. III,

Science-Based Industrial Park,

Hsinchu, Taiwan

TEL: 86-21-62365999

FAX: 86-21-62365998

TEL: 1-408-9436666

TEL: 886-3-5770066

FAX: 1-408-5441798

FAX: 886-3-5665577

http://www.winbond.com.tw/

Taipei Office

Winbond Electronics Corporation Japan

Winbond Electronics (H.K.) Ltd.

9F, No.480, Rueiguang Rd.,

Neihu District, Taipei, 114,

Taiwan, R.O.C.

7F Daini-ueno BLDG, 3-7-18

Shinyokohama Kohoku-ku,

Yokohama, 222-0033

Unit 9-15, 22F, Millennium City,

No. 378 Kwun Tong Rd.,

Kowloon, Hong Kong

TEL: 852-27513100

TEL: 886-2-8177-7168

FAX: 886-2-8751-3579

TEL: 81-45-4781881

FAX: 81-45-4781800

FAX: 852-27552064

Please note that all data and specifications are subject to change without notice.

All the trademarks of products and companies mentioned in this datasheet belong to their respective owners.

Publication Release Date: August 14, 2006

Revision A6

- 25 -

电子百科

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