W78E065A40DL全新原装原理图各脚功能电路原理芯片引脚定义-中国IC网-芯三七

W78E65/W78E065A Data Sheet

8-BIT MICROCONTROLLER

Table of Contents-

1.

2.

3.

4.

5.

6.

GENERAL DESCRIPTION ......................................................................................................... 3

FEATURES................................................................................................................................. 3

PIN CONFIGURATIONS ............................................................................................................ 4

PIN DESCRIPTION..................................................................................................................... 5

BLOCK DIAGRAM ...................................................................................................................... 6

FUNCTIONAL DESCRIPTION ................................................................................................... 7

6.1

6.2

RAM................................................................................................................................ 7

Timers 0, 1, and 2........................................................................................................... 8

6.2.1 Timer 2 Output .................................................................................................................8

6.3

6.4

Clock............................................................................................................................... 8

6.3.1 Crystal Oscillator ..............................................................................................................8

6.3.2 External Clock ..................................................................................................................8

Power Management........................................................................................................ 8

6.4.1 Idle Mode..........................................................................................................................8

6.4.2 Power-down Mode............................................................................................................9

6.4.3 Reduce EMI Emission ......................................................................................................9

6.5

6.6

Reset............................................................................................................................... 9

6.5.1 W78E65 Special Function Registers (SFRs) and Reset Values.....................................10

Port 4 ............................................................................................................................ 11

6.6.1 Port Options Register .....................................................................................................11

6.6.2 INT2 /INT3 ..................................................................................................................11

6.6.3 Port 4 Base Address Registers ......................................................................................13

Pulse Width Modulated Outputs (PWM)....................................................................... 15

Watchdog Timer ........................................................................................................... 18

6.7

6.8

6.9

In-System Programming (ISP) Mode............................................................................ 20

6.9.1 In-System Programming Control Register (CHPCON) ...................................................21

6.10 Software Reset ............................................................................................................. 22

6.11 H/W Reboot Mode (Boot from LD FLASH EPROM) .................................................... 22

6.12 Security......................................................................................................................... 25

ELETRICAL CHARACTERISTICS ........................................................................................... 26

7.

8.

7.1

7.2

7.3

Absolute Maximum Ratings.......................................................................................... 26

DC Characteristics........................................................................................................ 26

AC Characteristics........................................................................................................ 28

TIMING WAVEFORMS............................................................................................................. 29

Publication Release Date: January 9, 2006

- 1 -

Revision A7

W78E65/W78E065A

8.1

8.2

8.3

8.4

Program Fetch Cycle.................................................................................................... 29

Data Read Cycle........................................................................................................... 30

Data Write Cycle........................................................................................................... 31

Port Access Cycle......................................................................................................... 32

9.

TYPICAL APPLICATION CIRCUIT........................................................................................... 33

9.1

9.2

External Program Memory and Crystal ........................................................................ 33

Expanded External Data Memory and Oscillator ......................................................... 34

10.

11.

12.

PACKAGE DIMENSIONS......................................................................................................... 35

10.1 44-pin PLCC ................................................................................................................. 35

APPLICATION NOTE ............................................................................................................... 36

11.1 In-system Programming Software Examples ............................................................... 36

REVISION HISTORY................................................................................................................ 41

- 2 -

W78E65/W78E065A

1. GENERAL DESCRIPTION

The W78E65 is an 8-bit microcontroller which has an in-system programmable Flash EPROM for

firmware updating. The instruction set of the W78E65 is fully compatible with the standard 8052. The

W78E65 contains a 64K bytes of main ROM and a 4K bytes of auxiliary ROM which allows the

contents of the 64KB main ROM to be updated by the loader program located at the 4KB auxiliary

ROM; 256+1K bytes of on-chip RAM; four 8-bit bi-directional and bit-addressable I/O ports; an

additional 4-bit port P4; three 16-bit timer/counters; a serial port. These peripherals are supported by a

eight sources two-level interrupt capability. To facilitate programming and verification, the ROM inside

the W78E65 allows the program memory to be programmed and read electronically. Once the code is

confirmed, the user can protect the code for security.

The W78E65 microcontroller has two power reduction modes, idle mode and power-down mode, both

of which are software selectable. The idle mode turns off the processor clock but allows for continued

peripheral operation. The power-down mode stops the crystal oscillator for minimum power

consumption. The external clock can be stopped at any time and in any state without affecting the

processor.

2. FEATURES

y

Fully static design 8-bit CMOS microcontroller

64K bytes of in-system programmable Flash EPROM for Application Program (AP FLASH

EPROM)

y

4K bytes of auxiliary ROM for Loader Program (LD FLASH EPROM)

256+1K bytes of on-chip RAM. (Including 1K bytes of AUX-RAM, software selectable)

64K bytes program memory address space and 64K bytes data memory address space

ALE off software selectable.

Four 8-bit bi-directional ports; Port 0 has internal pull-up resisters enabled by software

One 4-bit multipurpose programmable port (I/O, interrupt, Chip select function)

Three 16-bit timer/counters

One full duplex serial port

5 channel PWM

Watchdog timer

Software Reset

P1.0 T2 programmable clock out

Eight-sources, two-level interrupt capability

Built-in power management

Code protection

Packaged in

− DIP 44: W78E65-40

− PLCC 44: W78E65P-40

− QFP 44: W78E65F-40

− Lead Free(RoHS) PLCC 44:W78E065A40PL

− Lead Free(RoHS) DIP 40: W78E065A40DL

− Lead Free(RoHS) QFP 44: W78E065A40FL

Publication Release Date: January 9, 2006

- 3 -

Revision A7

W78E65/W78E065A

3. PIN CONFIGURATIONS

40-Pin DIP

1

VDD

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

T2, P1.0

T2EX, P1.1

2

P0.0, AD0

P0.1, AD1

P0.2, AD2

P0.3, AD3

P0.4, AD4

P0.5, AD5

P0.6, AD6

P0.7, AD7

3

P1.2

P1.3

4

5

P1.4

6

P1.5

7

P1.6

8

P1.7

9

RST

10

11

12

13

14

15

16

17

18

19

20

RXD, P3.0

TXD, P3.1

EA

ALE

INT0, P3.2

PSEN

P2.7, A15

INT1, P3.3

T0, P3.4

T1, P3.5

P2.6, A14

P2.5, A13

P2.4, A12

P2.3, A11

P2.2, A10

P2.1, A9

WR, P3.6

RD, P3.7

XTAL2

XTAL1

VSS

P2.0, A8

44-Pin QFP

44-Pin PLCC

/

T

2

E

X

,

I

/

A

D

3

,

A

D

0

,

A

D

1

,

A

D

2

,

T

2

E

X

,

N

T

3

,

I

T

2

,

A

D

3

,

A

D

0

,

A

D

1

,

A

D

2

,

N

T

3

,

T

2

,

P

0

.

P

1

.

P

1

.

P

1

.

P

1

.

P

1

.

P

0

.

P

0

.

P

0

.

P

4

.

V

D

P

1

.

P

1

.

P

1

.

P

1

.

P

1

.

P

0

.

P

0

.

P

0

.

P

4

.

P

0

.

V

D

4

3

2

1

0

1

2

3

0

2

4

3

2

1

0

1

2

3

2

0

34

43 42 41 4039 38 37 36 35

44

40

39

6

5

4

3

2

1 44 43 42

41

1

2

3

4

5

6

7

8

9

33

P0.4, AD4

P0.5, AD5

P0.6, AD6

P0.7, AD7

P1.5

P1.6

7

8

9

P1.5

P1.6

P1.7

RST

P0.4, AD4

P0.5, AD5

P0.6, AD6

P0.7, AD7

32

31

30

29

28

27

26

25

38

37

36

35

34

33

32

31

P1.7

RST

10

11

12

13

14

15

RXD, P3.0

INT2, P4.3

TXD, P3.1

EA

RXD, P3.0

INT2, P4.3

TXD, P3.1

EA

P4.1

ALE

INT0, P3.2

INT1, P3.3

T0, P3.4

PSEN

P2.7, A15

INT0, P3.2

PSEN

P2.7, A15

INT1, P3.3

T0, P3.4

10

11

12

24

23

P2.6, A14

P2.5, A13

30

29

16

17

P2.6, A14

P2.5, A13

T1, P3.5

13 14 15 16 17 18 19 20 21 22

18 19 20 21 22 23 24 25 26 27 28

P

3

.

P

3

.

X

T

A

L

2

X

T

A

L

1

V

S

P

2

.

P

2

.

P

2

.

P

2

.

P

2

.

P

3

.

P

3

.

X

T

A

L

2

X

T

A

L

1

V

S

P

2

.

P

2

.

P

2

.

P

2

.

P

2

.

P

4

.

P

4

.

6

,

7

,

0

,

1

,

3

,

4

,

2

,

6

,

7

,

0

,

1

,

3

,

4

,

0

2

,

0

/

A

8

A

9

A

1

0

A

1

A

1

2

/

A

8

A

9

A

1

A

1

2

A

1

0

W R

R

D

R

D

- 4 -

W78E65/W78E065A

4. PIN DESCRIPTION

SYMBOL

TYPE

DESCRIPTIONS

EXTERNAL ACCESS ENABLE: This pin forces the processor to execute the

external ROM. The ROM address and data will not be presented on the bus if

I

EA

the EA pin is high.

PROGRAM STORE ENABLE: PSEN enables the external ROM data in the

O H

PSEN

ALE

Port 0 address/data bus. When internal ROM access is performed, no PSEN

strobe signal outputs originate from this pin.

ADDRESS LATCH ENABLE: ALE is used to enable the address latch that

O H separates the address from the data on Port 0. ALE runs at 1/6th of the

oscillator frequency.

RESET: A high on this pin for two machine cycles while the oscillator is

running resets the device.

RST

I L

CRYSTAL 1: This is the crystal oscillator input. This pin may be driven by an

external clock.

XTAL1

I

XTAL2

VSS

O

I

CRYSTAL 2: This is the crystal oscillator output. It is the inversion of XTAL1.

GROUND: ground potential.

VDD

I

POWER SUPPLY: Supply voltage for operation.

PORT 0: Function is the same as that of standard 8052. This port also

I/O D provides a multiplexed low order address/data bus during accesses to

external memory. Port 0 has internal pull-up resisters enabled by software.

P0.0−P0.7

P1.0−P1.7

I/O H PORT 1: Function is the same as that of standard 8052.

PORT 2: Port 2 is a bi-directional I/O port with internal pull-ups. This port also

provides the upper address bits for accesses to external memory. The P2.6

I/O H

P2.0−P2.7

and P2.7 also provide the alternate function REBOOT which is H/W reboot

from LD flash.

I/O H PORT 3: Function is the same as that of the standard 8052.

P3.0−P3.7

P4.0−P4.3

PORT 4: A bi-directional I/O. The P4.3 also provide the alternate function

I/O H

REBOOT which is H/W reboot from LD flash.

* Note: TYPE I: input, O: output, I/O: bi-directional, H: pull-high, L: pull-low, D: open drain

Publication Release Date: January 9, 2006

Revision A7

- 5 -

W78E65/W78E065A

5. BLOCK DIAGRAM

P1.0

Port 1

Latch

Port

1

P1.7

ACC

B

P0.0

Port 0

Latch

Interrupt

Port

0

T1

T2

Timer

2

P0.7

DPTR

Timer

0

Stack

Pointer

Temp Reg.

PC

PSW

ALU

Timer

1

Incrementor

Addr. Reg.

UART

P3.0

P3.7

64KB

Port 3

Latch

SFR RAM

Address

Port

3

Flash E ROM

Instruction

Decoder

&

4KB

Flash EROM

Sequencer

256+1K bytes

RAM & SFR

P2.0

P2.7

Port

2

Port 2

Latch

Bus & Clock

Controller

Port 4

Latch

P4.0

P4.7

Port

4

Oscillator

Reset Block

Power control

ALE

XTAL1 XTAL2

RST

VCC

Vss

PSEN

- 6 -

W78E65/W78E065A

6. FUNCTIONAL DESCRIPTION

The W78E65 architecture consists of a core controller surrounded by various registers, four general

purpose I/O ports, one special purpose programmable 4-bits I/O port, 256+1K bytes of RAM, three

timer/counters, a serial port. The processor supports 111 different opcodes and references both a 64K

program address space and a 64K data storage space.

6.1 RAM

The internal data RAM in the W78E65 is 256+1K bytes. It is divided into two banks: 256 bytes of

scratchpad RAM and 1K bytes of AUX-RAM. These RAMs are addressed by different ways.

• RAM 0H−7FH can be addressed directly and indirectly as the same as in 8051. Address pointers

are R0 and R1 of the selected register bank.

• RAM 80H−FFH can only be addressed indirectly as the same as in 8051. Address pointers are R0,

R1 of the selected registers bank.

• AUX-RAM 0H−3FFH is addressed indirectly as the same way to access external data memory with

the MOVX instruction. Address pointer are R0 and R1 of the selected register bank and DPTR

register. An access to external data memory locations higher than 3FFH will be performed with the

MOVX instruction in the same way as in the 8051. The AUX-RAM is enable after a reset. Setting

the bit 4 in CHPCON register will enable the access to AUX-RAM. When executing from internal

program memory, an access to AUX-RAM will not affect the Ports P0, P2, WR and RD.

Example,

CHPENR

CHPCON

XRAMAH

REG

F6H

BFH

A1H

MOV

ORL

MOV

CHPENR, #87H

CHPENR, #59H

CHPCON, #00010000B ; enable AUX-RAM

CHPENR, #00H

XRAMAH, #01H

R0, #23H

; internal high address

A, #55H

MOVX @R0, A

; Write 55h data to 0123h AUX-RAM address.

; Read data from 02FFh AUX-RAM address.

MOV

XRAMAH, #02H

MOV

R1, #FFH

MOVX

MOV

A, @R1

DPTR, #0134H

A, #78H

MOV

MOVX

MOV

@DPTR, A

DPTR, #7FFFH

A, @DPRT

; Write 78h data to 0134h AUX-RAM address.

MOVX

; Read data from the external 7FFFh address SRAM

Publication Release Date: January 9, 2006

Revision A7

- 7 -

W78E65/W78E065A

6.2 Timers 0, 1, and 2

Timers 0, 1, and 2 each consist of two 8-bit data registers. These are called TL0 and TH0 for Timer 0,

TL1 and TH1 for Timer 1, and TL2 and TH2 for Timer 2. The TCON and TMOD registers provide

control functions for timers 0, 1. The T2CON register provides control functions for Timer 2. RCAP2H

and RCAP2L are used as reload/capture registers for Timer 2. The operations of Timer 0 and Timer 1

are the same as in the W78C51. Timer 2 is a 16-bit timer/counter that is configured and controlled by

the T2CON register. Like Timers 0 and 1, Timer 2 can operate as either an external event counter or

as an internal timer, depending on the setting of bit C/T2 in T2CON. Timer 2 has three operating

modes: capture, auto-reload, and baud rate generator. The clock speed at capture or auto-reload

mode is the same as that of Timers 0 and 1.

6.2.1 Timer 2 Output

If Set T2OE(T2MOD.1) bit and clear C/T2 ( T2CON.1) bit when CPU work at auto-reload mode and

happen overflow, CPU will toggle P1.0 pin.

TIMER 2 Mode

Bit:

7

6

5

4

3

2

1

0

T2OE

Mnemonic: T2MOD

Address: C9H

T2OE: Enable this bit to toggle P1.0 pin while Timer2 has been overflowed.

6.3 Clock

The W78E65 is designed with either a crystal oscillator or an external clock. Internally, the clock is

divided by two before it is used by default. This makes the W78E65 relatively insensitive to duty cycle

variations in the clock.

6.3.1 Crystal Oscillator

The W78E65 incorporates a built-in crystal oscillator. To make the oscillator work, a crystal must be

connected across pins XTAL1 and XTAL2. In addition, a load capacitor must be connected from each

pin to ground.

6.3.2 External Clock

An external clock should be connected to pin XTAL1. Pin XTAL2 should be left unconnected. The

XTAL1 input is a CMOS-type input, as required by the crystal oscillator.

6.4 Power Management

6.4.1 Idle Mode

Setting the IDL bit in the PCON register enters the idle mode. In the idle mode, the internal clock to

the processor is stopped. The peripherals and the interrupt logic continue to be clocked. The

processor will exit idle mode when either an interrupt or a reset occurs.

- 8 -

W78E65/W78E065A

6.4.2 Power-down Mode

When the PD bit in the PCON register is set, the processor enters the power-down mode. In this mode

all of the clocks are stopped, including the oscillator. To exit from power-down mode is by a hardware

reset or external interrupts INT0 to INT1 when enabled and set to level triggered.

6.4.3 Reduce EMI Emission

The W78E65 allows user to diminish the gain of on-chip oscillator amplifier by using programmer to

clear the B7 bit of security register. Once B7 is set to 0, a half of gain will be decreased. Care must be

taken if user attempts to diminish the gain of oscillator amplifier, reducing a half of gain may affect the

external crystal operating improperly at high frequency. The value of C1 and C2 may need some

adjustment while running at lower gain.

ALE OFF Function

Auxiliary Register

Bit:

7

-

6

-

5

-

4

-

3

-

2

-

1

-

0

ALEOFF

Mnemonic: AUXR

Address: 8EH

ALEOFF: Set this bit to disable ALE output.

6.5 Reset

The external RESET signal is sampled at S5P2. To take effect, it must be held high for at least two

machine cycles while the oscillator is running. An internal trigger circuit in the reset line is used to

deglitch the reset line when the W78E65 is used with an external RC network. The reset logic also has

a special glitch removal circuit that ignores glitches on the reset line. During reset, the ports are

initialized to FFH, the stack pointer to 07H, PCON (with the exception of bit 4) to 00H, and all of the

other SFR registers except SBUF to 00H. SBUF is not reset.

Publication Release Date: January 9, 2006

- 9 -

Revision A7

W78E65/W78E065A

6.5.1 W78E65 Special Function Registers (SFRs) and Reset Values

FF

F7

EF

E7

DF

F8

F0

E8

E0

D8

+B

CHPENR

00000000

+ACC

00000000

+P4

PWMP

PWM0

PWM1

PWMCON1

00000000

PWM2

PWM3

11111111

00000000

+PSW

D7

CF

D0

C8

00000000

PWMCON

2

+T2CON

T2MOD

RCAP2L

RCAP2H

00000000

TL2

TH2

PWM4

00000000

SFRFD

+XICON

00000000

+IP

P4CONA

00000000

P4CONB

00000000

SFRAL

SFRAH

SFRCN

00000000

CHPCON

0xx00000

C7

BF

B7

AF

A7

9F

97

8F

87

C0

B8

B0

A8

A0

98

90

88

00000000

+P3

P43AL

00000000

P42AL

P43AH

00000000

P42AH

00000000

+IE

P4CSIN

00000000

+P2

00000000

XRAMAH

00000000

SBUF

11111111

+SCON

00000000

+P1

xxxxxxxx

P41AL

00000000

TH0

P41AH

00000000

TH1

11111111

+TCON

00000000

+P0

TMOD

00000000

SP

TL0

TL1

AUXR

00000000

POR

WDTC

00000000

PCON

00000000

DPL

00000000

DPH

00000000

P40AL

00000000

P40AH

80

11111111

00000111

00000000

00110000

Notes:

1. The SFRs marked with a plus sign(+) are both byte- and bit-addressable.

2. The text of SFR with bold type characters are extension function registers.

- 10 -

W78E65/W78E065A

6.6 Port 4

Port 4, address D8H, is a 8-bit multipurpose programmable I/O port. Each bit can be configured

individually by software. The Port 4 has four different operation modes.

Mode 0: P4.0−P4.3 is a bi-directional I/O port which is same as port 1. P4.2 and P4.3 also serve as

external interrupt INT3 and INT2 if enabled.

Mode 1: P4.0−P4.3 are read strobe signals that are synchronized with RD signal at specified

addresses. These signals can be used as chip-select signals for external peripherals.

Mode 2: P4.0−P4.3 are write strobe signals that are synchronized with WRsignal at specified

addresses. These signals can be used as chip-select signals for external peripherals.

Mode 3: P4.0−P4.3 are read/write strobe signals that are synchronized with RD or WRsignal at

specified addresses. These signals can be used as chip-select signals for external

peripherals.

When Port 4 is configured with the feature of chip-select signals, the chip-select signal address range

depends on the contents of the SFR P4xAH, P4xAL, P4CONA and P4CONB. The registers P4xAH

and P4xAL contain the 16-bit base address of P4.x. The registers P4CONA and P4CONB contain the

control bits to configure the Port 4 operation mode.

6.6.1 Port Options Register

Bit:

7

-

6

-

5

-

4

-

3

-

2

-

1

-

0

P0UP

Mnemonic: POR

Address: 86H

P0UP: Enable Port 0 weak up. The pins of Port 0 can be configured with either the open drain or

standard port with internal pull-up. By the default, Port 0 is an open drain bi-directional I/O port. When

the P0UP bit in the POR register is set, the pins of port 0 will perform a bi-directional I/O port with

internal pull-up that is structurally the same Port2.

6.6.2 INT2 /INT3

Two additional external interrupts, INT2 and INT3 , whose functions are similar to those of external

interrupt 0 and 1 in the standard 80C52. The functions/status of these interrupts are

determined/shown by the bits in the XICON (External Interrupt Control) register. The XICON register is

bit-addressable but is not a standard register in the standard 80C52. Its address is at 0C0H. To

set/clear bits in the XICON register, one can use the "SETB ( CLR ) bit" instruction. For example,

"SETB 0C2H" sets the EX2 bit of XICON.

XICON - external interrupt control (C0H)

PX3

EX3

IE3

IT3

PX2

EX2

IE2

IT2

PX3: External interrupt 3 priority high if set

EX3: External interrupt 3 enable if set

IE3: If IT3 = 1, IE3 is set/cleared automatically by hardware when interrupt is detected/serviced

Publication Release Date: January 9, 2006

- 11 -

Revision A7

W78E65/W78E065A

IT3: External interrupt 3 is falling-edge/low-level triggered when this bit is set/cleared by software

PX2: External interrupt 2 priority high if set

EX2: External interrupt 2 enable if set

IE2: If IT2 = 1, IE2 is set/cleared automatically by hardware when interrupt is detected/serviced

IT2: External interrupt 2 is falling-edge/low-level triggered when this bit is set/cleared by software

Eight-source interrupt information:

POLLING

SEQUENCE WITHIN

PRIORITY LEVEL

ENABLE

REQUIRED

SETTINGS

INTERRUPT

TYPE

EDGE/LEVEL

VECTOR

ADDRESS

INTERRUPT SOURCE

External Interrupt 0

Timer/Counter 0

External Interrupt 1

Timer/Counter 1

Serial Port

03H

0BH

13H

1BH

23H

2BH

33H

3BH

0 (highest)

IE.0

IE.1

TCON.0

1

-

2

IE.2

TCON.2

3

IE.3

-

4

IE.4

-

Timer/Counter 2

External Interrupt 2

External Interrupt 3

5

6

IE.5

-

XICON.2

XICON.6

XICON.0

XICON.3

7 (lowest)

P4CONB (C3H)

BIT

NAME

FUNCTION

00: Mode 0. P4.3 is a general purpose I/O port which is the same as Port1.

01: Mode 1. P4.3 is a Read Strobe signal for chip select purpose. The

address range depends on the SFR P43AH, P43AL, P43CMP1 and

P43CMP0.

10: Mode 2. P4.3 is a Write Strobe signal for chip select purpose. The

address range depends on the SFR P43AH, P43AL, P43CMP1 and

P43CMP0.

P43FUN1

P43FUN0

7, 6

11: Mode 3. P4.3 is a Read/Write Strobe signal for chip select purpose. The

address range depends on the SFR P43AH, P43AL, P43CMP1, and

P43CMP0.

Chip-select signals address comparison:

00: Compare the full address (16 bits length) with the base address register

P43AH, P43AL.

01: Compare the 15 high bits (A15−A1) of address bus with the base address

P43CMP1

P43CMP0

register P43AH, P43AL.

5, 4

10: Compare the 14 high bits (A15−A2) of address bus with the base address

register P43AH, P43AL.

11: Compare the 8 high bits (A15−A8) of address bus with the base address

register P43AH, P43AL.

- 12 -

W78E65/W78E065A

P4CONB (C3H), continued

BIT

NAME

FUNCTION

P42FUN1

P42FUN0

P42CMP1

P42CMP0

The P4.2 function control bits which are the similar definition as P43FUN1,

P43FUN0.

3, 2

The P4.2 address comparator length control bits which are the similar

definition as P43CMP1, P43CMP0.

1, 0

P4CONA (C2H)

BIT

NAME

FUNCTION

P41FUN1

P41FUN0

P41CMP1

P41CMP0

P40FUN1

P40FUN0

P40CMP1

P40CMP0

The P4.1 function control bits which are the similar definition as P43FUN1,

P43FUN0.

7, 6

The P4.1 address comparator length control bits which are the similar

definition as P43CMP1, P43CMP0.

5, 4

3, 2

1, 0

The P4.0 function control bits which are the similar definition as P43FUN1,

P43FUN0.

The P4.0 address comparator length control bits which are the similar

definition as P43CMP1, P43CMP0.

P4CSIN (AEH)

BIT

NAME

FUNCTION

The active polarity of P4.3 when pin P4.3 is defined as read and/or write strobe

signal.

7

P43CSINV = 1: P4.3 is active high when pin P4.3 is defined as read and/or write strobe

signal.

= 0: P4.3 is active low when pin P4.3 is defined as read and/or write strobe signal.

P42CSINV The similarity definition as P43SINV.

6

5

4

3

2

1

0

P41CSINV The similarity definition as P43SINV.

P40CSINV The similarity definition as P43SINV.

-

Reserve

0

6.6.3 Port 4 Base Address Registers

P40AH, P40AL:

The Base address register for comparator of P4.0. P40AH contains the high-order byte of address,

P40AL contains the low-order byte of address.

P41AH, P41AL:

The Base address register for comparator of P4.1. P41AH contains the high-order byte of address,

P41AL contains the low-order byte of address.

Publication Release Date: January 9, 2006

- 13 -

Revision A7

W78E65/W78E065A

P42AH, P42AL:

The Base address register for comparator of P4.2. P42AH contains the high-order byte of address,

P42AL contains the low-order byte of address.

P43AH, P43AL:

The Base address register for comparator of P4.3. P43AH contains the high-order byte of address,

P43AL contains the low-order byte of address.

P4 (D8H)

BIT

7

NAME

P47

P46

P45

P44

P43

P42

P41

P40

FUNCTION

I/O pin

I/O pin.

6

5

4

3

Port 4 Data bit which outputs to pin P4.3 at mode 0.

Port 4 Data bit. which outputs to pin P4.2 at mode 0.

Port 4 Data bit. which outputs to pin P4.1at mode 0.

Port 4 Data bit which outputs to pin P4.0 at mode 0.

2

1

0

Here is an example to program the P4.0 as a write strobe signal at the I/O port address 1234H−1237H

and positive polarity, and P4.1−P4.3 are used as general I/O ports.

MOV P40AH, #12H

MOV P40AL, #34H

; Base I/O address 1234H for P4.0

MOV P4CONA, #00001010B

MOV P4CONB, #00H

MOV P2ECON, #10H

; P4.0 a write strobe signal and address line A0 and A1 are masked.

; P4.1−P4.3 as general I/O port which are the same as PORT1

; Write the P40SINV = 1 to inverse the P4.0 write strobe polarity

; default is negative.

Then any instruction MOVX @DPTR, A (with DPTR = 1234H−1237H) will generate the positive

polarity write strobe signal at pin P4.0. And the instruction MOV P4, #XX will output the bit3 to bit1 of

data #XX to pin P4.3−P4.1.

- 14 -

W78E65/W78E065A

P4xCSINV

P4 REGISTER

P4.x

DATA I/O

RD_CS

MUX 4->1

WR_CS

READ

WRITE

RD/WR_CS

P4.x

ADDRESS BUS

P4xFUN0

P4xFUN1

EQUAL

REGISTER

P4xAL

P4xAH

Bit Length

P4.x INPUT DATA BUS

Selectable

comparator

REGISTER

P4xCMP0

P4xCMP1

6.7 Pulse Width Modulated Outputs (PWM)

There are five pulse width modulated output channels to generate pulses of programmable length and

interval. The repedtition frequency is defined by an 8-bit prescaler PWMP, which supplies the clock for

the counter. The prescaler and counter are common to both PWM channels. The 8-bit counter counts

modular 255 (0−254). The value of the 8-bit counteris compared to the contents of five registers:

PWM0, PWM1, PWM2, PWM3 and PWM4. Provided the contents of either of these registers is

greater than the counter value, the corresponding PWM0, PWM1, PWM2, PWM3 or PWM4 output is

set HIGH. If the contents of these registers are equal to, or less than the counter value, the output will

be LOW. The pulse-width-ratio is thesefore defined by the contents of the registers PWM0, PWM1,

PWM2, PWM3 and PWM4. The pulse-width-ratio is in the range of 0 to 1 and may be programmed in

increments of 1/255. ENPWM0, ENPWM1, ENPWM2, ENPWM3 and ENPWM4 bit will enable or

disable PWM output.

Buffered PWM outputs may be used to drive DC motors. The rotation speed of the motor would be

proportional to the contents of PWM0/1/2/3/4. The repetition frequency fpwm , at the PWM0/1/2/3/4

output is given by:

f

osc

f

pwm

=

2×(1+ PWMP)×255

Prescaler division factor = PWM + 1

(PWMn)

PWMn high/low ratio of PWMn =

255 - (PWMn)

Publication Release Date: January 9, 2006

Revision A7

- 15 -

W78E65/W78E065A

This gives a repetition frequency range of 123 Hz to 31.4 KHz ( fosc = 16 MHz). By loading the PWM

registers with either 00H or FFH, the PWM channels will output a constant HIGH or LOW level,

respectively. Since the 8-bit counter counts modulo 255, it can never actually reach the value of the

PWM registers when they are loaded with FFH.

When a compare register (PWM0, PWM1, PWM2, PWM3, PWM4) is loaded with a new value, the

associated output updated immediately. It does not have to wait until the end of the current counter

period. There is weakly pulled high on PWM output.

PWM0

ENPWM 0/1/2/3/4/5

Register

Counter

X

Y

+

PWM0

(P1.3)

>

PWMP

Counter

1/2

8-bits Counter

PWM0OE

PWM1OE

PWM2OE

-

Fosc

X

Y

PWM1

Register

PWM1

Counter

+

-

PWM1

(P1.4)

>

X

Y

PWM2

Register

PWM2

Counter

+

-

PWM2

(P1.5)

X

Y

PWM3

Register

PWM3

Counter

+

-

PWM3

(P1.6)

PWM3OE

PWM4OE

X

Y

PWM4

Register

PWM4

Counter

+

-

PWM4

(P1.7)

Figure 1 PWM diagram

Please refer as below code.

mov pwmcon1, #00110011b

mov pwmcon2, #00000101b

mov pwmp, #40h

; enable pwm3, 2, 1, 0

; enable pwm4

; Fpwm = XT/(2*(1+pwmp)*255)

jb

mov pwm0, #14h

jb p1.4, $

mov pwm1, #18h

p1.3, $

; duty cycle high/low = pwm0/(255-pmw0)

- 16 -

W78E65/W78E065A

jb

mov pwm2, #20h

jb p1.6, $

mov pwm3, #b0h

jb p1.7, $

p1.5, $

mov pwm4, #40h

mov pwmcon1, #11111111b ; output enable pwm3, 2, 1, 0

PWM3 Register

Bit:

7

6

5

4

3

2

1

0

Mnemonic: PWM3

Address: DEH

PWM2 Register

Bit:

6

5

3

2

Mnemonic: PWM2

Address: DDH

PWM CONTROL 1 Register

Bit:

7

6

5

4

3

2

1

0

PWM3OE

PWM2OE

ENPWM3

ENPWM2

PWM1OE

PWM0OE

ENPWM1

ENWPM0

Mnemonic: PWMCON1

Address: DCH

PWM3OE: Output enable for PWM3

PWM2OE: Output enable for PWM2

ENPWM3: Enable PWM3

ENPWM2: Enable PWM2

PWM1OE: Output enable for PWM1

PWM0OE: Output enable for PWM0

ENPWM1: Enable PWM1

ENPWM0: Enable PWM0

PWM1 Register

Bit:

7

6

5

4

3

2

1

0

Mnemonic: PWM1

Address: DBH

Publication Release Date: January 9, 2006

Revision A7

- 17 -

W78E65/W78E065A

PWM0 Register

Bit:

7

6

5

4

3

2

1

0

Mnemonic: PWM0

Address: DAH

PWMP Register

Bit:

6

5

3

2

Mnemonic: PWMP

Address: D9H

PWM4 Register

Bit:

6

5

3

2

Mnemonic: PWM4

Address: CFH

PWM CONTROL 2 Register

Bit:

7

6

5

4

3

2

1

0

-

PWM4OE

-

ENWPM4

Mnemonic: PWMCON2

Address: CEH

PWM4OE: Output enable for PWM4

ENPWM: Enable for PWM4

6.8 Watchdog Timer

The Watchdog timer is a free-running timer which can be programmed by the user to serve as a

system monitor, a time-base generator or an event timer. It is basically a set of dividers that divide the

system clock. The divider output is selectable and determines the time-out interval. When the time-out

occurs, a system reset can also be caused if it is enabled. The main use of the Watchdog timer is as a

system monitor. This is important in real-time control applications. In case of power glitches or electro-

magnetic interference, the processor may begin to execute errant code. If this is left unchecked the

entire system may crash. The watchdog time-out selection will result in different time-out values

depending on the clock speed. The Watchdog timer will de disabled on reset. In general, software

should restart the Watchdog timer to put it into a known state. The control bits that support the

Watchdog timer are discussed below.

Watchdog Timer Control Register

Bit:

7

6

5

4

-

3

-

2

1

0

ENW

CLRW

WIDL

PS2

PS1

PS0

Mnemonic: WDTC

Address: 8FH

ENW : Enable watch-dog if set.

CLRW: Clear watch-dog timer and prescaler if set. This flag will be cleared automatically

- 18 -

W78E65/W78E065A

WIDL : If this bit is set, watch-dog is enabled under IDLE mode. If cleared, watch-dog is disabled

under IDLE mode. Default is cleared.

PS2, PS1, PS0: Watch-dog prescaler timer select. Prescaler is selected when set PS2−0 as follows:

PS2 PS1 PS0

PRESCALER SELECT

0

1

0

1

0

1

0

1

0

1

0

1

0

1

2

4

8

16

32

64

128

256

The time-out period is obtained using the following equation:

1

14

× 2 × PRESCALER × 1000 × 12 mS

OSC

Before Watchdog time-out occurs, the program must clear the 14-bit timer by writing 1 to WDTC.6

(CLRW). After 1 is written to this bit, the 14-bit timer, prescaler and this bit will be reset on the next

instruction cycle. The Watchdog timer is cleared on reset.

ENW

WIDL

IDLE

EXTERNAL

RESET

INTERNAL

14-BIT TIMER

CLEAR

RESET

PRESCALER

OSC

1/12

CLRW

Watchdog Timer Block Diagram

Typical Watch-Dog time-out period when OSC = 20 MHz

PS2 PS1 PS0

WATCHDOG TIME-OUT PERIOD

19.66 mS

0

1

0

1

0

1

0

1

0

1

0

1

0

1

39.32 mS

78.64 mS

157.28 mS

314.57 mS

629.14 mS

1.25 S

2.50 S

Publication Release Date: January 9, 2006

Revision A7

- 19 -

W78E65/W78E065A

6.9 In-System Programming (ISP) Mode

The W78E65 equips one 64K byte of main ROM bank for application program (called AP FLASH

EPROM) and one 4K byte of auxiliary ROM bank for loader program (called LD FLASH EPROM). In

the normal operation, the microcontroller executes the code in the AP FLASH EPROM. If the content

of AP FLASH EPROM needs to be modified, the W78E65 allows user to activate the In-System

Programming (ISP) mode by setting the CHPCON register. The CHPCON is read-only by default,

software must write two specific values 87H, then 59H sequentially to the CHPENR register to

enable the CHPCON write attribute. Writing CHPENR register with the values except 87H and

59H will close CHPCON register write attribute. The W78E65 achieves all in-system programming

operations including enter/exit ISP Mode, program, erase, read ... etc, during device in the idle mode.

Setting the bit CHPCON.0 the device will enter in-system programming mode after a wake-up from

idle mode. Because device needs proper time to complete the ISP operations before awaken from idle

mode, software may use timer interrupt to control the duration for device wake-up from idle mode. To

perform ISP operation for revising contents of AP FLASH EPROM, software located at AP FLASH

EPROM setting the CHPCON register then enter idle mode, after awaken from idle mode the device

executes the corresponding interrupt service routine in LD FLASH EPROM. Because the device will

clear the program counter while switching from AP FLASH EPROM to LD FLASH EPROM, the first

execution of RETI instruction in interrupt service routine will jump to 00H at LD FLASH EPROM area.

The device offers a software reset for switching back to AP FLASH EPROM while the content of AP

FLASH EPROM has been updated completely. Setting CHPCON register bit 0, 1 and 7 to logic-1

will result a software reset to reset the CPU. The software reset serves as a external reset. This in-

system programming feature makes the job easy and efficient in which the application needs to

update firmware frequently. In some applications, the in-system programming feature make it possible

to easily update the system firmware without opening the chassis.

SFRAH, SFRAL: The objective address of on-chip ROM in the in-system programming mode.

SFRAH contains the high-order byte of address, SFRAL contains the low-order

byte of address.

SFRFD: The programming data for on-chip ROM in programming mode.

SFRCN: The control byte of on-chip ROM programming mode.

SFRCN (C7)

BIT

NAME

FUNCTION

7

-

Reserve.

On-chip ROM bank select for in-system programming.

= 0: 64K bytes ROM bank is selected as destination for re-programming.

= 1: 4K bytes ROM bank is selected as destination for re-programming.

ROM output enable.

6

WFWIN

5

4

OEN

CEN

ROM chip enable.

3, 2, 1, 0

CTRL[3:0] The flash control signals

- 20 -

W78E65/W78E065A

MODE

WFWIN

CTRL<3:0>

OEN

CEN

SFRAH, SFRAL

SFRFD

Erase 64KB AP FLASH

EPROM

0

0010

1

0

X

Program 64KB AP

FLASH EPROM

0

1

0001

0000

0010

0001

0000

1

0

1

0

Address in

X

Data in

Data out

X

Read 64KB AP FLASH

EPROM

Erase 4KB LD FLASH

EPROM

Program 4KB LD

FLASH EPROM

Address in

Data in

Data out

Read 4KB LD FLASH

EPROM

6.9.1 In-System Programming Control Register (CHPCON)

CHPCON (BFH)

BIT

NAME

FUNCTION

SWRESET

When this bit is set to 1, and both FBOOTSL and FPROGEN are set to 1. It

will enforce microcontroller reset to initial condition just like power on reset.

7

6

5

-

Reserve.

This bit is read only. 1: CPU is running LD FLASH EPROM program. 0: CPU

is running AP FLASH EPROM program.

LD/AP

1: Enable on-chip AUX-RAM.

0: Disable the on-chip AUX-RAM

Must be 1

4

ENAUXRAM

3

2

1

-

Reserve.

When this bit is set to 1, and both SWRESET and FPROGEN are set to 1. It

will enforce microcontroller reset to initial condition just like power on reset.

1

0

FBOOTSL

FPROGEN

When this bit is set to 1, and both SWRESET and FBOOTSL are set to 1. It

will enforce microcontroller reset to initial condition just like power on reset.

This register is protected by CHPENR register. Please write as below procedures while you would

like to write CHPCON register.

Mov CHPENR, #87h

Mov CHPENR, #59h

Anl CHPCON, #EFh; Disable AUX-RAM

Mov CHPENR, #0h

Publication Release Date: January 9, 2006

- 21 -

Revision A7

W78E65/W78E065A

6.10 Software Reset

Set CHPCON = 0X83, timer and enter IDLE mode. CPU will reset and restart from APFLASH after

time out.

6.11 H/W Reboot Mode (Boot from LD FLASH EPROM)

By default, the W78E65 boots from AP FLASH EPROM program after a power on reset. On some

occasions, user can force the W78E65 to boot from the LD FLASH EPROM program via following

settings. The possible situation that you need to enter H/W REBOOT mode when the AP FLASH

EPROM program can not run properly and device can not jump back to LD FLASH EPROM to

execute in-system programming function. Then you can use this H/W REBOOT mode to force the

W78E65 jumps to LD FLASH EPROM and executes in-system programming procedure. When you

design your system, you may reserve the pins P2.6, P2.7 to switches or jumpers. For example in a

CD-ROM system, you can connect the P2.6 and P2.7 to PLAY and EJECT buttons on the panel.

When the AP FLASH EPROM program fails to execute the normal application program. User can

press both two buttons at the same time and then turn on the power of the personal computer to force

the W78E65 to enter the H/W REBOOT mode. After power on of personal computer, you can release

both buttons and finish the in-system programming procedure to update the AP FLASH EPROM code.

In application system design, user must take care of the P2, P3, ALE, EA and PSEN pin value at

reset to prevent from accidentally activating the programming mode or H/W REBOOT mode. It is

necessary to add 10K resistor on these P2.6, P2.7 and P4.3 pins.

H/W Reboot Mode

P4.3

X

P2.7

L

P2.6

L

MODE

REBOOT

L

X

The Reset Timing For Entering

F04KBOOT Mode

P2.7

Hi-Z

P2.6

RST

30 mS

10 mS

- 22 -

W78E65/W78E065A

The Algorithm of In-System Programming

Part 1:32KB APROM

procedure of entering

START

In-System Programming Mode

Enter In-System

Programming Mode ?

(conditions depend on

user's application)

No

Yes

Setting control registers

MOV CHPENR,#87H

MOV CHPENR,#59H

MOV CHPCON,#03H

Execute the normal application

program

Setting Timer (about 1.5 us)

and enable timer interrupt

END

Start Timer and enter idle Mode.

(CPU will be wakened from idle mode

by timer interrupt, then enter In-System

Programming mode)

CPU will be wakened by interrupt and

re-boot from 4KB LDROM to execute

the loader program.

Go

Publication Release Date: January 9, 2006

Revision A7

- 23 -

W78E65/W78E065A

Part 2: 4KB LDROM

Go

Procedure of Updating

the 32KB APROM

Timer Interrupt Service Routine:

Stop Timer & disable interrupt

PGM

Yes

Is F04KBOOT Mode?

(CHPCON.7=1)

End of Programming ?

No

Reset the CHPCON Register:

MOV CHPENR,#87H

MOV CHPENR,#59H

MOV CHPCON,#03H

Setting Timer and enable Timer

interrupt for wake-up .

(50us for program operation)

Yes

Is currently in the

F04KBOOT Mode ?

No

Software reset CPU and

re-boot from the 32KB

APROM.

Get the parameters of new code

(Address and data bytes)

Setting Timer and enable Timer

interrupt for wake-up .

(15 ms for erasing operation)

through I/O ports, UART or

other interfaces.

MOV CHPENR,#87H

MOV CHPENR,#59H

MOV CHPCON,#83H

Setting erase operation mode:

MOV SFRCN,#22H

(Erase 32KB APROM)

Setting control registers for

programming:

Hardware Reset

to re-boot from

new 32 KB APROM.

MOV SFRAH,#ADDRESS_H

MOV SFRAL,#ADDRESS_L

MOV SFRFD,#DATA

Start Timer and enter IDLE

Mode.

(S/W reset is

invalid in F04KBOOT

Mode)

MOV SFRCN,#21H

(Erasing...)

End of erase

operation. CPU will

be wakened by Timer

interrupt.

END

Executing new code

from address

00H in the 32KB APROM.

PGM

- 24 -

W78E65/W78E065A

6.12 Security

During the on-chip ROM programming mode, the ROM can be programmed and verified repeatedly.

Until the code inside the ROM is confirmed OK, the code can be protected. The protection of ROM

and those operations on it are described below.

The W78E65 has a Security Register that can be accessed in programming mode. Those bits of the

Security Registers can not be changed once they have been programmed from high to low. They can

only be reset through erase-all operation. The Security Register is located at the 0FFFFH of the LD

FLASH EPROM space.

0000h

4KB On-chip ROM

Program Memory

64KB On-chip ROM

Program Memory

Security Bits

B2 B1 B0

LDROM

B7 Reserved

0FFFh

7FFFh

APROM

B0: Lock bit, logic 0: active

B1: MOVC inhibit,

logic 0: the MOVC instruction in external memory

cannot access the code in internal memory.

logic 1: no restriction.

RReesseerrvveedd

B2: Encryption

logic 0: the encryption logic enable

logic 1: the encryption logic disable

B07: Osillator Control

logic 0: 1/2 gain

FFFFh

Security Register

logic 1: Full gain

Default 1 for all security bits.

Reserved bits must be kept in logic 1.

Special Setting Register

Lock bit

This bit is used to protect the customer's program code in the W78E65. It may be set after the

programmer finishes the programming and verifies sequence. Once this bit is set to logic 0, both the

ROM data and Security Register can not be accessed again.

MOVC Inhibit

This bit is used to restrict the accessible region of the MOVC instruction. It can prevent the MOVC

instruction in external program memory from reading the internal program code. When this bit is set to

logic 0, a MOVC instruction in external program memory space will be able to access code only in the

external memory, not in the internal memory. A MOVC instruction in internal program memory space

will always be able to access the ROM data in both internal and external memory. If this bit is logic 1,

there are no restrictions on the MOVC instruction.

Encryption

This bit is used to enable/disable the encryption logic for code protection. Once encryption feature is

enabled, the data presented on port 0 will be encoded via encryption logic. Only whole chip erase will

reset this bit.

Publication Release Date: January 9, 2006

- 25 -

Revision A7

W78E65/W78E065A

Oscillator Control

W78E65/E516 allow user to diminish the gain of on-chip oscillator amplifier by using programmer to

set the bit B7 of security register. Once B7 is set to 0, a half of gain will be decreased. Care must be

taken if user attempts to diminish the gain of oscillator amplifier, reducing a half of gain may

improperly affect the external crystal operation at high frequency above 24 MHz. The value of R and

C1, C2 may need some adjustment while running at lower gain.

7. ELETRICAL CHARACTERISTICS

7.1 Absolute Maximum Ratings

PARAMETER

DC Power Supply

SYMBOL

MIN.

-0.3

MAX.

+6.0

UNIT

V

V_DD−V_SS

V_IN

Input Voltage

V_SS-0.3

0

V_DD+0.3

70

V

Operating Temperature

Storage Temperature

T_A

°C

T_ST

-55

+150

Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability

of the device.

7.2 DC Characteristics

(V_{DD −}V_SS= 5V ±10%, T_A= 25°C, Fosc = 20MHz, unless otherwise specified.)

SPECIFICATION

SYMBOL

PARAMETER

Operating Voltage

TEST CONDITIONS

MIN.

MAX.

UNIT

V_DD

I_DD

4.5

5.5

V

RST = 1, P0 = V_DD

No load

Operating Current

Idle Current

-

20

mA

μA

V

_DD= 5.5V

Idle mode

_DD= 5.5V

I_IDLE

I_PWDN

I_IN1

6

V

10

Power-down mode

V_DD= 5.5V

Power Down Current

-

Input Current

P1, P2, P3, P4

Input Current

RST

V

_DD= 5.5V

V_IN= 0V or V_DD

_DD= 5.5V

0<V_IN<V_DD

_DD= 5.5V

0V<V_IN<V_DD

_DD= 5.5V

V_IN=2.0V

-50

-10

-500

+10

+300

+10

-

V

I_IN2

Input Leakage Current

V

I_LK

P0, EA

Logic 1 to 0 Transition Current

P1, P2, P3, P4

V

[*4]

I_TL

- 26 -

W78E65/W78E065A

DC Characteristics, continued

SPECIFICATION

SYMBOL

PARAMETER

TEST CONDITIONS

MIN.

MAX.

UNIT

Input Low Voltage

V_IL1

V _IL2

V _IL3

V_IH1

V_IH2

V_IH3

V_OL1

0

0.8

V

V_DD= 4.5V

P0, P1, P2, P3, P4, EA

Input Low Voltage

RST

0

0.8

V

V_DD= 4.5V

Input Low Voltage

XTAL1^[*4]

0.8

V_DD= 4.5V

V_DD= 5.5V

Input High Voltage

2.4

3.5

-

V_DD+0.2

0.45

P0, P1, P2, P3, P4, EA

Input High Voltage

RST

Input High Voltage

XTAL1^[*4]

V_DD= 5.5V

V_DD= 4.5V

Output Low Voltage

P1, P2, P3, P4

Output Low Voltage

I

_OL= +2 mA

V_DD= 4.5V

_OL= +4 mA

V_OL2

Isk1

Isk2

V_OH1

V_OH2

Isr1

-

4

0.45

12

20

-

V

mA

V

P0, ALE, PSEN ^[*3]

I

Sink current

V_DD= 4.5V

P1, P3, P4

VOL = 0.45V

Sink current

V_DD= 4.5V

10

2.4

-120

-8

VOL = 0.45V

P0, P2, ALE, PSEN

V_DD= 4.5V

Output High Voltage

P1, P2, P3, P4

I_OH= -100 μA

Output High Voltage

V_DD= 4.5V

-

V

P0, ALE, PSEN ^[*3]

Source current

P1, P2, P3, P4

Source current

I_OH= -400 μA

V_DD= 4.5V

VOH = 2.4V

-250

-20

uA

mA

V_DD= 4.5V

VOH = 2.4V

Isr2

P0, P2, ALE, PSEN

Notes:

*1. RST pin is a Schmitt trigger input.

*2. P0, ALE and PSEN are tested in the external access mode.

*3. XTAL1 is a CMOS input.

*4. Pins of P1, P2, P3, P4 can source a transition current when they are being externally driven from 1 to 0.

Publication Release Date: January 9, 2006

Revision A7

- 27 -

W78E65/W78E065A

7.3 AC Characteristics

The AC specifications are a function of the particular process used to manufacture the part, the ratings

of the I/O buffers, the capacitive load, and the internal routing capacitance. Most of the specifications

can be expressed in terms of multiple input clock periods (TCP), and actual parts will usually

experience less than a ±20 nS variation.

Clock Input Waveform

XTAL1

T

CH

T

CL

F

T

CP

OP,

PARAMETER

Operating Speed

Clock Period

SYMBOL

F_OP

MIN.

0

TYP.

MAX.

UNIT

MHz

nS

NOTES

-

40

-

1

2

3

T_CP

41.7

20

Clock High

T_CH

-

nS

Clock Low

T_CL

20

-

nS

Notes:

1. The clock may be stopped indefinitely in either state.

2. The TCP specification is used as a reference in other specifications.

3. There are no duty cycle requirements on the XTAL1 input.

- 28 -

W78E65/W78E065A

8. TIMING WAVEFORMS

8.1 Program Fetch Cycle

S1

S2

S3

S4

S5

S6

S1

S2

S3

S4

S5

S6

XTAL1

ALE

T_ALW

T_APL

PSEN

T_PSW

T_AAS

PORT 2

PORT 0

T_PDA

T_AAH

T_PDH,T_PDZ

A0-A7

Code A0-A7

Code

Data

A0-A7

PARAMETER

SYMBOL

TAAS

MIN.

TYP.

MAX.

UNIT

NOTES

Address Valid to ALE Low

-

nS

4

1, 4

4

1 TCP-Δ

-

Address Hold from ALE Low

ALE Low to PSEN Low

TAAH

TAPL

TPDA

-

2 TCP

2

3

PSEN Low to Data Valid

Data Hold after PSEN High

TPDH

TPDZ

TALW

TPSW

0

-

1 TCP

-

1 TCP

Data Float after PSEN High

ALE Pulse Width

2 TCP

3 TCP

-

4

2 TCP-Δ

3 TCP-Δ

PSEN Pulse Width

Notes:

1. P0.0−P0.7, P2.0−P2.7 remain stable throughout entire memory cycle.

2. Memory access time is 3 TCP.

3. Data have been latched internally prior to PSEN going high.

4. "Δ" (due to buffer driving delay and wire loading) is 20 nS.

Publication Release Date: January 9, 2006

Revision A7

- 29 -

W78E65/W78E065A

Timing Waveforms, continued

8.2 Data Read Cycle

S4

S5

S6

S1

S2

S3

S4

S5

S6

S1

S2

S3

XTAL1

ALE

PSEN

PORT 2

A8-A15

DATA

A0-A7

PORT 0

RD

T_DAR

T_DDA

T_DDH,T_DDZ

T_DRD

PARAMETER

ALE Low to RD Low

SYMBOL

T_DAR

MIN.

TYP.

MAX.

3 T_CP+Δ

4 T_CP

2 T_CP

-

UNIT

nS

NOTES

1, 2

1

-

3 T_CP-

Δ

T_DDA

-

0

-

nS

RD Low to Data Valid

Data Hold from RD High

Data Float from RD High

T_DDH

-

nS

T_DDZ

0

nS

T_DRD

6 T_CP

nS

2

6 T_CP-

Δ

RD Pulse Width

Notes:

1. Data memory access time is 8 TCP.

2. "Δ" (due to buffer driving delay and wire loading) is 20 nS.

- 30 -

W78E65/W78E065A

Timing Waveforms, continued

8.3 Data Write Cycle

S4

S5

S6

S1

S2

S3

S4

S5

S6

S1

S2

S3

XTAL1

ALE

PSEN

A8-A15

PORT 2

PORT 0

WR

A0-A7

DATA OUT

DAD

T_DWD

T

T_DWR

T_DAW

PARAMETER

ALE Low to WR Low

Data Valid to WR Low

Data Hold from WR High

WR Pulse Width

SYMBOL

TDAW

MIN.

TYP.

MAX.

UNIT

nS

-

3 TCP-Δ

1 TCP-Δ

6 TCP-Δ

3 TCP+Δ

TDAD

-

nS

TDWD

nS

TDWR

6 TCP

nS

Note: "Δ" (due to buffer driving delay and wire loading) is 20 nS.

Publication Release Date: January 9, 2006

Revision A7

- 31 -

W78E65/W78E065A

Timing Waveforms, continued

8.4 Port Access Cycle

S5

S6

S1

XTAL1

ALE

T

PDS

T

PDA

PDH

PORT

DATA OUT

INPUT

SAMPLE

PARAMETER

SYMBOL

MIN.

1 T_CP

0

TYP.

MAX.

UNIT

nS

Port Input Setup to ALE Low

T_PDS

T_PDH

T_PDA

-

Port Input Hold from ALE Low

Port Output to ALE

nS

1 T_CP

nS

Note: Ports are read during S5P2, and output data becomes available at the end of S6P2. The timing data are referenced to

ALE, since it provides a convenient reference.

- 32 -

W78E65/W78E065A

9. TYPICAL APPLICATION CIRCUIT

9.1 External Program Memory and Crystal

V

DD

AD0

39

38 AD1

37 AD2

31

19

AD0 3

11

12

13

15

16

17

18

19

AD0

AD1

AD2

AD3

AD4

AD5

AD6

AD7

2

5

A0

A1

A2

A3

A4

A5

A0

A1

A2

A3

A4

A5

A6

A7

A8 25

A9 24

A10 21

A11

A12

A13 26

10

9

D0 Q0

D1 Q1

D2 Q2

D3 Q3

D4 Q4

D5 Q5

D6 Q6

D7 Q7

P0.0

P0.1

P0.2

P0.3

P0.4

P0.5

P0.6

P0.7

A0

O0

O1

O2

O3

O4

O5

O6

O7

EA

4

7

AD1

AD2

A1

6

8

A2

XTAL1

AD3

AD4

AD5

36

35

34

AD3 8

AD4 13

AD5 14

9

12

15

16 A6

19

7

10 u

A3

6

A4

R

18

9

5

XTAL2

RST

A5

CRYSTAL

33 AD6

32 AD7

17

AD6

4

A6

3

AD7 18

A7

8.2 K

A8

1

GND

21

22

23

24

25

26

27

28

A8

A9

OC

G

P2.0

P2.1

P2.2

P2.3

P2.4

P2.5

P2.6

P2.7

A9

C1

C2

11

A10

A11

A12

A13

A14

A15

INT0

12

13

14

15

A10

A11

A12

A13

A14

A15

23

2

INT1

T0

T1

74LS373

A14

A15

27

1

P1.0

P1.1

P1.2

P1.3

P1.4

P1.5

P1.6

P1.7

20

22

GND

2

3

4

5

6

7

8

CE

OE

RD

17

16

29

30

11

10

WR

27512

PSEN

ALE

TXD

RXD

W78E58B

Figure A

CRYSTAL

6 MHz

C1

C2

47P

R

47P

30P

15P

10P

5P

-

16 MHz

24 MHz

32 MHz

40 MHz

30P

15P

10P

5P

6.8K

4.7K

Above table shows the reference values for crystal applications.

Notes:

1. C1, C2, R components refer to Figure A

2. Crystal layout must get close to XTAL1 and XTAL2 pins on user's application board.

Publication Release Date: January 9, 2006

Revision A7

- 33 -

W78E65/W78E065A

Typical Application Circuit, continued

9.2 Expanded External Data Memory and Oscillator

V

DD

V

DD

31

19

10

AD0

AD1

AD2

39

38 AD1

37

36

35 AD4

34

33

32

3

4

7

AD0

11 AD0

12 AD1

13 AD2

15 AD3

2

5

6

9

12

15

16

A0 A0

A1 A1

A2 A2

A3 A3

A4 A4

P0.0

P0.1

P0.2

P0.3

P0.4

P0.5

P0.6

P0.7

A0

A1

A2

A3

A4

A5

A6

A7

A8

A9

D0 Q0

D1 Q1

D2 Q2

D3 Q3

D4 Q4

D5 Q5

D6 Q6

D7 Q7

D0

D1

D2

D3

D4

D5

D6

D7

EA

9

8

AD2

AD3

XTAL1

AD3 8

7

OSCILLATOR

10 u

AD4

17 AD5

13

6

16

AD4

18

9

AD5

AD6

AD7

5

14

17

18

A5

A6 A6

XTAL2

AD5

AD6

AD7

4

18

19

AD6

AD7

3

19 A7 A7

A8

8.2 K

25

RST

INT0

GND

A8

1

11

21

22 A9

23 A10

24

25 A12

26

27

28

A9 24

P2.0

P2.1

P2.2

P2.3

P2.4

P2.5

P2.6

P2.7

OC

G

21

23

2

26

1

A10

A11

A12

A13

A14

A10

A11

A12

A13

12

13

14

15

A11

74LS373

INT1

T0

T1

A13

A14

GND

20

22

27

CE

1

2

3

4

5

6

7

8

P1.0

P1.1

P1.2

P1.3

P1.4

P1.5

P1.6

P1.7

OE

WR

RD

17

16

29

30

11

10

WR

20256

PSEN

ALE

TXD

RXD

W78E58B

Figure B

- 34 -

W78E65/W78E065A

10. PACKAGE DIMENSIONS

10.1 44-pin PLCC

H^D

D

6

1

44

40

Dimension in inch Dimension in mm

Symbol

Min. Nom. Max. Min. Nom. Max.

7

39

0.185

4.699

A

A1

A₂

0.020

0.508

0.145 0.150 0.155 3.683 3.81 3.937

0.026 0.028

0.016 0.018

0.032 0.66

0.813

0.559

0.356

0.711

0.457

b

c

1

0.406

0.022

H_E

G^E

E

0.008 0.010 0.014 0.203 0.254

16.46 16.59 16.71

1.27 BSC

0.648 0.653 0.658

D

E

e

G_D

G

H

L

y

BSC

0.050

0.590

0.610

0.630

14.99 15.49 16.00

17.27 17.53 17.78

17

29

0.590

0.680

0.610 0.630

0.700

E

0.690

0.690 0.700

18

28

D

c

E

0.090 0.100

2.54 2.794

0.10

0.110 2.296

0.004

L

Notes:

A2

A¹

A

1. Dimension D & E do not include interlead

flash.

2. Dimension b1 does not include dambar

protrusion/intrusion.

θ

e

b

3. Controlling dimension: Inches

4. General appearance spec. should be based

on final visual inspection spec.

b₁

Seating Plane

y

G_D

Publication Release Date: January 9, 2006

Revision A7

- 35 -

W78E65/W78E065A

11. APPLICATION NOTE

11.1 In-system Programming Software Examples

This application note illustrates the in-system programmability of the Winbond W78E65 ROM

microcontroller. In this example, microcontroller will boot from 64KB AP FLASH EPROM bank and

waiting for a key to enter in-system programming mode for re-programming the contents of 64KB AP

FLASH EPROM. While entering in-system programming mode, microcontroller executes the loader

program in 4KB LD FLASH EPROM bank. The loader program erases the 64KB AP FLASH EPROM

then reads the new code data from external SRAM buffer (or through other interfaces) to update the

64KB AP FLASH EPROM.

EXAMPLE 1:

;*******************************************************************************************************************

;* Example of 64K AP FLASH EPROM program: Program will scan the P1.0. If P1.0 = 0, enters in-

system

;* programming mode for updating the content of AP FLASH EPROM code else executes the current

ROM code.

;* XTAL = 16 MHz

;*******************************************************************************************************************

.chip 8052

.RAMCHK OFF

.symbols

CHPCON EQU

CHPENR EQU

BFH

F6H

C4H

C5H

C6H

C7H

SFRAL

SFRAH

SFRFD

SFRCN

EQU

ORG

0H

LJMP 100H

; JUMP TO MAIN PROGRAM

;************************************************************************

;* TIMER0 SERVICE VECTOR ORG = 000BH

;************************************************************************

ORG 00BH

CLR

TR0

; TR0 = 0, STOP TIMER0

MOV

RETI

TL0, R6

TH0, R7

;************************************************************************

;* 64K AP FLASH EPROM MAIN PROGRAM

;************************************************************************

ORG100H

MAIN_64K:

MOV A, P1

; SCAN P1.0

ANL A, #01H

CJNE A, #01H, PROGRAM_64K; IF P1.0 = 0, ENTER IN-SYSTEM PROGRAMMING MODE

JMP NORMAL_MODE

PROGRAM_64K:

MOV CHPENR, #87H

; CHPENR = 87H, CHPCON REGISTER WRTE ENABLE

- 36 -

W78E65/W78E065A

MOV CHPENR, #59H

MOV CHPCON, #03H

MOV TCON, #00H

MOV IP, #00H

; CHPENR = 59H, CHPCON REGISTER WRITE ENABLE

; CHPCON = 03H, ENTER IN-SYSTEM PROGRAMMING MODE

; TR = 0 TIMER0 STOP

; IP = 00H

MOV IE, #82H

; TIMER0 INTERRUPT ENABLE FOR WAKE-UP FROM IDLE MODE

MOV R6, #F0H

MOV R7, #FFH

; TL0 = F0H

; TH0 = FFH

MOV TL0, R6

MOV TH0, R7

MOV TMOD, #01H

MOV TCON, #10H

MOV PCON, #01H

; TMOD = 01H, SET TIMER0 A 16-BIT TIMER

; TCON = 10H, TR0 = 1, GO

; ENTER IDLE MODE FOR LAUNCHING THE IN-SYSTEM

; PROGRAMMING

;********************************************************************************

;* Normal mode 64KB AP FLASH EPROM program: depending user's application

;********************************************************************************

NORMAL_MODE:

.

; User's application program

EXAMPLE 2:

;******************************************************************************************************************************

Example of 4 KB LD FLASH EPROM program: This loader program will erase the 64KB AP FLASH EPROM first,

then reads the new ;* code from external SRAM and program them into 32 KB AP FLASH EPROM bank. XTAL =

16 MHz

;*****************************************************************************************************************************

.chip 8052

.RAMCHK OFF

.symbols

CHPCON

CHPENR

SFRAL

SFRAH

SFRFD

SFRCN

EQU

BFH

F6H

C4H

C5H

C6H

C7H

ORG 000H

LJMP 100H

; JUMP TO MAIN PROGRAM

;************************************************************************

;* 1. TIMER0 SERVICE VECTOR ORG = 0BH

;************************************************************************

ORG 000BH

CLR TR0

MOV TL0, R6

MOV TH0, R7

RETI

; TR0 = 0, STOP TIMER0

;************************************************************************

;* 4KB LD FLASH EPROM MAIN PROGRAM

;************************************************************************

Publication Release Date: January 9, 2006

Revision A7

- 37 -

W78E65/W78E065A

ORG 100H

MAIN_4K:

MOV SP, #C0H

MOV CHPENR, #87H

MOV CHPENR, #59H

MOV CHPCON, #03H

MOV CHPENR, #00H

; CHPENR = 87H, CHPCON WRITE ENABLE.

; CHPENR = 59H, CHPCON WRITE ENABLE.

; CHPCON = 03H, ENABLE IN-SYSTEM PROGRAMMING.

; DISABLE CHPCON WRITE ATTRIBUTE

MOV TCON, #00H

MOV TMOD, #01H

MOV IP, #00H

; TCON = 00H, TR = 0 TIMER0 STOP

; TMOD = 01H, SET TIMER0 A 16BIT TIMER

; IP = 00H

MOV IE, #82H

; IE = 82H, TIMER0 INTERRUPT ENABLED

MOV R6, #F0H

MOV R7, #FFH

MOV TL0, R6

MOV TH0, R7

MOV TCON, #10H

MOV PCON, #01H

; TCON = 10H, TR0 = 1, GO

; ENTER IDLE MODE

UPDATE_64K:

MOV TCON, #00H

MOV IP, #00H

; TCON = 00H, TR = 0 TIM0 STOP

; IP = 00H

MOV IE, #82H

; IE = 82H, TIMER0 INTERRUPT ENABLED

; TMOD = 01H, MODE1

; SET WAKE-UP TIME FOR ERASE OPERATION, ABOUT 15 mS.

MOV TMOD, #01H

MOV R6, #E0H

DEPENDING

; ON USER'S SYSTEM CLOCK RATE.

MOV R7, #B1H

MOV TL0, R6

MOV TH0, R7

ERASE_P_4K:

MOV SFRCN, #22H

MOV TCON, #10H

MOV PCON, #01H

; SFRCN (C7H) = 22H ERASE 64K

; TCON = 10H, TR0 = 1, GO

; ENTER IDLE MODE (FOR ERASE OPERATION)

;*********************************************************************

;* BLANK CHECK

;*********************************************************************

MOV SFRCN, #0H

MOV SFRAH, #0H

MOV SFRAL, #0H

MOV R6, #FEH

MOV R7, #FFH

MOV TL0,R6

; READ 64KB AP FLASH EPROM MODE

; START ADDRESS = 0H

; SET TIMER FOR READ OPERATION, ABOUT 1.5 μS.

MOV TH0, R7

BLANK_CHECK_LOOP:

SETB TR0

MOV PCON, #01H

MOV A, SFRFD

; ENABLE TIMER 0

; ENTER IDLE MODE

; READ ONE BYTE

CJNE A, #FFH, BLANK_CHECK_ERROR

INC SFRAL

; NEXT ADDRESS

MOV A, SFRAL

JNZ BLANK_CHECK_LOOP

INC SFRAH

- 38 -

W78E65/W78E065A

MOV A, SFRAH

CJNE A, #80H, BLANK_CHECK_LOOP ; END ADDRESS = 7FFFH

JMP PROGRAM_64KROM

BLANK_CHECK_ERROR:

MOV P1, #F0H

MOV P3, #F0H

JMP $

;*******************************************************************************

;* RE-PROGRAMMING 64KB AP FLASH EPROM BANK

;*******************************************************************************

PROGRAM_64KROM:

MOV DPTR, #0H

MOV R2, #00H

MOV R1, #00H

MOV DPTR, #0H

MOV SFRAH, R1

; THE ADDRESS OF NEW ROM CODE

; TARGET LOW BYTE ADDRESS

; TARGET HIGH BYTE ADDRESS

; EXTERNAL SRAM BUFFER ADDRESS

; SFRAH, TARGET HIGH ADDRESS

MOV SFRCN, #21H ; SFRCN (C7H) = 21 (PROGRAM 64K)

MOV R6, #BEH

MOV R7, #FFH

MOV TL0, R6

MOV TH0, R7

; SET TIMER FOR PROGRAMMING, ABOUT 50 μS.

PROG_D_64K:

MOV SFRAL, R2

MOVX A, @DPTR

; SFRAL (C4H) = LOW BYTE ADDRESS

; READ DATA FROM EXTERNAL SRAM BUFFER. BY ACCORDING USER?

; CIRCUIT, USER MUST MODIFY THIS INSTRUCTION TO FETCH CODE

; SFRFD (C6H) = DATA IN

; TCON = 10H, TR0 = 1, GO

; ENTER IDLE MODE (PRORGAMMING)

MOV SFRFD, A

MOV TCON, #10H

MOV PCON, #01H

INC DPTR

INC R2

CJNE R2, #0H, PROG_D_64K

INC R1

MOV SFRAH, R1

CJNE R1, #80H, PROG_D_64K

;*****************************************************************************

; * VERIFY 64KB AP FLASH EPROM BANK

;*****************************************************************************

MOV R4, #03H

MOV R6, #FEH

MOV R7, #FFH

MOV TL0, R6

; ERROR COUNTER

; SET TIMER FOR READ VERIFY, ABOUT 1.5 μS.

MOV TH0, R7

MOV DPTR, #0H

MOV R2, #0H

; The start address of sample code

; Target low byte address

MOV R1, #0H

; Target high byte address

MOV SFRAH, R1

MOV SFRCN, #00H

; SFRAH, Target high address

; SFRCN = 00 (Read ROM CODE)

READ_VERIFY_64K:

MOV SFRAL, R2

; SFRAL (C4H) = LOW ADDRESS

Publication Release Date: January 9, 2006

Revision A7

- 39 -

W78E65/W78E065A

MOV TCON, #10H

MOV PCON, #01H

INC R2

; TCON = 10H, TR0 = 1, GO

MOVX A, @DPTR

INC DPTR

CJNE A, SFRFD, ERROR_64K

CJNE R2, #0H, READ_VERIFY_64K

INC R1

MOV SFRAH, R1

CJNE R1, #80H, READ_VERIFY_64K

;******************************************************************************

;* PROGRAMMING COMPLETLY, SOFTWARE RESET CPU

;******************************************************************************

MOV CHPENR, #87H

MOV CHPENR, #59H

MOV CHPCON, #83H

; CHPENR = 87H

; CHPENR = 59H

; CHPCON = 83H, SOFTWARE RESET.

ERROR_64K:

DJNZ R4, UPDATE_64K ; IF ERROR OCCURS, REPEAT 3 TIMES.

.

; IN-SYSTEM PROGRAMMING FAIL, USER'S PROCESS TO DEAL WITH IT.

- 40 -

W78E65/W78E065A

12. REVISION HISTORY

VERSION

A1

DATE

PAGE

DESCRIPTION

May 14, 2003

Dec. 30, 2004

-

Initial Issued

A2

2

5

Add Lead Free package

Add Lead Free DIP

A3

A4

A5

Feb. 14, 2005

April 20, 2005

June 22, 2005

Remove P4.4 ~ P4.7

38

Add Important Notice

27

32

Correct operating speed from 20Mhz to 40Mhz

Add 32M/40Mhz items in the table

A6

A7

Aug. 25, 2005

Jan. 9, 2006

3, 5

3

Add Port 0 pull-up resisters information

Add W78E65F-40 and W78E065A40FL

Important Notice

Winbond products are not designed, intended, authorized or warranted for use as components

in systems or equipment intended for surgical implantation, atomic energy control

instruments, airplane or spaceship instruments, transportation instruments, traffic signal

instruments, combustion control instruments, or for other applications intended to support or

sustain life. Further more, Winbond products are not intended for applications wherein failure

of Winbond products could result or lead to a situation wherein personal injury, death or

severe property or environmental damage could occur.

Winbond customers using or selling these products for use in such applications do so at their

own risk and agree to fully indemnify Winbond for any damages resulting from such improper

use or sales.

Publication Release Date: January 9, 2006

- 41 -

Revision A7

型号:	W78E065A40DL
是否无铅：	不含铅
是否Rohs认证：	符合
生命周期：	Obsolete
IHS 制造商：	WINBOND ELECTRONICS CORP
零件包装代码：	DIP
包装说明：	ROHS COMPLIANT, DIP-40
针数：	40
Reach Compliance Code：	compliant
ECCN代码：	3A991.A.2
HTS代码：	8542.31.00.01
风险等级：	5.81
具有ADC：	NO
地址总线宽度：	16
位大小：	8
最大时钟频率：	40 MHz
DAC 通道：	NO
DMA 通道：	NO
外部数据总线宽度：	8
JESD-30 代码：	R-PDIP-T40
JESD-609代码：	e3
长度：	52.2 mm
I/O 线路数量：	32
端子数量：	40
最高工作温度：	70 °C
最低工作温度：
PWM 通道：	YES
封装主体材料：	PLASTIC/EPOXY
封装代码：	DIP
封装形状：	RECTANGULAR
封装形式：	IN-LINE
峰值回流温度（摄氏度）：	NOT SPECIFIED
认证状态：	Not Qualified
ROM可编程性：	FLASH
座面最大高度：	5.334 mm
速度：	40 MHz
最大供电电压：	5.5 V
最小供电电压：	4.5 V
标称供电电压：	5 V
表面贴装：	NO
技术：	CMOS
温度等级：	COMMERCIAL
端子面层：	MATTE TIN
端子形式：	THROUGH-HOLE
端子节距：	2.54 mm
端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	15.24 mm
uPs/uCs/外围集成电路类型：	MICROCONTROLLER
Base Number Matches：	1

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