W78LE812F-24全新原装原理图各脚功能电路原理芯片引脚定义-中国IC网-芯三七

W78LE812

8-BIT MTP MICROCONTROLLER

GENERAL DESCRIPTION

The W78LE812 is an 8-bit microcontroller which can accommodate a wide range of supply voltages

with low power consumption. The instruction set for the W78LE812 is fully compatible with the

standard 8051. The W78LE812 contains an 8K bytes MTP ROM (Multiple-Time Programmable

ROM); a 256 bytes RAM; four 8-bit bi-directional and bit-addressable I/O ports; an additional 6-bit I/O

port P4; three 16-bit timer/counters; a hardware watchdog timer and a serial port. These peripherals

are supported by a fourteen sources two-level interrupt capability. To facilitate programming and

verification, the MTP-ROM inside the W78LE812 allows the program memory to be programmed and

read electronically. Once the code is confirmed, the user can protect the code for security.

The W78LE812 microcontroller has two power reduction modes, idle mode and power-down mode,

both of which are software selectable. The idle mode turns off the processor clock but allows for

continued peripheral operation. The power-down mode stops the crystal oscillator for minimum power

consumption. The external clock can be stopped at any time and in any state without affecting the

processor.

FEATURES

· Fully static design 8-bit CMOS microcontroller

· Wide supply voltage of 2.4V to 5.5V

· 256 bytes of on-chip scratchpad RAM

· 8 KB electrically erasable/programmable MTP-ROM

· 64 KB program memory address space

· 64 KB data memory address space

· Four 8-bit bi-directional ports

· Three 16-bit timer/counters

· Timer 2 Clock-out

· One full duplex serial port(UART)

· Watchdog Timer

· Direct LED drive outputs

· Fourteen sources, two-level interrupt capability

· Wake-up via external interrupts at Port 1

· EMI reduction mode

· Built-in power management

· Code protection mechanism

· Packages:

- DIP 40: W78LE812-24

- PLCC 44: W78LE812P-24

- PQFP 44: W78LE812F-24

Publication Release Date: February 1999

- 1 -

Revision A2

W78LE812

PIN CONFIGURATIONS

40-Pin DIP (W78LE812)

1

VDD

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

INT2,,T2, P1.0

INT3,T2EX, P1.1

INT4,P1.2

2

P0.0, AD0

P0.1, AD1

P0.2, AD2

P0.3, AD3

P0.4, AD4

P0.5, AD5

P0.6, AD6

P0.7, AD7

3

4

INT5,P1.3

5

INT6,P1.4

INT7,P1.5

INT8,P1.6

INT9,P1.7

6

7

8

9

RST

A9CTRL,RXD, P3.0

A13CTR,LTXD, P3.1

A14CTRL,INT0, P3.2

10

11

12

13

14

15

16

17

18

19

20

EA,VPP

ALE,P4.5

PSEN,P4.6

P2.7, A15

OECTRL,INT1, P3.3

T0, P3.4

P2.6, A14

P2.5, A13

P2.4, A12

P2.3, A11

P2.2, A10

P2.1, A9

T1, P3.5

CE,WR, P3.6

OE,RD, P3.7

XTAL2

XTAL1

VSS

P2.0, A8

44-Pin PQFP (W78LE812F)

44-Pin PLCC (W78LE812P)

I

N

T

N

T

I

3

N

T

3

,

N

T

,

T

2

E

X

,

I

2

T

2

I

A

D

1

,

A

D

3

,

2

A

D

0

,

A

D

2

,

N

T

N

T

N

T

A

D

3

,

A

D

0

,

A

D

1

,

A

D

2

,

N

T

N

T

N

T

2

,

E

X

,

T

2

,

4

6

5

4

,

6

5

,

P

0

.

P

1

.

P

1

.

P

1

.

P

1

.

P

0

.

P

0

.

P

0

.

P

4

.

P

0

.

P

1

.

P

1

.

P

1

.

P

1

.

P

0

.

P

0

.

P

0

.

P

4

.

1

.

V

D

1

.

V

D

4

3

2

1

0

1

3

2

0

2

4

3

2

1

0

1

2

3

2

0

34

33

43 42 41 40 39 38 37 36

44

35

40

39

6

5

4

3

2

1

44 43 42

41

P0.4, AD4

P0.5, AD5

P0.6, AD6

P0.7, AD7

7

8

9

1

2

3

4

5

6

7

8

9

P0.4, AD4

INT7,P1.5

INT8,P1.6

INT9,P1.7

RST

INT7,P1.5

INT8,P1.6

INT9,P1.7

32

31

30

29

28

27

26

25

38

37

36

35

34

33

32

31

P0.5, AD5

P0.6, AD6

P0.7, AD7

10

11

12

13

14

15

RST

A9CTRL,RXD, P3.0

P4.3

A9CTRL,RXD, P3.0

P4.3

EA,VPP

P4.1

ALE,P4.5

EA,VPP

P4.1

ALE,P4.5

A13CTRL,TXD, P3.1

A14CTRL,INT0, P3.2

OECTRL,INT1, P3.3

T0, P3.4

A13CTRL,TXD, P3.1

A14CTRL,INT0, P3.2

OECTRL,INT1, P3.3

T0, P3.4

PSEN,P4.6

P2.7, A15

P2.6, A14

P2.5, A13

PSEN,P4.6

P2.7, A15

10

11

24

23

16

17

30

29

P2.6, A14

P2.5, A13

T1, P3.5

12 13 14 15 16 17 18 19 20 21 22

18 19 20 21 22 23 24 25 26 27 28

P

3

.

P

3

.

X

T

A

L

2

X

T

A

L

1

V

S

P

2

.

P

2

.

P

2

.

P

2

.

P

2

.

P

4

.

P

3

.

P

3

.

X

T

A

L

2

X

T

A

L

1

V

S

P

2

.

P

2

.

P

2

.

P

2

.

P

2

.

P

4

.

6

,

7

,

3

,

0

1

2

,

4

0

6

,

7

,

0

,

1

,

2

,

3

,

4

,

0

,

A

8

,

A

9

,

/

A

1

A

1

0

A

1

2

/

A

1

A

8

A

9

A

1

0

A

1

2

W

R

W

R

D

R

D

,

/

C

O

C

O

E

- 2 -

W78LE812

PIN DESCRIPTION

SYMBOL

DESCRIPTIONS

EXTERNAL ACCESS ENABLE: This pin forces the processor to execute out of external

ROM. It should be kept high to access internal ROM. The ROM address and data will

EA

not be present on the bus if

pin is high and the program counter is within on-chip

EA

ROM area. Otherwise they will be present on the bus.

PROGRAM STORE ENABLE: enables the external ROM data onto the Port 0

PSEN

address/data bus during fetch and MOVC operations. When internal ROM access is

performed, no strobe signal outputs from this pin. This pin also serves the

PSEN

alternative function P4.6.

ALE

ADDRESS LATCH ENABLE: ALE is used to enable the address latch that separates

the address from the data on Port 0. This pin also serves the alternative function P4.5

RST

RESET: A high on this pin for two machine cycles while the oscillator is running resets

the device.

XTAL1

CRYSTAL1: This is the crystal oscillator input. This pin may be driven by an external

clock.

XTAL2

VSS

CRYSTAL2: This is the crystal oscillator output. It is the inversion of XTAL1.

GROUND: Ground potential

VDD

POWER SUPPLY: Supply voltage for operation.

PORT 0: Port 0 is a bi-directional I/O port which also provides a multiplexed low order

address/data bus during accesses to external memory. The pins of Port 0 can be

individually configured to open-drain or standard port with internal pull-ups.

P0.0- P0.7

PORT 1: Port 1 is a bi-directional I/O port with internal pull-ups. The bits have alternate

functions which are described below:

P1.0- P1.7

T2(P1.0): Timer/Counter 2 external count input

T2EX(P1.1): Timer/Counter 2 Reload/Capture control

INT2- INT9 (P1.0- P1.7):External interrupt 2 to 9

PORT 2: Port 2 is a bi-directional I/O port with internal pull-ups. This port also provides

the upper address bits for accesses to external memory.

PORT 3: Port 3 is a bi-directional I/O port with internal pull-ups. The pins P3.4 to P3.7

can be configured with high sink current which can drive LED displays directly. All bits

have alternate functions, which are described below:

P2.0- P2.7

P3.0- P3.7

RXD(P3.0) : Serial Port receiver input

TXD(P3.1) : Serial Port transmitter output

(P3.2) : External Interrupt 0

INT0

(P3.3) : External Interrupt 1

INT1

T0(P3.4) : Timer 0 External Input

T1(P3.5) : Timer 1 External Input

(P3.6) :External Data Memory Write Strobe

WR

(P3.7) : External Data Memory Read Strobe

RD

P4.0-P4.6 PORT 4: A 6-bit bi-directional I/O port which is bit-addressable. Pins P4.0 to P4.3 are

available on 44-pin PLCC/QFP package. Pins P4.5 and P4.6 are the alternative

function corresponding to ALE and

.

PSEN

Publication Release Date: February 1999

Revision A2

- 3 -

W78LE812

BLOCK DIAGRAM

P1.0

Port 1

Latch

Port

1

P1.7

INT2~9

ACC

B

P0.0

Port 0

Latch

Interrupt

Port

0

T1

T2

Timer

2

P0.7

DPTR

Timer

0

Stack

Pointer

Temp Reg.

PC

PSW

ALU

Timer

1

Incrementor

Addr. Reg.

UART

P3.0

P3.7

Port 3

Latch

SFR RAM

Address

Port

3

Instruction

Decoder

&

Sequencer

256 bytes

RAM & SFR

P2.0

Port

2

Port 2

Latch

Bus & Clock

Controller

P2.7

Port 4

Latch

P4.0

P4.6

Watchdog

Timer

Port

4

Oscillator

Reset Block

Power control

ALE

XTAL1 XTAL2

RST

VCC

Vss

PSEN

FUNCTIONAL DESCRIPTION

The W78LE812 architecture consists of a core controller surrounded by various registers, five general

purpose I/O ports, 256 bytes of RAM, three timer/counters, and a serial port. The processor supports

111 different opcodes and references both a 64K program address space and a 64K data storage

space.

Timers 0, 1, and 2

Timers 0, 1, and 2 each consist of two 8-bit data registers. These are called TL0 and TH0 for Timer 0,

TL1 and TH1 for Timer 1, TL2 and TH2 for Timer 2. The TCON and TMOD registers provide control

functions for timers 0 and 1. The T2CON register provides control functions for Timer 2. RCAP2H

and RCAP2L are used as reload/capture registers for Timer 2. The operations of Timer 0 and Timer 1

are the same as in the W78C51. Timer 2 is a special feature of the W78LE812: it is a 16-bit up/down

counter that is configured and controlled by the T2CON and T2MOD registers. Like Timers 0 and 1,

Timer 2 can operate as either an external event counter or as an internal timer, depending on the

- 4 -

W78LE812

setting of bit C/T2 in T2CON. Timer 2 has three operating modes: capture, auto-reload, and baud rate

generator. The clock speed at capture or auto-reload mode is the same as that of Timers 0 and 1. In

the auto-reload mode, Timer 2 performs a up counter which is similar with standard 8052. When

counting up, an overflow in Timer 2 will cause a reload from RCAP2H and RCAP2L registers. The

Timer 2 also provides a programmable clock-out mode as a clock generator. To enable this mode,

timer 2 has to be configured with a 16-bit auto-reload timer (C/T2 = 0, CP/RL2 = 0) and bit T2OE

(T2MOD.1) must be set to 1. This mode produces a 50% duty cycle clock output and timer 2 roll-

overs will not generate an interrupt. The clock-out frequency depends on the oscillator frequency and

the reload value of registers RCAP2H and RCAP2L. The clock-out frequency is determined by

following equation:

Clock-out Frequency = Oscillator Frequency / [ 4 ´ ( 65536 - RCAP2H, RCAP2L ) ]

OSC

1/2

TL2 TH2

T2 (P1.0)

1/2

TR2 (T2CON.2)

T2EX (P1.1)

RCAP2L

RCAP2H

EXF2

T2CON.6

Timer 2

Interrupt

EXEN2 (T2CON.3)

Timer 2 Clock-Out Mode

TIMER 2 MODE CONTROL

Bit:

7

-

6

5

-

4

-

3

-

2

-

1

T2OE

0

-

Mnemonic: T2MOD

Address: C9h

T2OE: Timer 2 Output Enable. This bit enables/disables the Timer 2 clock-out function.

I/O Port Options

The Port 0 and Port 3 of W78LE812 may be configured with different types by setting the bits of the

Port Options Register POR that is located at 86H. The pins of Port 0 can be configured with either

the open drain or standard port with internal pull-up. By the default, Port 0 is an open drain bi-

directional I/O port. When the PUP bit in the POR register is set, the pins of Port 0 will perform a

quasi-bi-directional I/O port with internal pull-up that is structurally the same as Port 2. The high

nibble of Port 3 (P3.4 to P3.7) can be selected to serve the direct LED displays drive outputs by

setting the HDx bit in the PO register. When the HDx bit is set, the corresponding pin P3.x can sink

about 20mA current for driving LED display directly. After reset, the POR register is cleared and the

pins of Ports 0 and 3 are the same as those of the standard 80C31. The POR register is shown below.

Publication Release Date: February 1999

- 5 -

Revision A2

W78LE812

Port Options Register

Bit:

7

6

5

-

4

3

2

1

0

EP6

EP5

HD7

HD6

HD5

HD4

PUP

Mnemonic: POR

PUP : Enable Port 0 weak pull-up.

HD4- 7 : Enable pins P3.4 to P3.7 individually with High Drive outputs.

Address: 86H

EP5 : Enable P4.5. To set this bit shifts ALE pin to the alternate function P4.5.

EP6 : Enable P4.6. To set this bit shifts PSEN pin to the alternate function P4.6

Port 4

The W78LE812 has one additional bit-addressable I/O port P4 in which the port address is D8H. The

Port 4 contains seven bits; P4.0 to P4.3 are only available on 44-pin PLCC/QFP package; P4.5 and

P4.6 are the alternate function corresponding to pins ALE, PSEN. When program is running in the

internal memory without any access to external memory, ALE and PSEN may be individually

configured to the alternate functions P4.5 and P4.6 that serve as general purpose I/O pins. To enable

I/O port P4.5 and P4.6, the bits EP5 and EP6 in the POR register must be set. During reset, the, ALE

and PSEN perform as in the standard 80C32. The alternate functions P4.5 and P4.6 must be

enabled by software. Care must be taken with the ALE pins when configured as the alternate

functions. The ALE will emit pulses until either the EP5 bit in POR register or AO bit in AUXR register

is set to 1. i.e. User's applications should elude the ALE pulses before software configure it with I/O

port P4.5.

Port 4

Bit:

7

-

6

5

4

-

3

2

1

0

P4.6

P4.5

P4.3

P4.2

P4.1

P4.0

Mnemonic: P4

Address: D8H

Interrupt System

The W78LE812 has twelve interrupt sources:

and

; Timer 0,1 and 2; Serial Port; INT2 to

INT1

INT0

INT9. Each interrupt vectors to a specific location in program memory for its interrupt service routine.

Each of these sources can be individually enabled or disabled by setting or clearing the

corresponding bit in Special Function Register IE0 and IE1. The individual interrupt priority level

depends on the Interrupt Priority Register IP0 and IP1. Additional external interrupts INT2 to INT9 are

level sensitive and may be used to awake the device from power down mode. The Port 1 interrupts

can be initialized to either active HIGH or LOW via setting the Interrupt Polarity Register IX. The IRQ

register contains the flags of Port 1 interrupts. Each flag in IRQ register will be set when a interrupt

request is recognized but must be cleared by software. Note that the interrupt flags have to be

cleared before the interrupt service routine is completed, or else another interrupt will be generated.

- 6 -

W78LE812

Interrupt Enable Register 0

Bit:

7

6

-

5

4

3

2

1

0

EA

ET2

ES

ET1

EX1

ET0

EX0

Mnemonic: IE

Address: A8H

EA : Global enable. Enable/disable all interrupts.

ET2: Enable Timer 2 interrupt.

ES : Enable Serial Port interrupt.

ET1: Enable Timer 1 interrupt

EX1: Enable external interrupt 1

ET0: Enable Timer 0 interrupt

EX0: Enable external interrupt 0

Interrupt Enable Register 1

Bit:

7

6

5

4

3

2

1

0

EX9

EX8

EX7

EX6

EX5

EX4

EX3

EX2

Mnemonic: IE1

Address: E8H

EX9: Enable external interrupt 9

EX8: Enable external interrupt 8

EX7: Enable external interrupt 7

EX6: Enable external interrupt 6

EX5: Enable external interrupt 5

EX4: Enable external interrupt 4

EX3: Enable external interrupt 3

EX2: Enable external interrupt 2

Note: 0 = interrupt disabled, 1 = interrupt enabled.

Interrupt Priority Register 0

Bit:

7

-

6

5

4

3

2

1

0

PS1

PT2

PS

PT1

PX1

PT0

PX0

Mnemonic: IP0

Address: B8h

IP.7: Unused.

PS1: This bit defines the Serial port 1 interrupt priority. PS = 1 sets it to higher priority level.

PT2: This bit defines the Timer 2 interrupt priority. PT2 = 1 sets it to higher priority level.

PS : This bit defines the Serial port 0 interrupt priority. PS = 1 sets it to higher priority level.

PT1: This bit defines the Timer 1 interrupt priority. PT1 = 1 sets it to higher priority level.

PX1: This bit defines the External interrupt 1 priority. PX1 = 1 sets it to higher priority level.

PT0: This bit defines the Timer 0 interrupt priority. PT0 = 1 sets it to higher priority level.

PX0: This bit defines the External interrupt 0 priority. PX0 = 1 sets it to higher priority level.

Publication Release Date: February 1999

Revision A2

- 7 -

W78LE812

Interrupt Priority Register 1

Bit:

7

6

5

4

3

2

1

0

PX9

PX8

PX7

PX6

PX5

PX4

PX3

PX2

Mnemonic: IP1

Address: F8h

PX9: This bit defines the External interrupt 9 priority. PX9 = 1 sets it to higher priority level.

PX8: This bit defines the External interrupt 8 priority. PX8 = 1 sets it to higher priority level.

PX7: This bit defines the External interrupt 7 priority. PX7 = 1 sets it to higher priority level.

PX6: This bit defines the External interrupt 6 priority. PX6 = 1 sets it to higher priority level.

PX5: This bit defines the External interrupt 5 priority. PX5 = 1 sets it to higher priority level.

PX4: This bit defines the External interrupt 4 priority. PX4 = 1 sets it to higher priority level.

PX3: This bit defines the External interrupt 3 priority. PX3 = 1 sets it to higher priority level.

PX2: This bit defines the External interrupt 2 priority. PX2 = 1 sets it to higher priority level.

Interrupt Polarity Register

Bit:

7

6

5

4

3

2

1

0

IL9

IL8

IL7

IL6

IL5

IL4

IL3

IL2

Mnemonic: IX

Address: E9H

IL9: External interrupt 9 polarity level.

IL8: External interrupt 8 polarity level.

IL7: External interrupt 7 polarity level.

IL6: External interrupt 6 polarity level.

IL5: External interrupt 5 polarity level.

IL4: External interrupt 4 polarity level.

IL3: External interrupt 3 polarity level.

IL2: External interrupt 2 polarity level.

Note: 0 = active LOW, 1 = active HIGH.

Interrupt Request Flag Register

Bit:

7

6

5

4

3

2

1

0

IQ9

IQ8

IQ7

IQ6

IQ5

IQ4

IQ3

IQ2

Mnemonic: IRQ

Address: C0H

IQ9: External interrupt 9 request flag.

IQ8: External interrupt 8 request flag.

IQ7: External interrupt 7 request flag.

IQ6: External interrupt 6 request flag.

IQ5: External interrupt 5 request flag.

IQ4: External interrupt 4 request flag.

IQ3: External interrupt 3 request flag.

IQ2: External interrupt 2 request flag.

- 8 -

W78LE812

Table.1 Priority level for simultaneous requests of the same priority interrupt sources

SOURCE

FLAG

PRIORITY LEVEL

VECTOR ADDRESS

External Interrupt 0

Serial Port

IE0

(highest)

0003H

0023H

0053H

000BH

005BH

0013H

003BH

0063H

001BH

002BH

0043H

006BH

004BH

0073H

RI + TI

IQ5

External Interrupt 5

Timer 0 Overflow

External Interrupt 6

External Interrupt 1

External Interrupt 2

External Interrupt 7

Timer 1 Overflow

Timer 2 Overflow

External Interrupt 3

External Interrupt 8

External Interrupt 4

External Interrupt 9

TF0

IQ6

IE1

IQ2

IQ7

TF1

TF2 + EXF2

IQ3

IQ8

IQ4

IQ9

(lowest)

Watchdog Timer

The Watchdog timer is a free-running timer which can be programmed by the user to serve as a

system monitor, a time-base generator or an event timer. It is basically a set of dividers that divide

the system clock. The divider output is selectable and determines the time-out interval. When the

time-out occurs, a system reset can also be caused if it is enabled. The main use of the Watchdog

timer is as a system monitor. This is important in real-time control applications. In case of power

glitches or electro-magnetic interference, the processor may begin to execute errant code. If this is

left unchecked the entire system may crash. The watchdog time-out selection will result in different

time-out values depending on the clock speed. The Watchdog timer will de disabled on reset. In

general, software should restart the Watchdog timer to put it into a known state. The control bits that

support the Watchdog timer are discussed below.

Watchdog Timer Control Register

Bit:

7

6

5

4

-

3

-

2

1

0

ENW

CLRW WIDL

PS2

PS1

PS0

Mnemonic: WDTC

Address: 8FH

ENW : Enable watch-dog if set.

CLRW : Clear watch-dog timer and prescaler if set. This flag will be cleared automatically

WIDL : If this bit is set, watch-dog is enabled under IDLE mode. If cleared, watch-dog is disabled

under IDLE mode. Default is cleared.

Publication Release Date: February 1999

- 9 -

Revision A2

W78LE812

PS2, PS1, PS0 : Watch-dog prescaler timer select. Prescaler is selected when set PS2- 0 as follows:

PS2 PS1 PS0

PRESCALER SELECT

0

1

0

1

0

1

0

1

0

1

0

1

0

1

2

4

8

16

32

64

128

256

The time-out period is obtained using the following equation :

1

14

´ 2 ´ PRESCALER ´ 1000 ´ 12 mS

OSC

Before Watchdog time-out occurs, the program must clear the 14-bit timer by writing 1 to WDTC.6

(CLRW). After 1 is written to this bit, the 14-bit timer , prescaler and this bit will be reset on the next

instruction cycle. The Watchdog timer is cleared on reset.

ENW

WIDL

IDLE

EXTERNAL

RESET

INTERNAL

14-BIT TIMER

CLEAR

RESET

PRESCALER

OSC

1/12

CLRW

Watchdog Timer Block Diagram

Typical Watch-Dog time-out period when OSC = 20 MHz

PS2 PS1 PS0

WATCHDOG TIME-OUT PERIOD

0

1

0

1

0

1

0

1

0

1

0

1

0

1

19.66 mS

39.32 mS

78.64 mS

157.28 mS

314.57 mS

629.14 mS

1.25 s

2.50 s

- 10 -

W78LE812

Clock

The W78LE812 is designed to be used with either a crystal oscillator or an external clock. Internally,

the clock is divided by two before it is used. This makes the W78LE812 relatively insensitive to duty

cycle variations in the clock. The W78LE812 incorporates a built-in crystal oscillator. To make the

oscillator work, a crystal must be connected across pins XTAL1 and XTAL2. In addition, a load

capacitor must be connected from each pin to ground. An external clock source should be connected

to pin XTAL1. Pin XTAL2 should be left unconnected. The XTAL1 input is a CMOS-type input, as

required by the crystal oscillator.

Power Management

Idle Mode

The idle mode is entered by setting the IDL bit in the PCON register. In the idle mode, the internal

clock to the processor is stopped. The peripherals and the interrupt logic continue to be clocked. The

processor will exit idle mode when either an interrupt or a reset occurs.

Power-down Mode

When the PD bit in the PCON register is set, the processor enters the power-down mode. In this

mode all of the clocks are stopped, including the oscillator.

AUXR - Auxiliary Register

Bit:

7

-

6

-

5

-

4

-

3

-

2

-

1

-

0

AO

Mnemonic: AUXR

Turn off ALE signal.

Address: 8Eh

AO:

Reduce EMI Emission

Because of the on-chip MTP-ROM, when a program is running in internal ROM space, the ALE will be

unused. The transition of ALE will cause noise, so it can be turned off to reduce the EMI emission if it

is not needed. Turning off the ALE signal transition only requires setting the bit 0 of the AUXR SFR,

which is located at 08Eh. When ALE is turned off, it will be reactivated when the program accesses

external ROM/RAM data or jumps to execute an external ROM code. The ALE signal will turn off

again after it has been completely accessed or the program returns to internal ROM code space..

Reset

The external RESET signal is sampled at S5P2. To take effect, it must be held high for at least two

machine cycles while the oscillator is running. An internal trigger circuit in the reset line is used to

deglitch the reset line when the W78LE812 is used with an external RC network. The reset logic also

has a special glitch removal circuit that ignores glitches on the reset line.

During reset, the ports are initialized to FFH, the stack pointer to 07H, PCON (with the exception of

bit 4) to 00H, and all of the other SFR registers except SBUF to 00H. SBUF is not reset.

Publication Release Date: February 1999

- 11 -

Revision A2

W78LE812

ON-CHIP MTP ROM CHARACTERISTICS

The W78LE812 has several modes to program the on-chip MTP-ROM. All these operations are

configured by the pins RST, ALE, , A9CTRL(P3.0), A13CTRL(P3.1), A14CTRL(P3.2),

PSEN

(P3.7), A0(P1.0) and VPP(

OECTRL(P3.3),

(P3.6),

). Moreover, the A15- A0(P2.7- P2.0,

EA

CE

OE

P1.7- P1.0) and the D7- D0(P0.7- P0.0) serve as the address and data bus respectively for these

operations.

READ OPERATION

This operation is supported for customer to read their code and the Security bits. The data will not be

valid if the Lock bit is programmed to low.

OUTPUT DISABLE CONDITION

When the

is set to high, no data output appears on the D7..D0.

OE

PROGRAM OPERATION

This operation is used to program the data to MTP ROM and the security bits. Program operation is

done when the VPP is reach to VCP (12.5V) level,

set to low, and

set to high.

CE

OE

PROGRAM VERIFY OPERATION

All the programming data must be checked after program operations. This operation should be

performed after each byte is programmed; it will ensure a substantial program margin.

ERASE OPERATION

An erase operation is the only way to change data from 0 to 1. This operation will erase all the MTP

ROM cells and the security bits from 0 to 1. This erase operation is done when the VPP is reach to

VEP level,

set to low, and

set to high.

CE

OE

ERASE VERIFY OPERATION

After an erase operation, all of the bytes in the chip must be verified to check whether they have been

successfully erased to 1 or not. The erase verify operation automatically ensures a substantial erase

margin. This operation will be done after the erase operation if VPP = VEP(14.5V),

is high and

CE

OE

is low.

PROGRAM/ERASE INHIBIT OPERATION

This operation allows parallel erasing or programming of multiple chips with different data. When

P3.6(_CE) = VIH, P3.7(_OE) = VIH, erasing or programming of non-targeted chips is inhibited. So,

except for the P3.6 and P3.7 pins, the individual chips may have common inputs.

- 12 -

W78LE812

COMPANY/DEVICE ID READ OPERATION

This operation is supported for MTP ROM programmer to get the company ID or device ID on the

W78LE812.

NOTES

OPERATIONS P3.0

(A9

P3.1

(A13

P3.2

(A14

P3.3

(OE

P3.6

P3.7

P2,P1

P0

EA

(

)

(

)

OE

(VPP) (A15..A0) (D7..D0)

CE

CTRL) CTRL) CTRL) CTRL)

Read

0

1

0

1

0

1

0

1

Address Data Out

Hi-Z

Address Data In

Address Data Out @3

Output Disable

Program

1

X

VCP

VEP

Program Verify

Erase

A0:0,

Data In

0FFH

@4

others: X

Erase Verify

1

0

1

0

1

VEP

Address Data Out @5

Program/Erase

Inhibit

X

VCP/

VEP

X

Company ID

Device ID

Notes:

1

0

1

A0 = 0 Data Out

A0 = 1 Data Out

1. All these operations happen in RST = VIH, ALE = VIL and

2. VCP = 12.5V, VEP = 14.5V, VIH = VDD, VIL = VSS.

= VIH.

PSEN

3. The program verify operation follows behind the program operation.

4. This erase operation will erase all the on-chip MTP-ROM cells and the Security bits.

5. The erase verify operation follows behind the erase operation.

SECURITY BITS

During the on-chip MTP-ROM operation mode, the MTP-ROM can be programmed and verified

repeatedly. Until the code inside the MTP-ROM is confirmed OK, the code can be protected. The

protection of MTP ROM and those operations on it are described below.

The W78LE812 has several Special Setting Registers, including the Security Register and

Company/Device ID Registers, which can not be accessed in normal mode. These registers can only

be accessed from the MTP-ROM operation mode. Those bits of the Security Registers can not be

changed once they have been programmed from high to low. They can only be reset through erase-

all operation.

The contents of the Company ID and Device ID registers have been set in factory. Both registers are

addressed by the A0 address line during the same specific condition.

The Security Register is addressed in the MTP-ROM operation mode by address #0FFFFh.

Publication Release Date: February 1999

- 13 -

Revision A2

W78LE812

D7 D6 D5 D4 D3 D2 D1 D0

Company ID (#DAH)

Device ID (#E0H)

Security Bits

0000h

1FFFh

1

0

1

0

1

0

8KB MTP ROM

Program Memory

1

0

Reserved

B2

B1

B0

Reserved

B0 : Lock bit, logic 0 : active

B1 : MOVC inhibit,

logic 0 : the MOVC instruction in external memory

cannot access the code in internal memory.

logic 1 : no restriction.

B2 : Encryption

Security Register

logic 0 : the encryption logic enable

logic 1 : the encryption logic disable

0FFFFh

Default 1 for each bit.

Special Setting Registers

Lock bit

This bit is used to protect the customer's program code in the W78LE812. It may be set after the

programmer finishes the programming and verifies sequence. Once this bit is set to logic 0, both the

MTP ROM data and Special Setting Registers can not be accessed again.

MOVC Inhibit

This bit is used to restrict the accessible region of the MOVC instruction. It can prevent the MOVC

instruction in external program memory from reading the internal program code. When this bit is set

to logic 0, a MOVC instruction in external program memory space will be able to access code only in

the external memory, not in the internal memory. A MOVC instruction in internal program memory

space will always be able to access the ROM data in both internal and external memory. If this bit is

logic 1, there are no restrictions on the MOVC instruction.

Encryption

This bit is used to enable/disable the encryption logic for code protection. Once encryption feature is

enabled, the data presented on port 0 will be encoded via encryption logic. Only whole chip erase will

reset this bit.

+5V

V

DD

PGM DATA

A0 to A7

P1

P0

A0 to A7

P1

P0

V

P3.0

P3.1

P3.2

P3.3

P3.6

P3.7

EA/Vpp

ALE

P3.0

P3.1

P3.2

P3.3

P3.6

P3.7

EA/Vpp

ALE

IL

IH

IL

IH

IL

V

CP

IL

CP

IL

V

RST

V

RST

V

IH

V

PSEN

X'tal1

X'tal2

Vss

X'tal1

X'tal2

Vss

A8 to A15

P2

Programming Configuration

Programming Verification

- 14 -

W78LE812

ABSOLUTE MAXIMUM RATINGS

PARAMETER

DC Power Supply

SYMBOL

MIN.

-0.3

MAX.

UNIT

+7.0

V

VDD- VSS

VIN

Input Voltage

VSS -0.3

0

VDD +0.3

70

V

Operating Temperature

Storage Temperature

TA

°C

TST

-55

+150

Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the

device.

DC CHARACTERISTICS

VSS = 0V, TA = 25° C, unless otherwise specified.

SYMBOL

PARAMETER

SPECIFICATION

TEST CONDITIONS

MIN.

MAX.

5.5

UNIT

VDD

IDD

Operating Voltage

Operating Current

2.4

-

V

20

mA

VDD = 5.5V, 20 Mhz, no load,

RST = 1

-

3

mA

VDD = 2.4V, 12 Mhz, no load,

RST = 1

IIDLE

Idle Current

-

7

mA

VDD = 5.5V, 20 Mhz, no load

VDD = 2.4V, 12 Mhz, no load

VDD = 5.5V, no load

1.5

50

30

IPWDN

Power Down Current

VDD = 2.4V, no load

mA

Input

IIN

Input Current

P1, P2, P3, P4

-50

-10

+10

VDD = 5.5V

VIN = 0V or VDD

mA

ILK

Input Leakage Current

P0, EA

VDD = 5.5V

VSS < VIN < VDD

IIN2

Input Current RST

-10

-60

+0

VDD = 5.5V

0 < VIN < VDD

mA

ILK1

Input Leakage Current

P0, EA

+300

VDD = 5.5V

0V < VIN < VDD

ITL

Logic 1-to-0 Transition

Current P1, P2, P3, P4

-500

-

VDD = 5.5V

VIN = 2V

mA

VIL1

Input Low Voltage

P1, P2, P3, P4

Input Low Voltage

RST^[*3]

0

0.8

0.5

0.8

0.3

V

VDD = 5.5V

VDD = 2.4V

VDD = 5.5V

VDD = 2.4V

VIL2

Publication Release Date: February 1999

Revision A2

- 15 -

W78LE812

DC Characteristics, continued

SYMBOL

PARAMETER

SPECIFICATION

TEST CONDITIONS

MIN.

0

MAX.

0.8

UNIT

VIL3

Input Low Voltage

XTAL1^[*3]

VDD = 5.5V

VDD = 2.4V

VDD = 5.5V

VDD = 2.4V

0

0.6

V

VIH1

Input High Voltage

3.5

1.6

VDD +0.2

P1, P2, P3, P4, EA

Input High Voltage

RST

VIH2

VIH3

3.5

1.7

3.5

1.6

VDD +0.2

V

VDD = 5.5V

VDD = 2.4V

VDD = 5.5V

VDD = 2.4V

Input High Voltage

XTAL1^[*4]

Output

VOL1

Output Low Voltage

P1, P2, P3, P4

-

0.45

0.25

0.45

0.25

V

VDD = 4.5V, IOL = +2 mA

VDD = 2.4V, IOL = +1 mA

VDD = 4.5V, IOL = +4 mA

VDD = 2.4V, IOL = +2 mA

VOL2

Output Low Voltage

P0, ALE, PSEN^[*4]

Output Low Voltage P3

Sink current

[*6]

VOL3

ISK1

-

0.22

12

V

VDD = 4.5V, IOL = +2 mA

VDD = 4.5V, VOL = 0.45V

VDD = 2.4V, VOL = 0.4V

VDD = 4.5V, VOL = 0.45V

VDD = 2.4V, VOL = 0.4V

4

mA

P1, P2, P3[5], P4<0:4>

Sink current

1.8

10

4.5

5.4

18

ISK2

9

P0, ALE, PSEN, P4<5:6>

ISK3

Sink current P3.4 to P3.7

in High-Drive mode

Output High Voltage

P1, P2, P3, P4

12

24

mA

VDD = 4.5V, VOL = 0.45V

VOH1

2.4

1.4

2.4

1.4

-

V

VDD = 4.5V, VOH = -100 mA

VDD = 2.4V, VOH = -20 mA

VDD = 4.5V, IOH = -400 mA

VDD = 2.4V, IOH = -200 mA

VOH2

Output High Voltage

P0, ALE, PSEN^[*4]

Source current

ISR1

ISR2

-120

-20

-250

-40

VDD = 4.5V, VOH = 2.4V

VDD = 2.4V, VOH = 1.4V

VDD = 4.5V, VOH = 2.4V

VDD = 2.4V, VOH = 1.4V

mA

P1, P2, P3, P4<0:4>

Source current

-10

-14

mA

-1.9

-3.3

P0, ALE, PSEN, P4<5:6>

Notes:

*1. RST pin has an internal pull-down.

*2. Pins of P1 and P3 can source a transition current when they are being externally driven from 1 to 0.

*3. RST is a Schmitt trigger input and XTAL1 is a CMOS input.

*4. P0, P2, ALE and

are tested in the external access mode.

PSEN

*5. P3.4 to P3.7 are in normal mode.

*6. P3(P3.4- P3.7) is used LED driver port by set SFR.

- 16 -

W78LE812

AC CHARACTERISTICS

The AC specifications are a function of the particular process used to manufacture the part, the

ratings of the I/O buffers, the capacitive load, and the internal routing capacitance. Most of the

specifications can be expressed in terms of multiple input clock periods (TCP), and actual parts will

usually experience less than a ±20 nS variation. The numbers below represent the performance

expected from a 0.6micron CMOS process when using 2 and 4 mA output buffers.

Clock Input Waveform

XTAL1

T_CH

T_CL

F_OP,

T_CP

PARAMETER

Operating Speed

SYMBOL

MIN.

TYP.

MAX.

UNIT

NOTES

FOP

TCP

TCH

TCL

0

-

24

-

MHz

nS

1

2

3

Clock Period

Clock High

Clock Low

25

10

-

nS

-

nS

Notes:

1. The clock may be stopped indefinitely in either state.

2. The TCP specification is used as a reference in other specifications.

3. There are no duty cycle requirements on the XTAL1 input.

Program Fetch Cycle

PARAMETER

SYMBOL

TAAS

MIN.

TYP.

MAX.

UNIT

nS

NOTES

Address Valid to ALE Low

Address Hold from ALE Low

-

4

1, 4

4

1 TCP -D

-

TAAH

nS

TAPL

nS

ALE Low to PSEN Low

PSEN Low to Data Valid

Data Hold after PSEN High

TPDA

-

2 TCP

nS

2

3

TPDH

TPDZ

TALW

TPSW

0

-

1 TCP

nS

-

1 TCP

Data Float after PSEN High

ALE Pulse Width

2 TCP

3 TCP

-

4

2 TCP -D

3 TCP -D

PSEN Pulse Width

Notes:

1. P0.0- P0.7, P2.0- P2.7 remain stable throughout entire memory cycle.

2. Memory access time is 3 TCP.

3. Data have been latched internally prior to PSEN going high.

4. "D" (due to buffer driving delay and wire loading) is 20 nS.

Publication Release Date: February 1999

Revision A2

- 17 -

W78LE812

Data Read Cycle

PARAMETER

SYMBOL

MIN.

TYP.

MAX.

3 TCP +D

4 TCP

2 TCP

-

UNIT

nS

NOTES

1, 2

TDAR

-

3 TCP -D

ALE Low to RD Low

RD Low to Data Valid

Data Hold from RD High

Data Float from RD High

RD Pulse Width

TDDA

TDDH

TDDZ

TDRD

-

nS

1

0

-

nS

6 TCP

nS

2

6 TCP -D

Notes:

1. Data memory access time is 8 TCP.

2. "D" (due to buffer driving delay and wire loading) is 20 nS.

Data Write Cycle

PARAMETER

ALE Low to WR Low

Data Valid to WR Low

Data Hold from WR High

WR Pulse Width

SYMBOL

MIN.

TYP.

MAX.

UNIT

TDAW

-

nS

3 TCP -D

1 TCP -D

6 TCP -D

3 TCP +D

TDAD

TDWD

TDWR

-

6 TCP

Note: "D" (due to buffer driving delay and wire loading) is 20 nS.

Port Access Cycle

PARAMETER

Port Input Setup to ALE Low

Port Input Hold from ALE Low

Port Output to ALE

SYMBOL

TPDS

MIN.

TYP.

MAX.

UNIT

nS

1 TCP

0

-

TPDH

nS

TPDA

1 TCP

nS

Note: Ports are read during S5P2, and output data becomes available at the end of S6P2. The timing data are referenced to

ALE, since it provides a convenient reference.

- 18 -

W78LE812

Program Operation

PARAMETER

SYMBOL

TVPS

TDS

MIN.

2.0

0

TYP.

MAX.

UNIT

mS

VPP Setup Time

Data Setup Time

Data Hold Time

-

mS

TDH

-

mS

Address Setup Time

Address Hold Time

TAS

-

mS

TAH

mS

TPWP

290

300

310

mS

CE Program Pulse Width for

Program Operation

TOCS

TOCH

TOES

2.0

-

mS

nS

OECTRL Setup Time

OECTRL Hold Time

OE Setup Time

TDFP

TOEV

0

-

130

150

OE High to Output Float

Data Valid from OE

nS

Note: Flash data can be accessed only in flash mode. The RST pin must pull in VIH status, the ALE pin must pull in VIL status, and

the PSEN pin must pull in VIH status.

TIMING WAVEFORMS

Program Fetch Cycle

S1

S2

S3

S4

S5

S6

S1

S2

S3

S4

S5

S6

XTAL1

ALE

T

ALW

T

APL

PSEN

T

PSW

T

AAS

PORT 2

PORT 0

T

PDA

T

AAH

T

PDZ

PDH,

A0-A7

Code

A0-A7

Code

Data

A0-A7

Publication Release Date: February 1999

Revision A2

- 19 -

W78LE812

Data Read Cycle

S4

S5

S6

S1

S2

S3

S4

S5

S6

S1

S2

S3

XTAL1

ALE

PSEN

PORT 2

A8-A15

DATA

A0-A7

PORT 0

RD

TDAR

TDDA

T_DDH,T_DDZ

T_DRD

Data Write Cycle

S4

S5

S6

S1

S2

S3

S4

S5

S6

S1

S2

S3

XTAL1

ALE

PSEN

A8-A15

PORT 2

PORT 0

WR

A0-A7

DATA OUT

T_DWD

T_DAD

T_DWR

T_DAW

- 20 -

W78LE812

Port Access Cycle

S5

S6

S1

XTAL1

ALE

T_PDS

T_PDA

DATA OUT

T_PDH

PORT

INPUT

SAMPLE

Program Operation

Program

Verify

Read Verify

V

IH

P2, P1

(A15... A0)

Address Stable

Address Valid

V

IL

T_AS

V

P3.6

(CE)

IH

T

PWP

V

IL

T_AH

V

P3.3

(OECTRL)

IH

T

OCS

V

T_OCH

IL

P3.7

(OE)

V

IH

T

OES

V

IL

T_DFP

T_DH

V

P0

(A7... A0)

IH

OUT

D

Data In

Data Out

V

IL

T_DS

Vcp

T_OEV

Vpp

V

IH

T

VPS

Publication Release Date: February 1999

Revision A2

- 21 -

W78LE812

TYPICAL APPLICATION CIRCUITS

Expanded External Program Memory and Crystal

V

DD

V

DD

31

19

AD0

AD1

AD2

39

38

37

AD0 3

11 AD0

O0

A0

A1

A2

A3

A4

A5

A6

A7

A8

A9

2 A0

10

9

8

7

6

D0 Q0

D1 Q1

D2 Q2

D3 Q3

D4 Q4

D5 Q5

D6 Q6

D7 Q7

P0.0

P0.1

P0.2

P0.3

P0.4

P0.5

P0.6

P0.7

A0

A1

A2

A3

A4

A5

A6

A7

A8

A9

A10

A11

A12

A13

A14

A15

EA

A1

A2

A3

A4

A5

4

7

8

13

14

17

18

5

6

12

13

15

16

17

18

19

AD1

AD2

AD3

AD4

AD5

AD6

AD7

AD1

AD2

AD3

AD4

AD5

AD6

AD7

O1

O2

O3

O4

O5

O6

O7

XTAL1

36 AD3

9

10 u

C1

AD4

AD5

AD6

AD7

35

34

33

32

12

15

R

18

9

5

XTAL2

RST

CRYSTAL

16 A6

4

19

A7

3

8.2 K

25

24

1

GND

A8

A9

A10

A11

A12

21

22

23

24

25

OC

G

P2.0

P2.1

P2.2

P2.3

P2.4

P2.5

P2.6

P2.7

C2

A10 21

11

INT0

A11

A12

23

2

12

13

14

15

INT1

T0

T1

74373

A13 26

A1427

26 A13

A14

28 A15

A15

1

27

1

2

3

4

5

6

7

8

P1.0

P1.1

P1.2

P1.3

P1.4

P1.5

P1.6

P1.7

GND

20

22

CE

OE

RD

WR

PSEN

ALE

TXD

RXD

17

16

29

30

11

10

27512

W78LE812

Figure A

CRYSTAL

16 MHz

C1

30P

15P

C2

30P

15P

R

-

24 MHz

-

Above table shows the reference values for crystal applications.

Note: C1, C2, R components refer to Figure A.

- 22 -

W78LE812

Typical Application Circuits, continued

Expanded External Data Memory and Oscillator

V

DD

V

DD

31

19

10

P0.0

P0.1

P0.2

P0.3

P0.4

P0.5

P0.6

P0.7

A0

A1

A2

A3

A4

A5

A6

A7

11

12

13

15

16

17

18

19

AD0

AD1

AD2

AD3

AD4

AD5

AD6

AD7

AD0

AD1 4

AD2

AD3 8

AD4

AD5 14

3

A0

A1

A2

A3

A4

39 AD0

AD1

2

5

A0

A1

A2

A3

A4

A5

A6

A7

A8

A9

D0 Q0

D1 Q1

D2 Q2

D3 Q3

D4 Q4

D5 Q5

D6 Q6

D7 Q7

D0

D1

D2

D3

D4

D5

D6

D7

EA

9

8

7

6

5

4

3

38

37 AD2

36 AD3

6

7

XTAL1

OSCILLATOR

10 u

9

12

AD4

35

13

18

9

AD5

34

15 A5

A6

XTAL2

33

AD6

16

19 A7

17

AD6

AD7 18

8.2 K

32 AD7

A8 25

RST

INT0

GND

1

P2.0 21

P2.1

A8

A9

24

21

23

2

26

1

OC

G

11

A10

A11

A12

A13

A14

22

A10

A11

A12

A13

12

13

14

15

P2.2

23

A10

A11

A12

A13

A14

P2.3

24

74373

INT1

T0

T1

P2.4

25

P2.5

26

A14

P2.6

P2.7

27

28

GND

CE

OE

WR

20

22

27

1

2

3

4

5

6

P1.0

P1.1

P1.2

P1.3

P1.4

P1.5

P1.6

P1.7

RD

17

WR 16

29

20256

PSEN

30

11

10

ALE

TXD

RXD

7

8

W78LE812

Figure B

Publication Release Date: February 1999

Revision A2

- 23 -

W78LE812

PACKAGE DIMENSIONS

40-pin DIP

Dimension in inch

Dimension in mm

Symbol

A

Nom.

Min.

Max. Min.

0.210

Max.

5.334

0.010

0.150

0.016

0.048

0.008

0.254

1

A

0.155

0.018

0.050

0.010

2.055

0.160

0.022

0.054

0.014

2.070

0.610

3.81

3.937 4.064

0.457 0.559

2

A

0.406

1.219

0.203

B

1.27

1.372

0.356

1

B

0.254

c

D

E

D

52.20 52.58

40

21

15.494

13.97

2.794

15.24

13.84

2.54

0.590 0.600

14.986

13.72

0.540

0.090

0.120

0

0.545

0.100

0.550

0.110

1

E

2.286

1

e

0.140 3.048

3.302

0.130

3.556

15

1

E

L

a

15

0

17.01

0.630 0.650

0.670

0.090

16.00

16.51

A

e

S

2.286

1

20

Notes:

E

1. Dimension D Max. & S include mold flash or

tie bar burrs.

S

c

2. Dimension E1 does not include interlead flash.

3. Dimension D & E1 include mold mismatch and

are determined at the mold parting line.

4. Dimension B1 does not include dambar

protrusion/intrusion.

5. Controlling dimension: Inches.

6. General appearance spec. should be based on

final visual inspection spec.

A2

A

Base Plane

1

A

.

L

Seating Plane

B

e₁

e

A

a

B ₁

44-pin PLCC

H _D

D

6

1

44

40

Dimension in inch Dimension in mm

Symbol

A

Nom.

Min.

Max. Min.

0.185

Max.

7

39

4.699

0.020

0.145

0.508

A

1

0.150

3.81

0.711

0.457

0.155 3.683

3.937

0.813

0.559

0.356

A₂

0.026 0.028 0.032

0.022

0.66

b

c

1

0.406

0.016 0.018

H _E

G_E

E

0.008 0.010 0.014 0.203 0.254

16.46 16.59 16.71

1.27 BSC

0.648 0.653 0.658

0.050 BSC

D

E

e

0.590

0.680

14.99 15.49 16.00

0.610 0.630

0.690 0.700

17

29

G_D

16.00

17.27 17.53 17.78

14.99 15.49

E

G

18

28

D

H

c

17.27

0.700

17.53 17.78

2.54 2.794

0.10

0.690

H

L

y

E

0.090 0.100

0.110 2.296

0.004

L

Notes:

A ₂

A

1. Dimension D & E do not include interlead

flash.

2. Dimension b1 does not include dambar

protrusion/intrusion.

q

e

b

A₁

3. Controlling dimension: Inches

4. General appearance spec. should be based

on final visual inspection spec.

b ₁

Seating Plane

y

G _D

- 24 -

W78LE812

Package Dimensions, continued

44-pin PQFP

H _D

D

Dimension in mm

Dimension in inch

Symbol

A

Nom.

---

Nom.

---

Min.

---

Max. Min.

Max.

---

34

44

---

0.002

0.075

0.01

0.02

0.25

2.05

0.05

1.90

0.25

0.5

1

A

0.081 0.087

2.20

0.45

A

b

c

2

33

1

0.014

0.006

0.394

0.031

0.520

0.031

0.018

0.010

0.398

0.35

0.101

9.9

0.152

10.00

0.254

0.004

0.390

10.1

0.952

13.45

0.95

1.905

0.08

7

D

E

e

9.9

0.398

0.036

0.530

0.037

10.00

0.80

0.390

0.025

0.510

E

HE

0.635

12.95

0.65

13.2

D

E

H

0.510

0.025

H

L

y

11

0.8

1.6

0.051 0.063 0.075

0.003

1.295

1

12

22

e

b

7

q

0

Notes:

1. Dimension D & E do not include interlead

flash.

c

2. Dimension b does not include dambar

protrusion/intrusion.

A

A ²

3. Controlling dimension: Millimeter

4. General appearance spec. should be based

on final visual inspection spec.

q

A 1

L

See Detail F

y

Seating Plane

L

1

Detail F

Winbond Electronics (H.K.) Ltd.

Winbond Electronics North America Corp.

Headquarters

Rm. 803, World Trade Square, Tower II, Winbond Memory Lab.

No. 4, Creation Rd. III,

Science-Based Industrial Park,

Hsinchu, Taiwan

TEL: 886-3-5770066

FAX: 886-3-5792766

123 Hoi Bun Rd., Kwun Tong,

Winbond Microelectronics Corp.

Kowloon, Hong Kong

TEL: 852-27513100

FAX: 852-27552064

Winbond Systems Lab.

2727 N. First Street, San Jose,

CA 95134, U.S.A.

http://www.winbond.com.tw/

TEL: 408-9436666

Voice & Fax-on-demand: 886-2-27197006

FAX: 408-5441798

Taipei Office

11F, No. 115, Sec. 3, Min-Sheng East Rd.,

Taipei, Taiwan

TEL: 886-2-27190505

FAX: 886-2-27197502

Note: All data and specifications are subject to change without notice.

Publication Release Date: February 1999

Revision A2

- 25 -

型号:	W78LE812F-24
生命周期：	Obsolete
IHS 制造商：	NUVOTON TECHNOLOGY CORP
包装说明：	QFP, QFP44,.5SQ,32
Reach Compliance Code：	compliant
风险等级：	5.8
具有ADC：	NO
地址总线宽度：	16
位大小：	8
CPU系列：	8051
最大时钟频率：	24 MHz
DAC 通道：	NO
DMA 通道：	NO
外部数据总线宽度：	8
JESD-30 代码：	S-PQFP-G44
长度：	10 mm
I/O 线路数量：	37
端子数量：	44
最高工作温度：	70 °C
最低工作温度：
PWM 通道：	NO
封装主体材料：	PLASTIC/EPOXY
封装代码：	QFP
封装等效代码：	QFP44,.5SQ,32
封装形状：	SQUARE
封装形式：	FLATPACK
电源：	2.5/5 V
认证状态：	Not Qualified
RAM（字节）：	256
ROM（单词）：	8192
ROM可编程性：	FLASH
速度：	24 MHz
子类别：	Microcontrollers
最大压摆率：	20 mA
最大供电电压：	5.5 V
最小供电电压：	2.4 V
标称供电电压：	4.5 V
表面贴装：	YES
技术：	CMOS
温度等级：	COMMERCIAL
端子形式：	GULL WING
端子节距：	0.8 mm
端子位置：	QUAD
宽度：	10 mm
Base Number Matches：	1

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