W83194BR-B原理图各脚功能电路原理芯片引脚定义引脚图及功能-中国IC网-芯三七

W83194BR-B

Stepless Clock Gen. For INTEL

Brookdale Chipset

Date: 02/25/2003 Revision: 2.0

W83194BR-B Data Sheet Revision History

NO. Page

s

Dates

Version

Web

Main Contents

Version

n.a.

11

n.a.

1.0

All of the versions before 0.50 are for internal use.

Change version and version on web site to 1.0

1

2

4/1/2002

1.0

1.1

10/1/2002

Modify ratio table of CPU, 3V66, and PCI clock

selection.

3

All

02/20/2003

2.0

Update new form

4

5

6

7

8

9

10

Please note that all data and specifications are subject to change without notice. All

the trademarks of products and companies mentioned in this data sheet belong to

their respective owners.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or

systems where malfunction of these products can reasonably be expected to result

in personal injury. Winbond customers using or selling these products for use in such

applications do so at their own risk and agree to fully indemnify Winbond for any

damages resulting from such improper use or sales.

W83194BR-B

STEPLESS CLOCK FOR INTEL BROOKDALE CHIPSET

TABLE OF CONTENT

1. GENERAL DESCRIPTION..................................................................................... 1

2. PRODUCT FEATURES.......................................................................................... 1

3. PIN CONFIGURATION........................................................................................... 2

4. BLOCK DIAGRAM ................................................................................................. 2

5. PIN DESCRIPTION................................................................................................. 3

5.1 CRYSTAL I/O ........................................................................................................................................3

5.2 CPU, 3V66, AND PCI CLOCK OUTPUTS...........................................................................................3

5.3 I²C CONTROL INTERFACE.................................................................................................................4

5.4 FIXED FREQUENCY OUTPUTS.........................................................................................................5

5.5 POWER PINS........................................................................................................................................5

6. FREQUENCY SELECTION BY HARDWARE OR SOFTWARE ............................ 6

7. I²C CONTROL AND STATUS REGISTERS........................................................... 7

7.1 REGISTER 1: FREQUENCY SELECT REGISTER (DEFAULT = 0).................................................7

7.2 REGISTER 2: CPU CLOCK REGISTER (1 = ENABLE, 0 = STOPPED) ..........................................7

7.3 REGISTER 3: PCI CLOCK REGISTER (1 = ENABLE, 0 = STOPPED) ............................................7

7.4 REGISTER 4: PCI, 48MHZ CLOCK REGISTER (1 = ENABLE, 0 = STOPPED)..............................8

7.5 REGISTER 5: 3V66 CONTROL REGISTER (1 = ENABLE, 0 = STOPPED) ....................................8

7.6 REGISTER 6: WATCHDOG CONTROL REGISTER .........................................................................8

7.7 REGISTER 7: WATCHDOG TIMER REGISTER................................................................................9

7.8 REGISTER 8: M/N PROGRAM REGISTER........................................................................................9

7.9 REGISTER 9: M/N PROGRAM REGISTER........................................................................................9

7.10 REGISTER 10: SPREAD SPECTRUM PROGRAMMING REGISTER.........................................10

7.11 REGISTER 11: DIVISOR AND STEP-LESS ENABLE AND SKEW CONTROL REGISTER.......10

7.12 REGISTER 12: WINBOND CHIP ID REGISTER (READ ONLY)................................................11

7.13 REGISTER 13: WINBOND CHIP ID REGISTER (READ ONLY)................................................11

7.14 REGISTER 81: WINBOND TEST REGISTER I ..............................................................................11

7.15 REGISTER 82: WINBOND TEST REGISTER II .............................................................................11

8. ACCESS INTERFACE.......................................................................................... 12

8.1 BLOCK WRITE PROTOCOL..............................................................................................................12

8.2 BLOCK READ PROTOCOL ...............................................................................................................12

8.3 BYTE WRITE PROTOCOL.................................................................................................................12

8.4 BYTE READ PROTOCOL ..................................................................................................................12

9. SPECIFICATIONS................................................................................................ 13

9.1 ABSOLUTE MAXIMUM RATINGS.....................................................................................................13

Publication Release Date: February 2003

- I -

Revision 2.0

W83194BR-B

STEPLESS CLOCK FOR INTEL BROOKDALE CHIPSET

10. ORDERING INFORMATION............................................................................... 13

11. HOW TO READ THE TOP MARKING................................................................ 14

12. PACKAGE DRAWING AND DIMENSIONS ....................................................... 15

Publication Release Date: February 2003

- II -

Revision 2.0

W83194BR-B

STEPLESS CLOCK FOR INTEL BROOKDALE CHIPSET

1. GENERAL DESCRIPTION

The W83194BR-B is a Clock Synthesizer for Intel Brook dale 845 chipset. W83194BR-B provides all

clocks required for high-speed microprocessor and provides step-less frequency programming and 32

different frequencies of CPU, PCI, and 3V66 clocks setting. All clocks are externally selectable with

smooth transitions.

The W83194BR-B provides I²C serial bus interface to program the registers to enable or disable each

clock outputs and provides -0.5% and +/-0.25% center type spread spectrum or programmable S.S.T.

scale to reduce EMI.

The W83194BR-B also has watch dog timer and reset output pin to support auto-reset when systems

hanging caused by improper frequency setting.

The W83194BR-B accepts a 14.318 MHz reference crystal as its input and runs on a 3.3V supply.

High drive PCI CLOCK outputs typically provide greater than 1 V /ns slew rate into 30 pF loads. CPU

CLOCK outputs typically provide better than 1 V /ns slew rate into 20 pF loads as maintaining 50± 5%

duty cycle. The fixed frequency outputs as REF and 48 MHz provide better than 0.5V /ns slew rate.

2. PRODUCT FEATURES

• 3 pairs of CPU clock outputs

• 4 3V66 clock outputs

• 9 PCI synchronous clocks

• 2 48 MHz clock outputs for USB and DOT

• Skew form CPU to PCI clock 1 to 4 ns, center 2.6 ns

• Smooth frequency switch with selections from 66.6 to 200MHz

• Step-less frequency programming

• I²C 2-Wire serial interface and I²C read back

• -0.5% and +/- 0.25% center type spread spectrum

• Programmable S.S.T. scale to reduce EMI

• Programmable registers to enable/stop each output and select modes

• Watch Dog Timer and RESET# output pins

• 48-pin SSOP package

Publication Release Date: February 2003

- 1 -

Revision 2.0

W83194BR-B

STEPLESS CLOCK FOR INTEL BROOKDALE CHIPSET

3. PIN CONFIGURATION

REF^/FS2&

CPUCLKT0

CPUCLKC0

VDDCPU

CPUCLKT1

CPUCLKC1

GND

VDDREF

XIN

XOUT

1

2

3

4

5

6

7

8

9

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

GND

FS0& /PCICLK_F1^

FS1& /PCICLK_F2^

VDDPCI

VDDCPU

GND

CPUCLKT2

CPUCLKC2

MULTISEL0*

IREF

ENWD*/PCICLK0^

PCICLK1 10

PCICLK2 11

PCICLK3 12

VDDPCI 13

GND 14

PCICLK4 15

PCICLK5 16

PCICLK6 17

VDD3V66 18

GND 19

3V66_1 20

3V66_2 21

3V66_3 22

RESET# 23

VDDA 24

GND

48MHZ_USB /FS3&

48MHZ_DOT

AVDD48

GND

3V66_0/VCH_CLK/FS4&

VDD3V66

GND

SCLK*

SDATA*

VTT_PWRGD/PD#*

GND

#: Active low

^: These outputs have 1.5 ~ 2X drive strength

*: Internal pull up resistor 120K to VDD

&: Internal Pull-down resistor 120K to GND

4. BLOCK DIAGRAM

D

ivider

2

48M

H z

PLL2

X

O

TA

SC

L

X

O

IN

U

REF^

X

T

PLL1

Spread

V

CO CLK

3

CPU CLK _T 0:2

CPU CLK _C 0:2

Spectrum

3

3V 66_0/

1

V C H _C LK

M

/N /R atio

RO

M

3

3V 66_1:3

D

ivider

9

PCICLK _0:6

PCICLK _F 1:2

V

TT_PW RG

FS<0:4>

D

Latch

PO

&

R

Control

Logic

PD #*

U LTSEL0*

RESET#

Rref

M

&

Config

Register

SD

A

TA

*

I2C

SCLK

*

Interface

Publication Release Date: February 2003

Revision 2.0

- 2 -

W83194BR-B

STEPLESS CLOCK FOR INTEL BROOKDALE CHIPSET

5. PIN DESCRIPTION

Buffer type symbol Description

IN

Input

IN_td120k

OUT

OD

I/O

I/OD

#

Input pin and internal 120K pull down

Output

Open Drain

Bi-directional Pin

Bi-directional Pin, Open Drain

Active Low

*

Internal 120kΩ pull-up

Internal 120kΩ pull-down

1.5X~2X strength

&

^

5.1 Crystal I/O

Type

Description

Pin Name

IN

Crystal input with internal loading capacitors (18pF) and

feedback resistors.

3

4

XIN

OUT Crystal output at 14.318MHz nominally with internal loading

capacitors (18pF).

XOUT

5.2 CPU, 3V66, and PCI Clock Outputs

Pin Name

Type

Description

CPUCLKT [0:2]

CPUCLKC [0:2]

OUT Low skew (< 250ps) differential clock outputs for host frequencies of

47, 46, 44,

CPU and chipset

43, 40, 39

IN

Power on trapping for different current reference. The reference

current is referred for Pin 37 (IREF). This pin is latched during

VTT_PWRGD. This pin is internal pull up 120K.

Deciding the reference current for the CPUCLK pairs. The pin

was connected to the precision resistor tied to ground to decide the

appropriate current. There are two modes to select different current

via power on trapping the Pin 38 (MULTISEL0). The table is show

as follows.

38

MULTISEL0*

MULTSEL0 Board

Reference

Output

Ioh @ Z

37

23

IREF

Target Trace R, Iref

Current

0

1

50 Ohms

R=221

Ioh=4*Iref 1.0V @ 50

Ioh=6*Iref 0.7V @ 50

Iref=5.0mA

R=475

50 Ohms

Iref=232mA

OD

System reset signal when the watch dog is time out. This pin will

RESET#

generate 250mS when the watchdog timer is timeout.

Publication Release Date: February 2003

- 3 -

Revision 2.0

W83194BR-B

STEPLESS CLOCK FOR INTEL BROOKDALE CHIPSET

IN

Power good input signal comes from ACPI with high active. This

3.3V input is level sensitive strobe used to determine FS [4:0] and

MULTISEL0 input are valid and is ready to sample. This pin is high

active.

VTT_PWRGD

26

IN

Power Down Function. This is internal 120K pull up. This is multi-

function pin. When the VTT_PWRGD signal is asserted (this is,

turns from a logical Low to high), the pin will be switched into the

function of power down (PD#).

PD#*

3V66_0

OUT

66MHz or 48MHz outputs selected by I2C register.

VCH_CLK

31

5

IN_td120kLatched input for FS4 at initial power up for H/W selecting the

output frequency of CPU 3V66 and PCI clocks. This is internal 120K

pull down.

FS4^&

OUT 3.3V free running PCI clock during normal operation. This pin is with

x1.5 ~ x2 driving strength.

IN_td120kLatched input for FS0 at initial power up for H/W selecting the

output frequency of CPU, 3V66 and PCI clocks. This is internal

120K pull down.

PCICLK_F1^

FS0^&

OUT 3.3V free running PCI clock outputs. This pin is with x1.5 ~ x2

PCICLK_F2^

FS1^&

driving strength.

6

9

IN_td120kLatched input for FS1 at initial power up for H/W selecting the

output frequency of CPU, 3V66 and PCI clocks. This is internal

120K pull down.

OUT 3.3V free running PCI clock outputs. This pin is with x1.5 ~ x2

PCICLK0^{^}

ENWD*

driving strength.

IN

Latched input for ENWD at initial power up for H/W enable the

watch dog timer. This is internal 120K pull up.

10, 11, 12,

15, 16, 17

OUT Low skew (< 250ps) PCI clock outputs.

PCICLK [1:6]

3V66_1, 3V66_2,

3V66_3

OUT 3.3V output clocks for the chipset.

20, 21, 22

5.3 I²C Control Interface

Pin Name

Type

I/OD

Description

Serial data of I²C 2-wire control interface with internal pull-up

resistor.

27

SDATA*

IN

Serial clock of I²C 2-wire control interface with internal pull-up

resistor.

28

SCLK*

Publication Release Date: February 2003

- 4 -

Revision 2.0

W83194BR-B

STEPLESS CLOCK FOR INTEL BROOKDALE CHIPSET

5.4 Fixed Frequency Outputs

Pin Name

Type

OUT

Description

REF^

14.318NHz output. This pin is with x1.5 ~ x2 driving strength.

IN_td120k

Latched input for FS2 at initial power up for H/W selecting the

output frequency of CPU, 3V66 and PCI clocks. This is internal

120K pull down.

48

FS2^&

34

35

48MHz_DOT

48MHz_USB

OUT

IN_td120k

48MHz clock output for DOT.

48MHz clock output for USB.

Latched input for FS3 at initial power up for H/W selecting the

FS3^&

output frequency. This is internal 120K pull down.

5.5 Power Pins

1,

7, 13

18, 30

41, 45

24

Pin Name

VDDREF

VDDPCI

VDD3V66

VDDCPU

VDDA

Description

3.3V power supply for REF.

3.3V power supply for PCI.

3.3V power supply for 3V66.

3.3V power supply for CPU.

3.3V power supply for analog core.

Analog power 3.3V for 48M Hz

Ground pin for 3.3 V

33

AVDD48

4, 8, 14, 19,

25, 29, 32,

36, 42

GND

Publication Release Date: February 2003

Revision 2.0

- 5 -

W83194BR-B

STEPLESS CLOCK FOR INTEL BROOKDALE CHIPSET

6. FREQUENCY SELECTION BY HARDWARE OR SOFTWARE

This frequency table is used at power on latched FS [4:0] value or software programming at SSEL

[4:0] (Register 1 bit 6 ~ 2).

FS4

0

1

FS3

0

1

0

1

FS2

0

1

0

1

0

1

0

1

FS1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

FS0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

CPU (MHz)

100.90

3V66(MHz) PCI (MHz)

33.63

Spread %

+/-0.25%

67.27

66.87

68.67

70.00

71.33

72.67

74.00

76.00

78.00

80.00

84.67

86.67

88.89

56.67

60.00

63.33

66.95

66.67

60.00

62.50

67.45

68.50

69.50

70.50

71.50

72.50

75.00

77.50

80.00

85.00

66.67

100.30

103.00

105.00

107.00

109.00

111.00

114.00

117.00

120.00

127.00

130.00

133.33

170.00

180.00

190.00

133.90

133.33

120.00

125.00

134.90

137.00

139.00

141.00

143.00

145.00

150.00

155.00

160.00

170.00

66.67

33.43

34.33

35.00

35.67

36.33

37.00

38.00

39.00

40.00

42.33

43.33

44.44

28.33

30.00

31.67

33.48

33.33

30.00

31.25

33.73

34.25

34.75

35.25

35.75

36.25

37.50

38.75

40.00

42.50

33.34

33.33

-0.5%

+/-0.25%

-0.5%

+/-0.25%

200.00

Publication Release Date: February 2003

Revision 2.0

- 6 -

W83194BR-B

STEPLESS CLOCK FOR INTEL BROOKDALE CHIPSET

7. I²C CONTROL AND STATUS REGISTERS

7.1 Register 0: Frequency Select Register (Default = 0)

Bit

Name

PWD Description

0

Enable Spread Spectrum in the frequency table.

7

EN_SPSP

0 = Normal

1 = Spread Spectrum enabled

6

5

4

3

2

SSEL [4]

SSEL [3]

SSEL [2]

SSEL [1]

SSEL [0]

0

Frequency selection by software via I²C.

Enable software program FS [4:0].

0

0 = Select frequency by hardware.

1

EN_SSEL

1= Select frequency by software I²C - Bit 6 ~ 2.

Enable reload safe frequency when the watchdog is timeout.

0 = reload the FS [4:0] latched pins when watchdog time out.

0

EN_SAFE_FREQ

1 = reload the safe frequency bit defined at Register 6 bit 4~0.

7.2 Register 1: CPU Clock Register (1 = Enable, 0 = Stopped)

Bit

7

6

Pin NO

47, 46

44, 43

PWD Description

1

CPUCLKT2 / C2

CPUCLKT1 / C1

CPUCLKT0 / C0

FS [4] Read back.

FS [3] Read back

FS [2] Read back

FS [1] Read back

FS [0] Read back

5

4

3

2

1

0

40, 39

1

-

X

7.3 Register 2: PCI Clock Register (1 = Enable, 0 = Stopped)

Bit

7

6

5

4

3

2

1

0

Pin NO

PWD Description

-

X

1

MULTISEL0 trapping pin data read back

PCICLK 6

PCICLK 5

PCICLK 4

PCICLK 3

PCICLK 2

PCICLK 1

PCICLK 0

17

16

15

12

11

10

9

Publication Release Date: February 2003

Revision 2.0

- 7 -

W83194BR-B

STEPLESS CLOCK FOR INTEL BROOKDALE CHIPSET

7.4 Register 3: PCI, 48MHz Clock Register (1 = Enable, 0 = Stopped)

Bit

7

6

5

4

Pin NO

PWD Description

34

35

48

-

1

0

48MHZ_DOT

48MHZ_USB

REF

Reserved

1 = VCH_CLK 48MHz clock output.

0 = 3V66_0 66MHz clock output (default).

Reserved

3

EN_VCH_CLK

2

1

0

-

6

5

1

PCICLK_F1

PCICLK_F0

7.5 Register 4: 3V66 Control Register (1 = Enable, 0 = Stopped)

Bit

7

6

5

4

3

2

1

0

Pin NO

PWD Description

-

1

Reserved

3V66_3

3V66_2

-

22

21

20

31

3V66_1

3V66_0/VCH_CLK

7.6 Register 5: Watchdog Control Register

Bit

Name

PWD Description

7

Reserved

0

Reserved

X

Enable Watchdog Timer if set to 1. Set to 0, disable watchdog timer.

This bit is trapping pin during VTT_PWRGD#. Read this bit will return a

counting state. If timer continues down count, this bit will return 1.

Otherwise, this bit will return 0.

6

EN_WD

0

Watchdog Timeout Status. If the watchdog is started and timer down

counts to zero, this bit will be set to 1. Clear this bit to logic 0, If set to 1,

when the watchdog is restart in the next time. This bit is Read Only.

5

WD_TIMEOUT

4

3

2

1

0

SAF_FREQ [4]

SAF_FREQ [3]

SAF_FREQ [2]

SAF_FREQ [1]

SAF_FREQ [0]

0

Watchdog safe frequency bits. These bits will be reloaded into FS [4:0],

if the watchdog is timeout and enable reload safe frequency bits.

Publication Release Date: February 2003

- 8 -

Revision 2.0

W83194BR-B

STEPLESS CLOCK FOR INTEL BROOKDALE CHIPSET

7.7 Register 6: Watchdog Timer Register

Bit Name

PWD Description

7

6

5

4

3

2

1

0

WD_TIME [7]

0

1

0

WD_TIME [6]

WD_TIME [5]

WD_TIME [4]

WD_TIME [3]

WD_TIME [2]

WD_TIME [1]

WD_TIME [0]

Watchdog timeout time. The bit resolution is 250mS. The default time is

8*250mS = 2.0 seconds. If the watchdog timer is start, this register will

be down count. Read this register will return a down count value.

7.8 Register 7: M/N Program Register

Bit

7

6

5

4

3

2

1

0

Name

N_DIV [8]

TEST1

PWD Description

0

1

0

Programmable N divisor value. Bit 7 ~0 are defined in the Register 9.

Test bit 1. Winbond test bit, do not change them.

Test bit 0. Winbond test bit, do not change them.

TEST0

M_DIV [4]

M_DIV [3]

M_DIV [2]

M_DIV [1]

M_DIV [0]

Programmable M divisor value.

7.9 Register 8: M/N Program Register

Bit

7

6

5

4

3

2

1

0

Name

PWD Description

N_DIV [7]

N_DIV [6]

N_DIV [5]

N_DIV [4]

N_DIV [3]

N_DIV [2]

N_DIV [1]

N_DIV [0]

0

Programmable N divisor value bit 7 ~0. The bit 8 is defined in Register

8.

Publication Release Date: February 2003

- 9 -

Revision 2.0

W83194BR-B

STEPLESS CLOCK FOR INTEL BROOKDALE CHIPSET

7.10 Register 9: Spread Spectrum Programming Register

Bit

7

6

5

4

3

2

1

0

Name

SP_UP [3]

SP_UP [2]

SP_UP [1]

PWD Description

0

1

Spread Spectrum Up Counter bit 3.

Spread Spectrum Up Counter bit 2.

Spread Spectrum Up Counter bit 1.

Spread Spectrum Up Counter bit 0

Spread Spectrum Down Counter bit 3

Spread Spectrum Down Counter bit 2

Spread Spectrum Down Counter bit 1

Spread Spectrum Down Counter bit 0

SP_UP [0]

SP_DOWN [3]

SP_DOWN [2]

SP_DOWN [1]

SP_DOWN [0]

7.11 Register 10: Divisor and Step-less Enable and Skew Control Register

Bit

Name

PWD Description

0: use frequency table

0

1: use M/N register to program frequency

7

EN_MN_PROG

The equation is VCO freq. = 14.318MHz * (N+4)/ M. When the watchdog timer

is timeout, this will be clear. In this time, the frequency is set to hardware

default latched or safe frequency set by EN_SFAE_FREQ (Register 1 bit 0).

Reserved

6

5

4

3

2

1

0

Reserved

RATIO_SEL [2]

RATIO_SEL [1]

RATIO_SEL [0]

0

1

0

CPU, 3V66, and PCI ratio selection. The ratio is shown as following table.

CPU to 3V66 skew.

CPU_3V66_SKEW [2]

CPU_3V66_SKEW [1]

CPU_3V66_SKEW [0]

Table of CPU, 3V66, and PCI clock selection.

Reg10 Bit5 Reg10 Bit4 Reg10 Bit3 VCO / CPU VCO / 3V66 VCO / PCI

SEL2

SEL1

SEL0

Ratio

8

10

12

8

12

X

0

1

0

1

0

1

0

1

0

1

0

1

0

1

2

3

4

6

X

4

5

6

4

6

X

Publication Release Date: February 2003

Revision 2.0

- 10 -

W83194BR-B

STEPLESS CLOCK FOR INTEL BROOKDALE CHIPSET

7.12 Register 11: Winbond Chip ID Register (Read Only)

Bit Name PWD Description

7

6

5

4

3

2

1

0

CHPI_ID [7]

0

1

0

1

0

Winbond Chip ID. W83194BR-B is 0x32.

CHPI_ID [6]

CHPI_ID [5]

CHPI_ID [4]

CHPI_ID [3]

CHPI_ID [2]

CHPI_ID [1]

CHPI_ID [0]

Winbond Chip ID.

7.13 Register 12: Winbond Chip ID Register (Read Only)

Bit Name PWD Description

7

SUB_ID [3]

0

Winbond Sub-Chip ID. The sub-chip ID of W83194BR-B is defined as

0001b.

6

5

4

3

2

1

0

SUB_ID [2]

SUB_ID [1]

SUB_ID [0]

VER_ID [3]

VER_ID [2]

VER_ID [1]

VER_ID [0]

0

1

0

1

Winbond Sub-Chip ID.

Winbond Version ID. The Version ID of W83194BR-B is 0001b.

Winbond Version ID.

7.14 Register 81: Winbond Test Register I

Bit Name PWD Description

7:0 TEST_REG1 00h Winbond Test Register. User don’t write it, otherwise this chip will get an

unexpected result.

7.15 Register 82: Winbond Test Register II

Bit Name

PWD Description

7:0 TEST_REG2 04h Winbond Test Register. User don’t write it, otherwise this chip will get an

unexpected result.

Publication Release Date: February 2003

- 11 -

Revision 2.0

W83194BR-B

STEPLESS CLOCK FOR INTEL BROOKDALE CHIPSET

8. ACCESS INTERFACE

The W83194BR-B provides I²C Serial Bus for microprocessor to read/write internal registers. In the

W83194BR-B is provided Block Read/Block Write and Byte-Data Read/Write protocol. The I²C

address is defined at 0xD2.

8.1 Block Write protocol

8.2 Block Read protocol

## In block mode, the command code must filled 8’h00

8.3 Byte Write protocol

8.4 Byte Read protocol

Publication Release Date: February 2003

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Revision 2.0

W83194BR-B

STEPLESS CLOCK FOR INTEL BROOKDALE CHIPSET

9. SPECIFICATIONS

9.1 ABSOLUTE MAXIMUM RATINGS

Stresses greater than those listed in this table may cause permanent damage to the device.

Precautions should be taken to avoid application of any voltage higher than the maximum rated

voltages to this circuit. Subjection to maximum conditions for extended periods may affect reliability.

Unused inputs must always be tied to an appropriate logic voltage level (Ground or Vdd).

Parameter

Rating

Absolute 3.3V Core Supply Voltage

Absolute 3.3V I/O Supple Voltage

Operating 3.3V Core Supply Voltage

Operating 3.3V I/O Supple Voltage

Storage Temperature

- 0.5 V to + 4.6 V

3.135V to 3.465 V

- 65°C to + 150°C

- 55°C to + 125°C

0°C to + 70°C

Ambient Temperature

Operating Temperature

Input ESD protection (Human body model)

2000V

10. ORDERING INFORMATION

Part Number

Package Type

Production Flow

W83194BR-B

48 PIN SSOP

Commercial, 0°C to +70°C

Publication Release Date: February 2003

Revision 2.0

- 13 -

W83194BR-B

STEPLESS CLOCK FOR INTEL BROOKDALE CHIPSET

11. HOW TO READ THE TOP MARKING

W83194BR-B

28051234

814GBB

1st line: Winbond logo and the type number: W83194BR-B

2nd line: Tracking code 2 8051234

2: wafers manufactured in Winbond FAB 2

8051234: wafer production series lot number

3rd line: Tracking code 814 G BB

814: packages made in '98, week 14

G: assembly house ID; O means OSE, G means GR

A: Internal use code

B: IC revision

All the trademarks of products and companies mentioned in this data sheet belong to their respective

owners.

Publication Release Date: February 2003

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Revision 2.0

W83194BR-B

STEPLESS CLOCK FOR INTEL BROOKDALE CHIPSET

12. PACKAGE DRAWING AND DIMENSIONS

Headquarters

No. 4, Creation Rd. III

Science-Based Industrial Park

Hsinchu, Taiwan

TEL: 886-35-770066

Winbond Electronics

(North America) Corp.

Winbond Electronics (H.K.) Ltd.

Rm. 803, World Trade Square, Tower II

123 Hoi Bun Rd., Kwun Tong

Kowloon, Hong Kong

TEL: 852-27516023-7

FAX: 852-27552064

2727 North First Street

San Jose, California 95134

TEL: 1-408-9436666

FAX: 886-35-789467

www: http://www.winbond.com.tw/

FAX: 1-408-9436668

Taipei Office

9F, No. 480, Rueiguang Road, Neihu District,

Taipei, 114, Taiwan

TEL: 886-2-81777168

FAX: 886-2-87153579

Please note that all data and specifications are subject to change without notice. All the trade marks

of products and companies mentioned in this data sheet belong to their respective owners.

These products are not designed for use in life support appliances, devices, or systems where

malfunction of these products can reasonably be expected to result in personal injury.

Winbond customers using or selling these products for use in such applications do so at their own risk

and agree to fully indemnify Winbond for any damages resulting from such improper use or sale.

Publication Release Date: February 2003

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Revision 2.0

型号:	W83194BR-B
是否Rohs认证：	不符合
生命周期：	Obsolete
IHS 制造商：	WINBOND ELECTRONICS CORP
零件包装代码：	SSOP
包装说明：	SSOP, SSOP48,.4
针数：	48
Reach Compliance Code：	unknown
ECCN代码：	EAR99
HTS代码：	8542.39.00.01
风险等级：	5.79
JESD-30 代码：	R-PDSO-G48
JESD-609代码：	e0
长度：	15.88 mm
端子数量：	48
最高工作温度：	70 °C
最低工作温度：
最大输出时钟频率：	200.1 MHz
封装主体材料：	PLASTIC/EPOXY
封装代码：	SSOP
封装等效代码：	SSOP48,.4
封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, SHRINK PITCH
峰值回流温度（摄氏度）：	240
电源：	3.3 V
主时钟/晶体标称频率：	14.318 MHz
认证状态：	Not Qualified
座面最大高度：	2.79 mm
子类别：	Clock Generators
最大供电电压：	3.465 V
最小供电电压：	3.135 V
标称供电电压：	3.3 V
表面贴装：	YES
技术：	CMOS
温度等级：	COMMERCIAL
端子面层：	TIN LEAD
端子形式：	GULL WING
端子节距：	0.635 mm
端子位置：	DUAL
处于峰值回流温度下的最长时间：	30
宽度：	7.49 mm
uPs/uCs/外围集成电路类型：	CLOCK GENERATOR, PROCESSOR SPECIFIC
Base Number Matches：	1

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