W83195CG-413全新原装原理图各脚功能电路原理芯片引脚定义-中国IC网-芯三七

Winbond Clock Generator

W83195WG-413

W83195CG-413

For ATI P4 Chipset

Date: Feb/27/2006

Revision: 0.6

W83195WG-413/W83195CG-413

STEPLESS FOR ATI P4 CLOCK GENERATOR

W83195WG-413/W83195CG-413 Data Sheet Revision History

Web

Version

Pages

Dates

Version

Main Contents

All of the versions before 0.50 are for internal

use.

1

2

n.a.

01/20/2006

02/27/2006

0.5

0.6

n.a.

8,13

n.a.

Modify default register value in blue text.

3

4

5

6

7

8

9

10

Please note that all data and specifications are subject to change without notice. All

the trademarks of products and companies mentioned in this data sheet belong to

their respective owners.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or

systems where malfunction of these products can reasonably be expected to result

in personal injury. Winbond customers using or selling these products for use in such

applications do so at their own risk and agree to fully indemnify Winbond for any

damages resulting from such improper use or sales.

Publication Release Date: Feb 2006

- I -

Revision 0.6

W83195WG-413/W83195CG-413

STEPLESS FOR ATI P4 CLOCK GENERATOR

TABLE OF CONTENT

1.

2.

3.

4.

5.

6.

7.

GENERAL DESCRIPTION ......................................................................................................... 1

PRODUCT FEATURES .............................................................................................................. 1

PIN CONFIGURATION............................................................................................................... 2

BLOCK DIAGRAM ...................................................................................................................... 2

PIN DESCRIPTION..................................................................................................................... 3

FREQUENCY SELECTION BY HARDWARE OR SOFTWARE ................................................ 5

I²C CONTROL AND STATUS REGISTERS............................................................................... 6

7.1

Register 0: ( Default : 00h )......................................................................................................6

Register 1: ( Default : XXh) ......................................................................................................6

Register 2: ( Default : 03h )......................................................................................................7

Register 3: ( Default : 03h )......................................................................................................7

Register 4: ( Default : FEh) ......................................................................................................8

Register 5: ( Default : 02h )......................................................................................................9

Register 6: ( Default : FFh )......................................................................................................9

Register 7: Winbond Chip ID – Project Code Register ( Default : 06h )...............................10

Register 8: ( Default :D0h )..................................................................................................10

Register 9: ( Default : 7Ah )....................................................................................................11

Register 10: Reserved ( Default : 3Bh ).................................................................................11

Register 11: ( Default : 0Eh )..................................................................................................11

Register 12: ( Default : XXh ).................................................................................................12

Register 13: ( Default : 3Fh )..................................................................................................12

Register 14: ( Default : D0h ) .................................................................................................13

Register 15: ( Default : 5Ch ) .................................................................................................13

Register 16: ( Default : 24h )..................................................................................................14

Register 17: Reserved ( Default : 0Fh ).................................................................................14

Register 18: Reserved ( Default : 7Ah ).................................................................................14

Register 19: ( Default : 04h )..................................................................................................14

Register 20: ( Default : 88h )..................................................................................................15

Register 21: ( Default : ECh ).................................................................................................15

7.2

7.3

7.4

7.5

7.6

7.7

7.8

7.9

7.10

7.11

7.12

7.13

7.14

7.15

7.16

7.17

7.18

7.19

7.20

7.21

7.22

Table3: SRC & ATIG Frequency Selection Table..............................................................................16

ACCESS INTERFACE.............................................................................................................. 17

8.

9.

8.1

8.2

8.3

8.4

Block Write protocol ...............................................................................................................17

Block Read protocol...............................................................................................................17

Byte Write protocol.................................................................................................................17

Byte Read protocol.................................................................................................................17

SPECIFICATIONS .................................................................................................................... 18

Publication Release Date: Feb 2006

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Revision 0.6

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STEPLESS FOR ATI P4 CLOCK GENERATOR

9.1

9.2

9.3

9.4

9.5

9.6

9.7

9.8

9.9

ABSOLUTE MAXIMUM RATINGS .......................................................................................18

General Operating Characteristics ........................................................................................18

Skew Group timing clock........................................................................................................18

CPU 0.7V Electrical Characteristics ......................................................................................19

SRC 0.7V Electrical Characteristics ......................................................................................19

ATIG 0.7V Electrical Characteristics......................................................................................19

PCI Electrical Characteristics.................................................................................................20

USB Electrical Characteristics ...............................................................................................20

REF Electrical Characteristics ...............................................................................................20

10.

11.

12.

ORDERING INFORMATION..................................................................................................... 21

HOW TO READ THE TOP MARKING...................................................................................... 21

PACKAGE DRAWING AND DIMENSIONS.............................................................................. 22

Publication Release Date: Feb 2006

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Revision 0.6

W83195WG-413/W83195CG-413

STEPLESS FOR ATI P4 CLOCK GENERATOR

1. GENERAL DESCRIPTION

The W83195WG-413/W83195CG-413 is a Clock Synthesizer for ATI P4 serial chipsets. W83195WG-

413/ W83195CG-413 provides all clocks required for the high-speed microprocessor and provides

step-less frequency programming and 32 different frequencies of CPU, PCI, and SRC clocks setting,

all clocks are externally selectable with smooth transitions.

The W83195WG-413/W83195CG-413 provides I²C serial bus interface to program the registers to

enable or disable each clock outputs and provides programmable S.S.T. scale to reduce EMI.

The W83195WG-413/W83195CG-413 accepts a 14.318 MHz reference crystal as its input and runs

on a 3.3V supply.

2. PRODUCT FEATURES

•

3 pair current-mode Differential clock outputs for CPU.

6 pair current-mode Differential clock outputs for SRC.

2 pair current-mode Differential clock outputs for ATIG programmable.

1 PCI clock output.

1 48 MHz clock output for USB.

3 14.318MHz REF clock outputs.

Smooth frequency switch with selections from 100 to 400MHz.

Step-less frequency programming.

I²C 2-wire serial interface and support byte read/write and block read/write.

Programmable S.S.T. scale to reduce EMI in M/N mode.

Programmable registers to enable/disable each output and select modes.

Programmable clock outputs slew rate control and skew control.

•

56 pin TSSOP/SSOP package.

Publication Release Date: Feb 2006

Revision 0.6

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STEPLESS FOR ATI P4 CLOCK GENERATOR

3. PIN CONFIGURATION

1

2

3

4

5

6

7

8

XIN

XOUT

VDD48

USB_48

GND

VDDREF

GND

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

^&FSA/REF0

^&FSB/REF1

REF2

VTT_PG#/PD

SCLK

VDDPCI

^&CK410#/PCICLK0

GND

*CPU_STOP#

CPUT0

CPUC0

VDDCPU

GND

CPUT1

CPUC1

CPUT2_ITP

CPUC2_ITP

VDDA

GNDA

IREF

GND

VDDSRC

SRCT0

SRCC0

VDDATI

GND

ATIGT0

ATIGC0

SDATA

^&FSC

9

^&CLKREQA#

^&CLKREQB#

SRCT7

SRCC7

VDDSRC

GND

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

SRCT6

SRCC6

SRCT5

SRCC5

GND

VDDSRC

SRCT4

SRCC4

SRCT3

SRCC3

GND

ATIGT1

ATIGC1

#: Active low

*: Internal pull up resistor 120K to VDD

&: Internal Pull-down resistor 120K to GND

4. BLOCK DIAGRAM

2

ATIGT 0:1

ATIGC 0:1

Divider

ATIGLOOP

USBLOOP

2

CPULOOP

Spread

&

Sync

48MHz

Spectrum

3

XIN

XOUT

XTAL

OSC

REF 0:2

3

CPUT 0:2

CPUC 0:2

3

SRCLOOP

Spread

VCOCLK

Spectrum

6

Divider

Snyc

SRCT 0,3:7

SRCC 0,3:7

M/N/Ratio

ROM

&

6

FS(A:C)

CR#_(A:B)

VTT_PG#

CK410#

Latch

&POR

PCI0

Control

Logic

&Config

Register

CPU_STOP#

PD

475

SDATA

SCLK

I2C

Interface

Publication Release Date: Feb 2006

Revision 0.6

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W83195WG-413/W83195CG-413

STEPLESS FOR ATI P4 CLOCK GENERATOR

5. PIN DESCRIPTION

PIN NAME

TYPE

DESCRIPTION

Crystal output at 14.318MHz nominally with internal loading

capacitors (18pF).

1

XIN

IN

Crystal input with internal loading capacitors (18pF) and feedback

resistors.

2

XOUT

OUT

3

4

5

6

7

8

9

VDD48

USB_48

GND

PWR Power supply for USB_48

OUT 3.3V USB 48Mhz clock output.

PWR Ground pin

VTT_PG#/PD

SCLK

IN

Notifies CK410 to sample latched input or power down mode

Serial clock of I²C 2-wire control interface.

IN

SDATA

^&FSC

I/O Serial data of I²C 2-wire control interface.

IN

FSC CPU frequency select

Dynamic output control

0 = active, 1 = inactive

Dynamic output control

0 = active, 1 = inactive

10 ^&CLKREQA#

11 ^&CLKREQB#

IN

12 SRCT7

13 SRCC7

14 VDDSRC

15 GND

OUT 0.7V current mode differential clock output for SRC

PWR Power supply for SRC

PWR Ground pin

16 SRCT6

17 SRCC6

18 SRCT5

19 SRCC5

20 GND

OUT 0.7V current mode differential clock output for SRC

PWR Ground pin

21 VDDSRC

22 SRCT4

23 SRCC4

24 SRCT3

25 SRCC3

26 GND

PWR Power supply for SRC

OUT 0.7V current mode differential clock output for SRC

PWR Ground pin

27 ATIGT1

28 ATIGC1

OUT 0.7V current mode differential clock output for ATIG

Publication Release Date: Feb 2006

Revision 0.6

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STEPLESS FOR ATI P4 CLOCK GENERATOR

29 ATIGC0

30 ATIGT0

31 GND

OUT 0.7V current mode differential clock output for ATIG

PWR Ground pin

32 VDDATIG

33 SRCC0

34 SRCT0

35 VDDSRC

36 GND

PWR Power supply for ATIG

OUT 0.7V current mode differential clock output for SRC

PWR Power supply for SRC

PWR Ground pin

Deciding the reference current for the differential pairs. The

OUT pin was connected to the precision resistor tied to ground to

decide the appropriate current; 475 ohm is the standard value.

37 IREF

38 GNDA

PWR Ground pin for PLL core.

39 VDDA

PWR 3.3V power supply for PLL core.

40 CPUC2_ITP

41 CPUT2_ITP

42 CPUC1

43 CPUT1

44 GND

OUT 0.7V current mode differential clock output for CPUC2

OUT 0.7V current mode differential clock output for CPUT2

OUT 0.7V current mode differential clock output for CPUC1

OUT 0.7V current mode differential clock output for CPUT1

PWR Ground pin

45 VDDCPU

46 CPUC0

47 CPUT0

48 *CPU_STOP#

49 GND

PWR Power supply for CPU

OUT 0.7V current mode differential clock output for CPUC0

OUT 0.7V current mode differential clock output for CPUT0

IN

PWR Ground pin

FS Table select latch input pin / 3.3V PCI clock output.

Stop selected CPUCLK.

50 ^&CK410#/PCICLK0

I/O

0 = CK410 FS Table, 1 = CK409 FS Table

51 VDDPCI

52 REF2

PWR Power supply for PCI

OUT ꢀ 3.3V REF 14.318Mhz clock output.

I/O FSB CPU frequency select/3.3V REF 14.318Mhz clock output.

I/O FSA CPU frequency select/3.3V REF 14.318Mhz clock output.

PWR Ground pin

53 ^&FSB/REF1

54 ^&FSA/REF0

55 GND

56 VDDREF

PWR Power supply for REF

Publication Release Date: Feb 2006

- 4 -

Revision 0.6

W83195WG-413/W83195CG-413

STEPLESS FOR ATI P4 CLOCK GENERATOR

6. FREQUENCY SELECTION BY HARDWARE OR SOFTWARE

This frequency table is used at power on latched FS [2:0] value or software programming at SSEL

[4:0] (Register 0 bit 7 ~ 3). If FS [2:0] no any external circuit to modify power on status the Gray

shading is Hardware default frequency.

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

CPU (MHZ)

SRC (MHZ)

PCI (MHZ)

FS4

0

1

FS3

0

1

0

1

FS2

0

1

0

1

0

1

0

1

FS1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

FS0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

266.68

133.34

200.01

166.59

333.17

100.00

400.01

200.06

266.68

133.34

200.01

166.59

333.17

100.00

400.01

200.06

100.00

133.34

200.01

166.59

199.90

266.68

400.01

333.30

100.00

133.34

200.01

166.59

199.90

266.68

400.01

333.30

100.00

111.06

100.00

100.03

100.00

111.06

100.00

100.03

100.00

111.06

99.95

33.33

33.32

33.33

33.34

33.33

33.32

33.33

33.34

33.33

33.32

33.33

33.32

33.33

100.00

111.10

100.00

111.06

99.95

100.00

111.10

Publication Release Date: Feb 2006

Revision 0.6

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W83195WG-413/W83195CG-413

STEPLESS FOR ATI P4 CLOCK GENERATOR

7. I²C CONTROL AND STATUS REGISTERS

(The register No. is increased by 1 if use byte data read/write protocol)

7.1 Register 0: ( Default : 00h )

AFFECTED PIN/

FUNCTION NAME(S)

BIT

PWD

AFFECTED PIN / FUNCTION DESCRIPTION

TYPE

7

6

5

4

3

SSEL<4>

0

SSEL<3>

SSEL<2>

Software frequency table selection through I²C

R/W

SSEL<1>

SSEL<0>

Enable software table selection FS[4:0].

0 = Hardware table setting (Jump mode).

1 = Software table setting through Bit7~3 .

(Jumpless mode)

2

1

EN_SSEL

SPSPEN

0

R/W

Enable spread spectrum mode under clock

output.

0 = Spread Spectrum mode disable

1 = Spread Spectrum mode enable

After watchdog timeout

0 = Reload the hardware FS [4:0] latched

pins setting.

0

EN_SAFE_FREQ

0

R/W

1 = Reload the desirable frequency table

selection defined at Reg-5 Bit 4~0.

7.2 Register 1: ( Default : XXh)

AFFECTED PIN/

FUNCTION NAME(S)

BIT

PWD

FUNCTION DESCRIPTION

TYPE

CPUT/C_ITP output control

1: Enable

7

CPUEN<2>

1

R/W

0: Disable

CPUCLKT1/C1 output control

1: Enable

6

CPUEN<1>

R/W

0: Disable

CPUCLKT0/C0 output control

1: Enable

0: Disable

5

4

CPUEN<0>

1

R/W

R

CK410_N_BACK

X

Power on latched value of FS4 pin. Default : 0

Publication Release Date: Feb 2006

Revision 0.6

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W83195WG-413/W83195CG-413

STEPLESS FOR ATI P4 CLOCK GENERATOR

3

2

1

0

Reserved

X

Reserved

R

FS2_BACK

FS1_BACK

FS0_BACK

Power on latched value of FS2 pin. Default : 0

Power on latched value of FS1 pin. Default : 0

Power on latched value of FS0 pin. Default : 0

7.3 Register 2: ( Default : 03h )

AFFECTED PIN/

FUNCTION NAME(S)

BIT

PWD

FUNCTION DESCRIPTION

TYPE

SRCCLK7 is controlled by the CLREQA# pin

1: Controllable

7

CLREQA7#_Ctr

0

R/W

0: Uncontrollable

SRCCLK6 is controlled by the CLREQA# pin

1: Controllable

6

5

4

3

2

CLREQA6#_Ctr

CLREQA5#_Ctr

CLREQA4#_Ctr

CLREQA3#_Ctr

CLREQA0#_Ctr

R/W

0: Uncontrollable

SRCCLK5 is controlled by the CLREQA# pin

1: Controllable

0: Uncontrollable

SRCCLK4 is controlled by the CLREQA# pin

1: Controllable

0: Uncontrollable

SRCCLK3 is controlled by the CLREQA# pin

1: Controllable

0: Uncontrollable

SRCCLK0 is controlled by the CLREQA# pin

1: Controllable

0: Uncontrollable

1

0

Reserved

1

Reserved

R/W

7.4 Register 3: ( Default : 03h )

AFFECTED PIN/

FUNCTION NAME(S)

BIT

PWD

FUNCTION DESCRIPTION

TYPE

SRCCLK7 is controlled by the CLREQB# pin

1: Controllable

7

CLREQB7#_Ctr

0

R/W

0: Uncontrollable

SRCCLK6 is controlled by the CLREQB# pin

1: Controllable

6

CLREQB6#_Ctr

R/W

0: Uncontrollable

Publication Release Date: Feb 2006

Revision 0.6

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W83195WG-413/W83195CG-413

STEPLESS FOR ATI P4 CLOCK GENERATOR

SRCCLK5 is controlled by the CLREQB# pin

5

4

3

2

CLREQB5#_Ctr

CLREQB4#_Ctr

CLREQB3#_Ctr

CLREQB0#_Ctr

0

1: Controllable

R/W

0: Uncontrollable

SRCCLK4 is controlled by the CLREQB# pin

1: Controllable

0: Uncontrollable

SRCCLK3 is controlled by the CLREQB# pin

1: Controllable

0: Uncontrollable

SRCCLK0 is controlled by the CLREQB# pin

1: Controllable

0: Uncontrollable

PCI0 output control

1

0

PCIEN

1

1: Enable

R/W

0: Disable

Reserved

7.5 Register 4: ( Default : FEh)

AFFECTED PIN/

FUNCTION NAME(S)

BIT

PWD

FUNCTION DESCRIPTION

TYPE

CPU_STOP# pin control.

1: Enable CPUCLK2 stop feature

0: Disable stop feature

7

CPU2S_EN

1

R/W

CPU_STOP# pin control.

1: Enable CPUCLK1 stop feature

0: Disable stop feature

6

5

4

3

CPU1S_EN

CPU0S_EN

REFEN<2>

REFEN<1>

R/W

CPU_STOP# pin control.

1: Enable CPUCLK0 stop feature

0: Disable stop feature

PREF2 output control

1: Enable

0: Disable

PREF1 output control

1: Enable

0: Disable

PREF0 output control

1: Enable

2

1

REFEN<0>

F48EN

1

R/W

0: Disable

PUSB48 output control

Publication Release Date: Feb 2006

Revision 0.6

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STEPLESS FOR ATI P4 CLOCK GENERATOR

1: Enable

0: Disable

0

Reserved

0

Reserved

R/W

7.6 Register 5: ( Default : 02h )

AFFECTED PIN/

FUNCTION NAME(S)

BIT

PWD

FUNCTION DESCRIPTION

TYPE

7

Reserved

0

Reserved

R/W

Program this bit =>

1 : Enable Watchdog Timer feature.

0 : Disable Watchdog Timer feature.

Enable WD sequence =>

6

CNT_EN

0

R/W

Program this bit to 1 firstly, then program the

Reg-20 to start the counting

Read-back this bit =>

During timer count down the bit read back to 1.

If count to zero, this bit read back to 0.

Read Back only. Timeout Flag.

0

1 : Watchdog has ever started and count to zero.

0 : a.) Watchdog is restarted and counting.

b.) Power on default state

5

WD_TIMEOUT

R

4

3

2

1

0

SAF_FREQ<4>

SAF_FREQ<3>

SAF_FREQ<2>

SAF_FREQ<1>

SAF_FREQ<0>

0

1

0

These bits will be reloaded in Reg-0 to select

frequency table. As the watchdog is timeout and

EN_SAFE_FREQ=1.

R/W

7.7 Register 6: ( Default : FFh )

AFFECTED PIN/

FUNCTION NAME(S)

BIT

PWD

FUNCTION DESCRIPTION

TYPE

SRC7 output control

1: Enable

R/W

7

SRCEN<7>

1

0: Disable

SRC6 output control

1: Enable

6

5

SRCEN<6>

SRCEN<5>

1

R/W

0: Disable

SRC5 output control

1: Enable

Publication Release Date: Feb 2006

Revision 0.6

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W83195WG-413/W83195CG-413

STEPLESS FOR ATI P4 CLOCK GENERATOR

0: Disable

SRC4 output control

4

3

SRCEN<4>

SRCEN<3>

1

1: Enable

R/W

0: Disable

SRC3 output control

1: Enable

0: Disable

ATIG1 output control

1: Enable

2

ATIGEN<1>

1

R/W

0: Disable

ATI clock can’t be controlled by CLKREQ# pins

ATIG0 output control

1: Enable

1

0

ATIGEN<0>

SRCEN<0>

1

R/W

0: Disable

ATI clock can’t be controlled by CLKREQ# pins

SRC0 output control

1: Enable

0: Disable

7.8 Register 7: Winbond Chip ID – Project Code Register ( Default : 06h )

AFFECTED PIN/

BIT

PWD

FUNCTION DESCRIPTION

TYPE

FUNCTION NAME(S)

CHIP_ID [7]

CHIP_ID [6]

CHIP_ID [5]

CHIP_ID [4]

CHIP_ID [3]

CHIP_ID [2]

CHIP_ID [1]

CHIP_ID [0]

7

6

5

4

3

2

1

0

1

0

Winbond Chip ID.W83195CG/W-413 (BA5A06).

Winbond Chip ID.

R

Winbond Chip ID.

7.9 Register 8: ( Default :D0h )

AFFECTED PIN/

FUNCTION NAME(S)

BIT

7

PWD

FUNCTION DESCRIPTION

TYPE

Programmable N divisor value. Bit 7 ~0 are

defined in the Register 9.

NVAL<8>

1

R/W

Programmable N divisor value. Bit 7 ~0 are

defined in the Register 9.

6

NVAL<9>

R/W

Programmable M divisor

5

4

MVAL<5>

MVAL<4>

0

1

Publication Release Date: Feb 2006

Revision 0.6

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STEPLESS FOR ATI P4 CLOCK GENERATOR

3

2

1

0

MVAL<3>

MVAL<2>

MVAL<1>

MVAL<0>

0

7.10 Register 9: ( Default : 7Ah )

AFFECTED PIN/

FUNCTION NAME(S)

BIT

PWD

FUNCTION DESCRIPTION

TYPE

7

6

5

4

3

2

1

0

NVAL<7>

0

1

0

1

0

NVAL<6>

NVAL<5>

Programmable N divisor bit 7 ~0. The bit 8,9 is

defined in Register 8.

NVAL<4>

R/W

NVAL<3>

Default value follow FS=0

NVAL<2>

NVAL<1>

NVAL<0>

7.11 Register 10: Reserved ( Default : 3Bh )

7.12 Register 11: ( Default : 0Eh )

AFFECTED PIN/

BIT

PWD

FUNCTION DESCRIPTION

TYPE

FUNCTION NAME(S)

SPH VAL<3>

SPH VAL<2>

SPH VAL<1>

SPH VAL<0>

SPL VAL<3>

SPL VAL<2>

SPL VAL<1>

SPL VAL<0>

7

6

5

4

3

2

1

0

1

0

Spread Spectrum Up Counter bit 3 ~ bit 0.

R/W

Spread Spectrum Down Counter bit 3 ~ bit 0

2’s complement representation.

Ex: 1 -> 1111 ; 2 -> 1110 ; 7 -> 1001 ; 8 ->

1000

Publication Release Date: Feb 2006

Revision 0.6

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STEPLESS FOR ATI P4 CLOCK GENERATOR

7.13 Register 12: ( Default : XXh )

AFFECTED PIN/

FUNCTION NAME(S)

BIT

PWD

FUNCTION DESCRIPTION

TYPE

7

6

5

4

3

2

1

0

Reserved

KVAL<9>

KVAL<5>

KVAL<4>

KVAL<3>

KVAL<2>

KVAL<1>

KVAL<0>

0

X

Reserved

R/W

Define the PCI divider ratio

Table-2 integrate the all divider configuration

R/W

Define the SRC divider ratio

Refer to Table-2

Define the CPU divider ratio

R/W

Refer to Table-2

Table-2 CPU, SRC, PCI divider ratio selection Table

LSB

PCI

SRC

Bit3

CPU

Bit5

Bit1,0

MSB

0

1

0

1

00

01

10

11

Bit2/

0

1

Reserved Div20 Reserved

Div24 Div30 Div8

Div6

Div2

Div3

Div8

Div4

Div6

Bit4/

Bit9

Div10

Div8

7.14 Register 13: ( Default : 3Fh )

AFFECTED PIN/

FUNCTION NAME(S)

BIT

PWD

FUNCTION DESCRIPTION

TYPE

0: Output frequency depend on frequency table

1: Program all clock frequency by changing M/N

value

The equation is

VCO =14.318MHz*(N+4)/ M.

7

EN_MN_PROG

0

Once the watchdog timer timeout, the bit will be

clear. Then the frequency will be decided by

hardware default FS<4:0> or desired

frequency select SAF_FREQ[4:0] depend on

EN_SAFE_FREQ (Reg0 – bit0).

6

5

4

Reserved

0

1

Reserved

R/W

Reserved

Publication Release Date: Feb 2006

Revision 0.6

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W83195WG-413/W83195CG-413

STEPLESS FOR ATI P4 CLOCK GENERATOR

3

2

1

0

IVAL<3>

IVAL<2>

IVAL<1>

IVAL<0>

1

R/W

Charge pump current selection

1

7.15 Register 14: ( Default : D0h )

AFFECTED PIN/

FUNCTION NAME(S)

BIT

PWD

FUNCTION DESCRIPTION

TYPE

7

6

5

4

3

2

1

0

Reserved

1

0

1

0

Reserved

R/W

Reserved

SPCNT<5>

SPCNT<4>

SPCNT<3>

SPCNT<2>

SPCNT<1>

SPCNT<0>

Spread Spectrum Programmable time, the

resolution is 280ns. Default period is 11.8us

R/W

7.16 Register 15: ( Default : 5Ch )

AFFECTED PIN/

FUNCTION NAME(S)

BIT

PWD

FUNCTION DESCRIPTION

TYPE

Invert the CPUCLKT2/1/0 phase

0: Default

7

6

INV_CPU

0

1

R/W

1: Inverse

Reserved

CPUT/ SRCT/ ATIG output state in during

POWER DOWN assertion.

1: Driven (2*Iref)

0: Tristate (Floating)

CPUT/ SRCT/ ATIG output state in during STOP

Mode assertion.

5

DRI_CONT

0

R/W

1: Driven (6*Iref)

0: Tristate (Floating)

Complementary parts always tri-state (floating) in

power down or stop mode.

4

3

2

Reserved

1

Reserved

R/W

Reserved

Publication Release Date: Feb 2006

Revision 0.6

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W83195WG-413/W83195CG-413

STEPLESS FOR ATI P4 CLOCK GENERATOR

1

0

Reserved

0

7.17 Register 16: ( Default : 24h )

AFFECTED PIN/

FUNCTION NAME(S)

BIT

PWD

FUNCTION DESCRIPTION

Invert the SRC phase

TYPE

7

INV_SRC

0

0: Default

R/W

1: Inverse

Invert the HTT & PCI phase

0: Default

6

INV_PCI

0

R/W

1: Inverse

5

4

3

2

1

0

CSKEW<2>

CSKEW<1>

CSKEW<0>

PSKEW<2>

PSKEW<1>

PSKEW<0>

1

0

1

0

CPUCLKT1 to CPUCLKT0 skew control

Skew resolution is 300ps

The decision of skew direction is same as

CSKEW<2:0> setting

CPU1 to PCI skew control

Skew resolution is 300ps

R/W

The decision of skew direction is same as

PSKEW<2:0> setting

7.18 Register 17: Reserved ( Default : 0Fh )

7.19 Register 18: Reserved ( Default : 7Ah )

7.20 Register 19: ( Default : 04h )

AFFECTED PIN/

FUNCTION NAME(S)

BIT

PWD

FUNCTION DESCRIPTION

TYPE

7

6

5

4

3

2

1

0

SRC_FS<4>

0

1

0

R/W

SRC frequency table. See Table-3.

SRC_FS<3>

SRC_FS<2>

SRC_FS<4> also is spread spectrum enable

bit.

R/W

SRC_FS<1>

SRC_FS<0>

CPU1 center skew control

Skew resolution is 300ps

CENTERSKEW<2>

CENTERSKEW<1>

The decision of skew direction is same as

CENTERSKEW<2:0> setting

CENTERSKEW<0>

Publication Release Date: Feb 2006

Revision 0.6

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W83195WG-413/W83195CG-413

STEPLESS FOR ATI P4 CLOCK GENERATOR

7.21 Register 20: ( Default : 88h )

AFFECTED PIN/

FUNCTION NAME(S)

BIT

PWD

FUNCTION DESCRIPTION

TYPE

7

6

5

4

3

2

1

0

Reserved

SEC<6>

SEC<5>

SEC<4>

SEC<3>

SEC<2>

SEC<1>

SEC<0>

1

0

1

0

Reserved

R/W

Setting the down count depth (Failure decision).

One bit resolution represent 250ms. Default time

depth is 8*250ms = 2.0 second. If the watchdog

timer is counting, this register will return present

down count value.

R/W

7.22 Register 21: ( Default : ECh )

AFFECTED PIN/

FUNCTION NAME(S)

BIT

PWD

FUNCTION DESCRIPTION

TYPE

7

Reserved

1

Reserved

R/W

CPU align with SRC

1 : Enable

0 : Disable

6

5

CPU2SRC_SYNC

CPU2PCI_SYNC

1

R/W

CPU align with PCI

1 : Enable

0 : Disable

4

3

2

1

0

Reserved

0

1

0

Reserved

R/W

Reserved

SRCSKEW<2>

SRCSKEW<1>

SRCSKEW<0>

CPU1 to SRC skew control

Skew resolution is 300ps

R/W

The decision of skew direction is same as

SRCSKEW<2:0> setting

Publication Release Date: Feb 2006

Revision 0.6

- 15 -

W83195WG-413/W83195CG-413

STEPLESS FOR ATI P4 CLOCK GENERATOR

Table3: SRC & ATIG Frequency Selection Table

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

SRC,ATIG

(MHZ)

SPREAD(%)

FS4

0

1

FS3

0

1

0

1

FS2

0

1

0

1

0

1

0

1

FS1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

FS0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

100.00

101.00

102.00

104.00

100.00

101.00

102.00

104.00

0

-0.5

Publication Release Date: Feb 2006

Revision 0.6

- 16 -

W83195WG-413/W83195CG-413

STEPLESS FOR ATI P4 CLOCK GENERATOR

8. ACCESS INTERFACE

The W83195BR-413 provides I²C Serial Bus for microprocessor to read/write internal registers. In the

W83195BR-413 is provided Block Read/Block Write and Byte-Data Read/Write protocol. The I²C

address is defined at 0xD2.

The register number is increased by one if using byte data read/write protocol.

Example: In block mode, byte number of program register is 1

In byte mode, byte number of program register is 2 (Byte number of block mode +1)

8.1 Block Write protocol

8.2 Block Read protocol

## In block mode, the command code must filled 8’h00

8.3 Byte Write protocol

8.4 Byte Read protocol

Publication Release Date: Feb 2006

- 17 -

Revision 0.6

W83195WG-413/W83195CG-413

STEPLESS FOR ATI P4 CLOCK GENERATOR

9. SPECIFICATIONS

9.1 ABSOLUTE MAXIMUM RATINGS

Stresses greater than those listed in this table may cause permanent damage to the device.

Precautions should be taken to avoid application of any voltage higher than the maximum rated

voltages to this circuit. Subjection to maximum conditions for extended periods may affect reliability.

Unused inputs must always be tied to an appropriate logic voltage level (Ground or VDD).

Parameter

Rating

Absolute 3.3V Core Supply Voltage

Absolute 3.3V I/O Supple Voltage

Operating 3.3V Core Supply Voltage

Operating 3.3V I/O Supple Voltage

Storage Temperature

-0.5V to +4.6V

- 0.5V to + 4.6V

3.135V to 3.465V

- 65°C to + 150°C

- 55°C to + 125°C

0°C to + 70°C

2000V

Ambient Temperature

Operating Temperature

Input ESD protection (Human body model)

9.2 General Operating Characteristics

VDD= 3.3V ± 5 %, TA = 0°C to +70°C,

Parameter

Input Low Voltage

Input High Voltage

Output Low Voltage

Output High Voltage

Symbol

V_IL

Min

2.0

2.4

Max

Units

V_dc

Test Conditions

0.8

V_IH

V_dc

V_OL

0.4

V_dc

V_OH

V_dc

CPU = 100 to 400 MHz

Operating Supply Current

I_dd

350

mA

PCI = 33.3 Mhz with load 10pF

Input pin capacitance

Output pin capacitance

Input pin inductance

Cin

Cout

Lin

5

6

7

pF

nH

9.3 Skew Group timing clock

VDD = 3.3V ± 5 %, TA = 0°C to +70°C, Cl=10pF

Parameter

CPU pair to CPU pair Skew

PCIE pair to PCIE pair Skew

PCI to PCI Skew

Min

Max

100

Units

Test Conditions

ps

Measure Crossing point

Measured at 1.5V

100

250

48MHz to 48MHz Skew

1000

Measured at 1.5V

Publication Release Date: Feb 2006

Revision 0.6

- 18 -

W83195WG-413/W83195CG-413

STEPLESS FOR ATI P4 CLOCK GENERATOR

9.4 CPU 0.7V Electrical Characteristics

VDDC= 3.3V ± 5 %, TA = 0°C to +70°C, Test load Rs=33, Rp=49.9 Cl=2pF, Vol=0.175V,

Voh=0.525V, Vr=475, IREF=2.32mA, Ioh=6*IREF

Parameter

Min

175

250

660

-150

Max

700

550

850

Units

ps

Test Conditions

Rise Time

Fall Time

Measure Single Ended waveform

Measure Differential waveform

ps

Absolute crossing point Voltages

Voltage High

mV

ps

Voltage Low

Cycle to Cycle jitter

Duty Cycle

100

55

45

%

9.5 SRC 0.7V Electrical Characteristics

VDDS= 3.3V ± 5 %, TA = 0°C to +70°C, Test load Rs=33, Rp=49.9 Cl=2pF, Vol=0.175V,

Voh=0.525V, Vr=475, IREF=2.32mA, Ioh=6*IREF

Parameter

Min

175

250

660

-150

Max

700

550

850

Units

ps

Test Conditions

Rise Time

Fall Time

Measure Single Ended waveform

Measure Differential waveform

ps

Absolute crossing point Voltages

Voltage High

mV

ps

Voltage Low

Cycle to Cycle jitter

Duty Cycle

100

55

45

%

9.6 ATIG 0.7V Electrical Characteristics

VDDATIG= 3.3V ± 5 %, TA = 0°C to +70°C, Test load Rs=33, Rp=49.9 Cl=2pF, Vol=0.175V,

Voh=0.525V, Vr=475, IREF=2.32mA, Ioh=6*IREF

Parameter

Min

175

250

660

-150

Max

700

550

850

Units

ps

Test Conditions

Rise Time

Fall Time

Measure Single Ended waveform

Measure Differential waveform

ps

Absolute crossing point Voltages

Voltage High

mV

ps

Voltage Low

Cycle to Cycle jitter

Duty Cycle

100

55

45

%

Publication Release Date: Feb 2006

Revision 0.6

- 19 -

W83195WG-413/W83195CG-413

STEPLESS FOR ATI P4 CLOCK GENERATOR

9.7 PCI Electrical Characteristics

VDDP= 3.3V ± 5 %, TA = 0°C to +70°C, Test load, Cl=10pF,

Parameter

Min

500

Max

2000

250

Units

ps

Test Conditions

Vol=0.4V, Voh=2.4V

Rise Time

Fall Time

ps

Voh=2.4V, Vol=0.4V

Measured at 1.5V

Vout=1.0V

Cycle to Cycle jitter

Duty Cycle

ps

45

55

%

Pull-Up Current Min

Pull-Up Current Max

Pull-Down Current Min

Pull-Down Current Max

-33

mA

-33

38

Vout=3.135V

30

Vout=1.95V

Vout=0.4V

9.8 USB Electrical Characteristics

VDD48= 3.3V ± 5 %, TA = 0°C to +70°C, Test load, Cl=10pF,

Parameter

Min

500

Max

2000

300

Units

ps

Test Conditions

Rise Time

Fall Time

Vol=0.4V, Voh=2.4V

Voh=2.4V, Vol=0.4V

Measured at 1.5V

Vout=1.0V

ps

Long term jitter

ps

Duty Cycle

45

55

%

Pull-Up Current Min

Pull-Up Current Max

Pull-Down Current Min

Pull-Down Current Max

-29

mA

-23

27

Vout=3.135V

29

Vout=1.95V

Vout=0.4V

9.9 REF Electrical Characteristics

VDDR= 3.3V ± 5 %, TA = 0°C to +70°C, Test load, Cl=10pF,

Parameter

Min

500

Max

2000

700

Units

ps

Test Conditions

Rise Time

Fall Time

Vol=0.4V, Voh=2.4V

Voh=2.4V, Vol=0.4V

Measured at 1.5V

Vout=1.0V

ps

Cycle to Cycle jitter

Duty Cycle

ps

45

55

%

Pull-Up Current Min

Pull-Up Current Max

Pull-Down Current Min

Pull-Down Current Max

-33

mA

-33

38

Vout=3.135V

30

Vout=1.95V

Vout=0.4V

Publication Release Date: Feb 2006

Revision 0.6

- 20 -

W83195WG-413/W83195CG-413

STEPLESS FOR ATI P4 CLOCK GENERATOR

10. ORDERING INFORMATION

Part Number

W83195WG-413

W83195CG-413

Package Type

56 PIN TSSOP

56 PIN SSOP

Production Flow

Commercial, 0°C to +70°C

11. HOW TO READ THE TOP MARKING

W83195WG-413

28051234

604LBABA

W83195CG-413

28051234

604GBABA

1st line: Winbond logo and the type number: W83195WG-413/W83195CG-413

2nd line: Tracking code 2 8051234

2: wafers manufactured in Winbond FAB 2

8051234: wafer production series lot number

3rd line: Tracking code 604 L A A BA

604: packages made in '2006, week 04

L: assembly house ID; O means OSE, G means GR , L means Lingsen.

A: Internal use code

A: IC revision

BA: mask version

All the trademarks of products and companies mentioned in this data sheet belong to their

respective owners.

Publication Release Date: Feb 2006

- 21 -

Revision 0.6

W83195WG-413/W83195CG-413

STEPLESS FOR ATI P4 CLOCK GENERATOR

12. PACKAGE DRAWING AND DIMENSIONS

56 PIN TSSOP-240mil

56 PIN SSOP-300mil

.035

.045

DIMENSION IN MM

DIMENSION IN INCH

SYMBOL

.045

.055

MIN. NOM MAX. MIN. NOM MAX.

0.40/0.50 DIA

0.101 0.110

2.41

0.20

2.57 2.79

0.095

0.008

0.088

A

A1

A2

b

END VIEW

0.30

0.41

2.34

0.016

0.092

0.0135

0.010

0.012

0.090

0.010

E

HE

2.24

0.20

0.13

2.29

0.25

0.34 0.008

0.25

0.005

c

TOP VIEW

18.2

9

18.54

18.42

0.720 0.725 0.730

0.400 0.406 0.410

0.292 0.296 0.299

0.020 0.025 0.030

SEE DETAIL "A"

D

H_E

c

10.16 10.31 10.41

D

E

e

7.52

0.64

7.59

0.76

7.42

0.51

θ

A2

A

0.61

0

0.81

1.40

0.024 0.032

0.040

1.02

L

L1

Y

0.055

A1

SEATING PLANE

e

PARTING LINE

0.003

Y

0.08

8

b

SIDE VIEW

c

0

θ

8

θ

L

L1

DETAIL"A"

Publication Release Date: Feb 2006

Revision 0.6

- 22 -

W83195WG-413/W83195CG-413

STEPLESS FOR ATI P4 CLOCK GENERATOR

Important Notice

Winbond products are not designed, intended, authorized or warranted for use as components

in systems or equipment intended for surgical implantation, atomic energy control

instruments, airplane or spaceship instruments, transportation instruments, traffic signal

instruments, combustion control instruments, or for other applications intended to support or

sustain life. Further more, Winbond products are not intended for applications wherein failure

of Winbond products could result or lead to a situation wherein personal injury, death or

severe property or environmental damage could occur.

Winbond customers using or selling these products for use in such applications do so at their

own risk and agree to fully indemnify Winbond for any damages resulting from such improper

use or sales.

Headquarters

Winbond Electronics Corporation America Winbond Electronics (Shanghai) Ltd

27F, 2299 Yan An W. Rd. Shanghai,

No. 4, Creation Rd. III,

Science-Based Industrial Park,

Hsinchu, Taiwan

TEL: 886-3-5770066

FAX: 886-3-5665577

2727 North First Street, San Jose,

200336 China

CA 95134, U.S.A.

TEL: 1-408-9436666

FAX: 1-408-5441798

TEL: 86-21-62365999

FAX: 86-21-62365998

http://www.winbond.com.tw/

Taipei Office

Winbond Electronics Corporation Japan Winbond Electronics (H.K.) Ltd.

9F, No.480, Rueiguang Rd.,

Neihu District, Taipei, 114,

Taiwan, R.O.C.

TEL: 886-2-8177-7168

FAX: 886-2-8751-3579

7F Daini-ueno BLDG, 3-7-18

Shinyokohama Kohoku-ku,

Yokohama, 222-0033

Unit 9-15, 22F, Millennium City,

No. 378 Kwun Tong Rd.,

Kowloon, Hong Kong

TEL: 852-27513100

TEL: 81-45-4781881

FAX: 81-45-4781800

FAX: 852-27552064

Please note that all data and specifications are subject to change without notice.

All the trade marks of products and companies mentioned in this data sheet belong to their respective owners.

Publication Release Date: Feb 2006

Revision 0.6

- 23 -

型号:	W83195CG-413
是否Rohs认证：	符合
生命周期：	Transferred
IHS 制造商：	WINBOND ELECTRONICS CORP
零件包装代码：	SSOP
包装说明：	0.300 INCH, SSOP-56
针数：	56
Reach Compliance Code：	unknown
ECCN代码：	EAR99
HTS代码：	8542.39.00.01
风险等级：	5.47
JESD-30 代码：	R-PDSO-G56
JESD-609代码：	e3
长度：	18.42 mm
端子数量：	56
最高工作温度：	70 °C
最低工作温度：
最大输出时钟频率：	400.01 MHz
封装主体材料：	PLASTIC/EPOXY
封装代码：	SSOP
封装等效代码：	SSOP56,.4
封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, SHRINK PITCH
电源：	3.3 V
主时钟/晶体标称频率：	14.318 MHz
认证状态：	Not Qualified
座面最大高度：	2.79 mm
子类别：	Clock Generators
最大压摆率：	350 mA
最大供电电压：	3.465 V
最小供电电压：	3.135 V
标称供电电压：	3.3 V
表面贴装：	YES
技术：	CMOS
温度等级：	COMMERCIAL
端子面层：	MATTE TIN
端子形式：	GULL WING
端子节距：	0.635 mm
端子位置：	DUAL
宽度：	7.52 mm
uPs/uCs/外围集成电路类型：	CLOCK GENERATOR, PROCESSOR SPECIFIC
Base Number Matches：	1

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