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W9816G6IH

512K × 2 BANKS × 16 BITS SDRAM

Table of Contents-

1.

2.

3.

4.

5.

6.

7.

GENERAL DESCRIPTION ......................................................................................................... 3

FEATURES................................................................................................................................. 3

AVAILABLE PART NUMBER ..................................................................................................... 3

PIN CONFIGURATION............................................................................................................... 4

PIN DESCRIPTION..................................................................................................................... 5

BLOCK DIAGRAM ...................................................................................................................... 6

FUNCTIONAL DESCRIPTION ................................................................................................... 7

7.1

7.2

7.3

7.4

7.5

7.6

7.7

7.8

7.9

Power Up and Initialization ............................................................................................. 7

Programming Mode Register.......................................................................................... 7

Bank Activate Command ................................................................................................ 7

Read and Write Access Modes ...................................................................................... 7

Burst Read Command .................................................................................................... 8

Burst Write Command .................................................................................................... 8

Read Interrupted by a Read ........................................................................................... 8

Read Interrupted by a Write............................................................................................ 8

Write Interrupted by a Write............................................................................................ 8

7.10 Write Interrupted by a Read............................................................................................ 8

7.11 Burst Stop Command ..................................................................................................... 9

7.12 Addressing Sequence of Sequential Mode .................................................................... 9

7.13 Addressing Sequence of Interleave Mode ..................................................................... 9

7.14 Auto-precharge Command ........................................................................................... 10

7.15 Precharge Command.................................................................................................... 10

7.16 Self Refresh Command ................................................................................................ 10

7.17 Power Down Mode ....................................................................................................... 11

7.18 No Operation Command............................................................................................... 11

7.19 Deselect Command ...................................................................................................... 11

7.20 Clock Suspend Mode.................................................................................................... 11

OPERATION MODE ................................................................................................................. 12

ELECTRICAL CHARACTERISTICS......................................................................................... 13

8.

9.

9.1

9.2

9.3

Absolute Maximum Ratings.......................................................................................... 13

Recommended DC Operating Conditions.................................................................... 13

Capacitance.................................................................................................................. 13

Publication Release Date:May 05, 2008

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Revision A01

W9816G6IH

9.4

9.5

DC Characteristics........................................................................................................ 14

AC Characteristics........................................................................................................ 15

10.

11.

TIMING WAVEFORMS............................................................................................................. 17

10.1 Command Input Timing ................................................................................................ 17

10.2 Read Timing.................................................................................................................. 18

10.3 Control Timing of Input/Output Data............................................................................. 19

10.4 Mode Register Set Cycle.............................................................................................. 20

OPERATING TIMING EXAMPLE ............................................................................................. 21

11.1 Interleaved Bank Read (Burst Length = 4, CAS Latency = 3)...................................... 21

11.2 Interleaved Bank Read (Burst Length = 4, CAS Latency = 3, Auto-precharge)........... 22

11.3 Interleaved Bank Read (Burst Length = 8, CAS Latency = 3)...................................... 23

11.4 Interleaved Bank Read (Burst Length = 8, CAS Latency = 3, Auto-precharge)........... 24

11.5 Interleaved Bank Write (Burst Length = 8) ................................................................... 25

11.6 Interleaved Bank Write (Burst Length = 8, Auto-precharge) ........................................ 26

11.7 Page Mode Read (Burst Length = 4, CAS Latency = 3) .............................................. 27

11.8 Page Mode Read / Write (Burst Length = 8, CAS Latency = 3)................................... 28

11.9 Auto Precharge Read (Burst Length = 4, CAS Latency = 3)........................................ 29

11.10 Auto Precharge Write (Burst Length = 4).................................................................... 30

11.11 Auto Refresh Cycle ..................................................................................................... 31

11.12 Self Refresh Cycle....................................................................................................... 32

11.13 Burst Read and Single Write (Burst Length = 4, CAS Latency = 3) ........................... 33

11.14 Power Down Mode...................................................................................................... 34

11.15 Auto-precharge Timing (Read Cycle) ......................................................................... 35

11.16 Auto-precharge Timing (Write Cycle).......................................................................... 36

11.17 Timing Chart of Read to Write Cycle........................................................................... 37

11.18 Timing Chart of Write to Read Cycle........................................................................... 37

11.19 Timing Chart of Burst Stop Cycle (Burst Stop Command).......................................... 38

11.20 Timing Chart of Burst Stop Cycle (Precharge Command).......................................... 38

11.21 CKE/DQM Input Timing (Write Cycle)......................................................................... 39

11.22 CKE/DQM Input Timing (Read Cycle)......................................................................... 40

PACKAGE SPECIFICATION.................................................................................................... 41

12.1 50L-TSOP (II) 400 mill.................................................................................................. 41

REVISION HISTORY................................................................................................................ 42

12.

13.

Publication Release Date:May 05, 2008

- 2 -

Revision A01

W9816G6IH

1. GENERAL DESCRIPTION

W9816G6IH is a high-speed synchronous dynamic random access memory (SDRAM), organized as

512K words × 2 banks × 16 bits. W9816G6IH delivers a data bandwidth of up to 200M words per

second (-5). For different applications the W9816G6IH is sorted into the following speed grades: -5/-

6/-7/-6I and -7I. The -5 parts can run up to 200MHz/CL3 or 143MHz/CL2. The -6/-6I parts can run up

to 166MHz/CL3 (the -6I grade which is guaranteed to support -40°C ~ 85°C). The -7/-7I parts can run

up to 143MHz/CL3 (the -7I grade which is guaranteed to support -40°C ~ 85°C).

Accesses to the SDRAM are burst oriented. Consecutive memory location in one page can be

accessed at a burst length of 1, 2, 4, 8 or full page when a bank and row is selected by an ACTIVE

command. Column addresses are automatically generated by the SDRAM internal counter in burst

operation. Random column read is also possible by providing its address at each clock cycle. The

multiple bank nature enables interleaving among internal banks to hide the precharging time.

By having a programmable Mode Register, the system can change burst length, latency cycle,

interleave or sequential burst to maximize its performance. W9816G6IH is ideal for main memory in

high performance applications.

2. FEATURES

•

2.7V~3.6V power supply for -7/-7I speed grades

3.3V ± 0.3V power supply for -5/-6/-6I speed grades

524,288 words x 2 banks x 16 bits organization

Self Refresh current: standard and low power

CAS Latency: 2 and 3

Burst Length: 1, 2, 4, 8 and Full Page

Burst Read, Single Writes Mode

Byte Data Controlled by LDQM, UDQM

Auto-precharge and Controlled Precharge

4K Refresh Cycles/64 mS

Interface: LVTTL

Packaged in 50-pin, 400 mil TSOP II, using Lead free materials with RoHS compliant

3. AVAILABLE PART NUMBER

SELF REFRESH CURRENT

(MAX.)

OPERATING

PART NUMBER

SPEED GRADE

TEMPERATURE

200MHz/CL3 or

143MHz/CL2

166MHz/CL3

143MHz/CL3

166MHz/CL3

143MHz/CL3

0°C ~ 70°C

W9816G6IH-5

2mA

0°C ~ 70°C

-40°C ~ 85°C

W9816G6IH-6

W9816G6IH-7

W9816G6IH-6I

W9816G6IH-7I

2mA

Publication Release Date:May 05, 2008

Revision A01

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W9816G6IH

4. PIN CONFIGURATION

V

1

2

3

50

49

48

47

46

45

44

43

42

41

40

39

V

SS

CC

DQ0

DQ1

DQ15

DQ14

V

Q

V

SS

Q

4

SS

DQ2

DQ3

5

DQ13

DQ12

6

V Q

CC

V

Q

CC

7

8

DQ4

DQ5

DQ11

DQ10

9

V

Q

SS

10

11

12

V

SS

Q

DQ6

DQ7

DQ9

DQ8

V

Q

CC

V

Q

13

14

CC

38

37

36

35

34

LDQM

WE

NC

UDQM

CLK

CKE

NC

15

16

CAS

RAS

17

18

19

20

21

22

23

33

32

31

30

29

CS

BA

A9

A10

A0

A8

A7

A1

A6

A5

A4

A2

A3

28

27

26

24

25

V

CC

V

SS

Publication Release Date:May 05, 2008

Revision A01

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W9816G6IH

5. PIN DESCRIPTION

PIN NUMBER PIN NAME

FUNCTION

DESCRIPTION

20−24,

A0−A10

27−32

Multiplexed pins for row and column address.

Row address: A0−A10. Column address: A0−A7.

Address

Select bank to activate during row address latch time,

19

BA

Bank Select or bank to read/write during column address latch

time.

2, 3, 5, 6, 8, 9,

11, 12, 39, 40,

42, 43, 45, 46,

48, 49

Data

Multiplexed pins for data input and output.

Input/ Output

DQ0−DQ15

Disable or enable the command decoder. When

Chip Select command decoder is disabled, new command is

ignored and previous operation continues.

18

17

CS

Command input. When sampled at the rising edge of

Row Address

RAS

the clock, RAS, CAS and WE define the operation

Strobe

to be executed.

Column

16

15

CAS

WE

Referred to RAS

Address Strobe

Write Enable

Referred to RAS

The output buffer is placed at Hi-Z (with latency of 2)

UDQM/

LDQM

Input/Output when DQM is sampled high in read cycle. In write

36, 14

Mask

cycle, sampling DQM high will block the write

operation with zero latency.

System clock used to sample inputs on the rising

edge of clock.

35

34

CLK

CKE

Clock Inputs

CKE controls the clock activation and deactivation.

Clock Enable When CKE is low, Power Down mode, Suspend

mode, or Self Refresh mode is entered.

1, 25

VCC

VSS

Power (+3.3V) Power for input buffers and logic circuit inside DRAM.

Ground for input buffers and logic circuit inside

26, 50

Ground

DRAM.

Power (+3.3V) Separated power from VCC, used for output buffers to

for I/O buffer improve noise immunity.

7, 13, 38, 44,

4, 10, 41, 47

33, 37

VCCQ

VSSQ

NC

Ground for I/O Separated ground from VSS, used for output buffers

buffer

to improve noise immunity.

No connection. (NC pin should be connected to GND

or floating)

No Connection

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W9816G6IH

6. BLOCK DIAGRAM

CLK

CLOCK

BUFFER

CKE

CS

RAS

CAS

WE

CONTROL

SIGNAL

GENERATOR

COLUMN DECODER

R

O

COMMAND

DECODER

W

CELL ARRAY

BANK #0

D

E

C

O

D

E

R

SENSE AMPLIFIER

A10

A0

MODE

REGISTER

ADDRESS

BUFFER

A9

BA

DQ0

DQ

BUFFER

DATA CONTROL

CIRCUIT

DQ15

LDQM

UDQM

REFRESH

COUNTER

COLUMN

COUNTER

COLUMN DECODER

R

O

W

CELL ARRAY

BANK #1

D

E

C

O

D

E

R

SENSE AMPLIFIER

Note: The cell array configuration is 2048 * 256 * 16

Publication Release Date:May 05, 2008

Revision A01

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W9816G6IH

7. FUNCTIONAL DESCRIPTION

7.1 Power Up and Initialization

The default power up state of the mode register is unspecified. The following power up and

initialization sequence need to be followed to guarantee the device being preconditioned to each user

specific needs during power up, all VCC and VCCQ pins must be ramp up simultaneously to the

specified voltage when the input signals are held in the "NOP" state. The power up voltage must not

exceed VCC + 0.3V on any of the input pins or VCC supplies. After power up, an initial pause of 200 µS

is required followed by a precharge of all banks using the precharge command. To prevent data

contention on the DQ bus during power up, it is required that the DQM and CKE pins be held high

during the initial pause period. Once all banks have been precharged, the Mode Register Set

Command must be issued to initialize the Mode Register. An additional eight Auto Refresh cycles

(CBR) are also required before or after programming the Mode Register to ensure proper subsequent

operation.

7.2 Programming Mode Register

After initial power up, the Mode Register Set Command must be issued for proper device operation.

All banks must be in a precharged state and CKE must be high at least one cycle before the Mode

Register Set Command can be issued. The Mode Register Set Command is activated by the low

signals of RAS, CAS , CS and WE at the positive edge of the clock. The address input data

during this cycle defines the parameters to be set as shown in the Mode Register Operation table. A

new command may be issued following the mode register set command once a delay equal to t_RSC

has elapsed. Please refer to the next page for Mode Register Set Cycle and Operation Table.

7.3 Bank Activate Command

The Bank Activate command must be applied before any Read or Write operation can be executed.

The operation is similar to RAS activate in EDO DRAM. The delay from when the Bank Activate

command is applied to when the first read or write operation can begin must not be less than the RAS

to CAS delay time (t_RCD). Once a bank has been activated it must be precharged before another Bank

Activate command can be issued to the same bank. The minimum time interval between successive

Bank Activate commands to the same bank is determined by the RAS cycle time of the device (t_RC).

The minimum time interval between interleaved Bank Activate commands (Bank A to Bank B and vice

versa) is the Bank-to-Bank delay time (t_RRD). The maximum time that each bank can be held active is

specified as t_RAS(max.).

7.4 Read and Write Access Modes

After a bank has been activated, a read or write cycle can be followed. This is accomplished by setting

RAS high and CAS low at the clock rising edge after minimum of t_RCDdelay. WE pin voltage level

defines whether the access cycle is a read operation ( WE high), or a write operation ( WE low). The

address inputs determine the starting column address. Reading or writing to a different row within an

activated bank requires the bank be precharged and a new Bank Activate command be issued. When

more than one bank is activated, interleaved bank Read or Write operations are possible. By using the

programmed burst length and alternating the access and precharge operations between multiple

banks, seamless data access operation among many different pages can be realized. Read or Write

Commands can also be issued to the same bank or between active banks on every clock cycle.

Publication Release Date:May 05, 2008

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Revision A01

W9816G6IH

7.5 Burst Read Command

The Burst Read command is initiated by applying logic low level to CS and CAS while holding

RAS and WE high at the rising edge of the clock. The address inputs determine the starting column

address for the burst. The Mode Register sets type of burst (sequential or interleave) and the burst

length (1, 2, 4, 8 and full page) during the Mode Register Set Up cycle. Table 2 and 3 in the next page

explain the address sequence of interleave mode and sequence mode.

7.6 Burst Write Command

The Burst Write command is initiated by applying logic low level to CS , CAS and WE while

holding RAS high at the rising edge of the clock. The address inputs determine the starting column

address. Data for the first burst write cycle must be applied on the DQ pins on the same clock cycle

that the Write Command is issued. The remaining data inputs must be supplied on each subsequent

rising clock edge until the burst length is completed. Data supplied to the DQ pins after burst finishes

will be ignored.

7.7 Read Interrupted by a Read

A Burst Read may be interrupted by another Read Command. When the previous burst is interrupted,

the remaining addresses are overridden by the new read address with the full burst length. The data

from the first Read Command continues to appear on the outputs until the CAS Latency from the

interrupting Read Command the is satisfied.

7.8 Read Interrupted by a Write

To interrupt a burst read with a Write Command, DQM may be needed to place the DQs (output

drivers) in a high impedance state to avoid data contention on the DQ bus. If a Read Command will

issue data on the first and second clocks cycles of the write operation, DQM is needed to insure the

DQs are tri-stated. After that point the Write Command will have control of the DQ bus and DQM

masking is no longer needed.

7.9 Write Interrupted by a Write

A burst write may be interrupted before completion of the burst by another Write Command. When the

previous burst is interrupted, the remaining addresses are overridden by the new address and data

will be written into the device until the programmed burst length is satisfied.

7.10 Write Interrupted by a Read

A Read Command will interrupt a burst write operation on the same clock cycle that the Read

Command is activated. The DQs must be in the high impedance state at least one cycle before the

new read data appears on the outputs to avoid data contention. When the Read Command is

activated, any residual data from the burst write cycle will be ignored.

Publication Release Date:May 05, 2008

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Revision A01

W9816G6IH

7.11 Burst Stop Command

A Burst Stop Command may be used to terminate the existing burst operation but leave the bank

open for future Read or Write Commands to the same page of the active bank, if the burst length is full

page. Use of the Burst Stop Command during other burst length operations is illegal. The Burst Stop

Command is defined by having RAS and CAS high with CS and WE low at the rising edge of

the clock. The data DQs go to a high impedance state after a delay, which is equal to the CAS

Latency in a burst read cycle, interrupted by Burst Stop. If a Burst Stop Command is issued during a

full page burst write operation, then any residual data from the burst write cycle will be ignored.

7.12 Addressing Sequence of Sequential Mode

A column access is performed by increasing the address from the column address, which is input to

the device. The disturb address is varied by the Burst Length as shown in Table 2.

Table 2 Address Sequence of Sequential Mode

DATA

Data 0

Data 1

Data 2

Data 3

Data 4

Data 5

Data 6

Data 7

ACCESS ADDRESS

BURST LENGTH

n

BL = 2 (disturb address is A0)

No address carry from A0 to A1

BL = 4 (disturb addresses are A0 and A1)

No address carry from A1 to A2

n + 1

n + 2

n + 3

n + 4

n + 5

n + 6

n + 7

BL = 8 (disturb addresses are A0, A1 and A2)

No address carry from A2 to A3

7.13 Addressing Sequence of Interleave Mode

A column access is started in the input column address and is performed by inverting the address bit

in the sequence shown in Table 3.

Table 3 Address Sequence of Interleave Mode

DATA

ACCESS ADDRESS

BURST LENGTH

Data 0

A8 A7 A6 A5 A4 A3 A2 A1 A0

BL = 2

Data 1

Data 2

Data 3

Data 4

Data 5

Data 6

Data 7

A8 A7 A6 A5 A4 A3 A2 A1 A0

BL = 4

BL = 8

Publication Release Date:May 05, 2008

Revision A01

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W9816G6IH

7.14 Auto-precharge Command

If A10 is set to high when the Read or Write Command is issued, then the Auto-precharge function is

entered. During Auto-precharge, a Read Command will execute as normal with the exception that the

active bank will begin to precharge automatically before all burst read cycles have been completed.

Regardless of burst length, it will begin a certain number of clocks prior to the end of the scheduled

burst cycle. The number of clocks is determined by CAS Latency.

A Read or Write Command with Auto-precharge can not be interrupted before the entire burst

operation is completed. Therefore, use of a Read, Write, or Precharge Command is prohibited during

a read or write cycle with Auto-precharge. Once the precharge operation has started, the bank cannot

be reactivated until the Precharge time (t_RP) has been satisfied. Issue of Auto-precharge command is

illegal if the burst is set to full page length. If A10 is high when a Write Command is issued, the Write

with Auto-precharge function is initiated. The SDRAM automatically enters the precharge operation

two clock delay from the last burst write cycle. This delay is referred to as Write t_WR. The bank

undergoing Auto-precharge can not be reactivated until t_WRand t_RPare satisfied. This is referred to as

t_DAL, Data-in to Active delay (t_DAL= t_WR+ t_RP). When using the Auto-precharge Command, the interval

between the Bank Activate Command and the beginning of the internal precharge operation must

satisfy t_RAS(min).

7.15 Precharge Command

The Precharge Command is used to precharge or close a bank that has been activated. The

Precharge Command is entered when CS, RAS and WE are low and CAS is high at the rising

edge of the clock. The Precharge Command can be used to precharge each bank separately or all

banks simultaneously. The address bits, A10, and BA, are used to define which bank(s) is to be

precharged when the command is issued. After the Precharge Command is issued, the precharged

bank must be reactivated before a new read or write access can be executed. The delay between the

Precharge Command and the Activate Command must be greater than or equal to the Precharge time

(t_RP).

7.16 Self Refresh Command

The Self-Refresh Command is defined by having CS, RAS, CAS and CKE held low with WE

high at the rising edge of the clock. All banks must be idle prior to issuing the Self-Refresh Command.

Once the command is registered, CKE must be held low to keep the device in Self-Refresh mode.

When the SDRAM has entered Self Refresh mode all of the external control signals, except CKE, are

disabled. The clock is internally disabled during Self-Refresh Operation to save power. The device will

exit Self-Refresh operation after CKE is returned high. Any subsequent commands can be issued

after t_RCfrom the end of Self Refresh command.

If, during normal operation, Auto-Refresh cycles are issued in bursts (as opposed to being evenly

distributed), a burst of 4,096 Auto-Refresh cycles should be completed just prior to entering and just

after exiting the Self-Refresh mode.

Publication Release Date:May 05, 2008

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Revision A01

W9816G6IH

7.17 Power Down Mode

The Power Down mode is initiated by holding CKE low. All of the receiver circuits except CKE are

gated off to reduce the power. The Power Down mode does not perform any refresh operations;

therefore the device can not remain in Power Down mode longer than the Refresh period (t_REF) of the

device.

The Power Down mode is exited by bringing CKE high. When CKE goes high, a No Operation

Command is required on the next rising clock edge, depending on t_CK. The input buffers need to be

enabled with CKE held high for a period equal to t_CKS(min) + t_CK(min).

7.18 No Operation Command

The No Operation Command should be used in cases when the SDRAM is in an idle or a wait state to

prevent the SDRAM from registering any unwanted commands between operations. A No Operation

Command is registered when CS is low with RAS, CAS and WE held high at the rising edge of

the clock. A No Operation Command will not terminate a previous operation that is still executing,

such as a burst read or write cycle.

7.19 Deselect Command

The Deselect Command performs the same function as a No Operation Command. Deselect

Command occurs when CS is brought high, the RAS, CAS and WE signals become don't cares.

7.20 Clock Suspend Mode

During normal access mode, CKE must be held high enabling the clock. When CKE is registered low

while at least one of the banks is active, Clock Suspend Mode is entered. The Clock Suspend mode

deactivates the internal clock and suspends any clocked operation that was currently being executed.

There is a one-clock delay between the registration of CKE low and the time at which the SDRAM

operation suspends. While in Clock Suspend mode, the SDRAM ignores any new commands that are

issued. The Clock Suspend mode is exited by bringing CKE high. There is a one-clock cycle delay

from when CKE returns high to when Clock Suspend mode is exited.

Publication Release Date:May 05, 2008

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W9816G6IH

8. OPERATION MODE

Fully synchronous operations are performed to latch the commands at the positive edges of CLK.

Table 1 shows the truth table for the operation commands.

TABLE 1 TRUTH TABLE (NOTE 1, 2)

DEVICE

COMMAND

Bank Active

Bank Precharge

Precharge All

CKEn-1 CKEn DQM BA

A10 A9-A0

RAS CAS

WE

CS

STATE

Idle

Any

H

X

H

L

X

V

X

V

X

V

L

V

X

V

X

L

H

L

H

L

H

L

H

L

H

L

H

L

X

H

Any

H

L

H

L

H

V

X

Write

Active ⁽³⁾

Idle

Write with Auto-precharge

Read

Read with Auto-precharge

Mode Register Set

No-Operation

Burst Stop

Device Deselect

Auto-Refresh

L

Any

H

X

L

H

X

L

Active ⁽⁴⁾

Any

Idle

Self-Refresh Entry

L

Idle

L

H

X

H

L

X

H

X

H

X

Self-Refresh Exit

(S.R)

Clock Suspend Mode

Entry

Active

H

L

X

Idle

H

L

H

X

H

L

X

H

L

X

H

X

H

X

Power Down Mode Entry

Clock Suspend Mode Exit

Active ⁽⁵⁾

Active

X

H

X

H

X

Any

L

H

X

Power Down Mode Exit

(power down)

Data Write/Output Enable

Data Write/Output Disable

Active

H

X

L

H

X

Notes：(1) V = Valid, X = Don't care, L = Low Level, H = High Level

(2) CKEn signal is input level when commands are provided.

CKEn-1 signal is the input level one clock cycle before the command is issued.

(3) These are state of bank designated by BA signals.

(4) Device state is full page burst operation.

(5) Power Down Mode can not be entered in the burst cycle.

When this command asserts in the burst cycle, device state is clock suspend mode.

Publication Release Date:May 05, 2008

Revision A01

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W9816G6IH

9. ELECTRICAL CHARACTERISTICS

9.1 Absolute Maximum Ratings

PARAMETER

Input, Output Voltage

Power Supply Voltage

SYMBOL

VIN, VOUT

VCC, VCCQ

TOPR

RATING

-1 ~ VCC + 0.3

-1~ 4.6

0 ~ 70

UNIT

V

°C

W

NOTES

1

Operating Temperature for -5/-6/-7

Operating Temperature for -6I/-7I

Storage Temperature

TOPR

-40 ~ 85

-55 ~ 150

260

TSTG

Soldering Temperature (10s)

Power Dissipation

Short Circuit Output Current

TSOLDER

PD

1

50

IOUT

mA

Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability

of the device.

9.2 Recommended DC Operating Conditions

(TA = 0 to 70°C for -5/–6/-7 , TA= -40 to 85°C for -6I/-7I)

PARAMETER

SYM. MIN.

TYP.

MAX.

UNIT

NOTES

Power Supply Voltage for -5/-6/-6I

Power Supply Voltage for -7/-7I

VCC

3.0

2.7

3.3

3.6

V

2

Power Supply Voltage for -5/-6/-6I (for I/O Buffer) VCCQ

3.0

3.3

3.6

V

2

Power Supply Voltage for -7/-7I (for I/O Buffer)

Input High Voltage

VCCQ

VIH

2.7

2.0

3.3

3.6

VCC + 0.3

0.8

V

2

-

Input Low Voltage

VIL

-0.3

Note: VIH (max.) = VCC/VCCQ +1.5V for pulse width < 5 nS

VIL (min.) = VSS/VSSQ -1.5V for pulse width < 5 nS

9.3 Capacitance

(VCC = 3.3V, TA = 25 °C, f = 1MHz)

PARAMETER

SYM.

MIN.

MAX.

UNIT

Input Capacitance (A0 to A10, BA, CS, RAS, CAS , WE ,

UDQM, LDQM, CKE)

CI

-

4

pf

Input Capacitance (CLK)

-

4

pf

Input/Output capacitance (DQ0 to DQ15)

Note: These parameters are periodically sampled and not 100% tested

CIO

5.5

Publication Release Date:May 05, 2008

Revision A01

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W9816G6IH

9.4 DC Characteristics

(VCC = 3.3V ±0.3V for -5/-6/-6I, VCC = 2.7V to 3.6V for -7/-7I, TA = 0 to 70°C for -5/–6/-7, TA= -40 to 85°C for -6I/-7I)

-5

-6/-6I

MAX.

-7/-7I

MAX.

PARAMETER

SYM.

UNIT NOTES

MAX.

Operating Current

t

_CK= min., t_RC= min.

1 Bank Operation

CKE = VIH

I_CC1

80

60

50

3

Active precharge command

cycling without burst operation

Standby Current

I_CC2

I_CC2P

I_CC2S

I_CC2PS

I_CC3

30

2

30

2

25

2

3

tCK = min., CS = VIH

VIH /L = VIH (min.) / VIL (max.)

CKE = VIL

(Power Down mode)

CKE = VIH

Bank: inactive state

Standby Current

10

2

10

2

10

2

CLK = VIL, CS = VIH

VIH/L = VIH (min.) / VIL (max.)

CKE = VIL

(Power Down mode)

mA

Bank: inactive state

No Operating Current

CKE = VIH

45

10

40

10

35

10

t

_CK= min., CS = VIH (min.)

CKE = VIL

(Power Down mode)

I_CC3P

Bank: active state (2 Banks)

Burst Operating Current

(t_CK= min.)

Read/ Write command cycling

Auto Refresh Current

(t_CK= min.)

I_CC4

I_CC5

I_CC6

120

60

2

110

55

2

100

50

2

3, 4

3

Auto refresh command cycling

Self Refresh Current

(CKE = 0.2V)

mA

Self refresh mode

PARAMETER

SYM.

MIN.

MAX.

UNIT

NOTES

Input Leakage Current

(0V ≤ VIN ≤ VCC, all other pins not under test = 0V)

I_I(L)

-5

5

µA

Output Leakage Current

I_O(L)

V_OH

V_OL

-5

2.4

-

5

-

µA

V

(Output disable , 0V ≤ VOUT ≤ VCCQ )

″

LVTTL Output H Level Voltage

(I_OUT= -2 mA)

″

LVTTL Output L Level Voltage

(I_OUT= 2 mA)

0.4

V

Publication Release Date:May 05, 2008

Revision A01

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W9816G6IH

9.5 AC Characteristics

(VCC = 3.3V ±0.3V for -5/-6/-6I, VCC = 2.7V to 3.6V for -7/-7I, TA = 0 to 70°C for -5/–6/-7, TA= -40 to 85°C for -6I/-7I)

-5

-6/-6I

MAX.

-7/-7I

MAX.

PARAMETER

SYM.

UNIT NOTES

MIN.

MAX.

MIN.

Ref/Active to Ref/Active Command Period t_RC

55

60

65

Active to Precharge Command Period

t_RAS

40 100000 42

100000 45 100000

nS

Active to Read/Write Command Delay

Time

t_RCD

15

1

18

1

20

Read/Write(a) to Read/Write(b)Command

Period

t_CCD

1

t_CK

nS

Precharge to Active(b) Command Period

Active(a) to Active(b) Command Period

t_RP

15

10

2

18

12

2

18

14

2

t_RRD

CL* = 2

Write Recovery Time

t_WR

t_CK

CL* = 3

2

CL* = 2

7

1000

8

1000

10

7

1000

CLK Cycle Time

CL* = 3

t_CK

5

6

CLK High Level Width

CLK Low Level Width

t_CH

t_CL

2

8

9

7

2

CL* = 2

Access Time from CLK

CL* = 3

5.5

5

5.5

5

t_AC

4.5

5

Output Data Hold Time

Output Data High Impedance Time

Output Data Low Impedance Time

Power Down Mode Entry Time

Data-in-Set-up Time

t_OH

t_HZ

2

2.5

0

2

6

7

t_LZ

0

9

nS

t_SB

0

5

0

t_DS

1.5

0.7

1.5

0.7

1.5

0.7

1.5

0.7

1.5

0.7

1.5

0.7

1.5

0.7

1.5

0.7

1.5

1

8

Data-in Hold Time

t_DH

8

Address Set-up Time

t_AS

1.5

1

8

Address Hold Time

t_AH

8

CKE Set-up Time

t_CKS

t_CKH

t_CMS

t_CMH

t_REF

t_RSC

t_XSR

1.5

1

8

CKE Hold Time

8

Command Set-up Time

Command Hold Time

1.5

1

8

Refresh Time

64

mS

Mode Register Set Cycle Time

Exit self refresh to ACTIVE command

10

70

12

72

14

75

nS

Publication Release Date:May 05, 2008

Revision A01

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W9816G6IH

Notes:

1. Operation exceeds " Absolute Maximum Ratings " may cause permanent damage to the devices.

2. All voltages are referenced to VSS.

• 2.7V~3.6V power supply for -7/-7I speed grade.

• 3.3V ± 0.3V power supply for -5/-6/-6I speed grades.

3. These parameters depend on the cycle rate and listed values are measured at a cycle rate with the

minimum values of t_CKand t_RC.

4. These parameters depend on the output loading conditions. Specified values are obtained with

output open.

5. Power up sequence please refer to "Functional Description" section described before.

6. AC Test Load diagram.

1.4 V

50 ohms

output

Z = 50 ohms

30pF

ACTEST LOAD

7. t_HZdefines the time at which the outputs achieve the open circuit condition and is not referenced

to output level.

8. Assumed input rise and fall time (t_T) = 1nS.

If tr & tf is longer than 1nS, transient time compensation should be considered,

i.e., [(tr + tf)/2-1]nS should be added to the parameter

( The t_Tmaximum can’t be more than 10nS for low frequency application. )

9. If clock rising time (t_T) is longer than 1nS, (t_T/2-0.5)nS should be added to the parameter.

Publication Release Date:May 05, 2008

- 16 -

Revision A01

W9816G6IH

10. TIMING WAVEFORMS

10.1 Command Input Timing

tCL

tCH

tCK

V^IH

VIL

CLK

tT

tCMS

tCMH

tCMS

CS

RAS

tCMS

tCMH

CAS

WE

tAS

tAH

A0-A10

BA

tCKS

tCKH

tCKS

tCKH

CKE

Publication Release Date:May 05, 2008

Revision A01

- 17 -

W9816G6IH

10.2 Read Timing

Read CAS Latency

CLK

CS

RAS

CAS

WE

A0-A10

BA

tAC

tHZ

tOH

tLZ

Valid

Data-Out

DQ

Read Command

Burst Length

Publication Release Date:May 05, 2008

Revision A01

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W9816G6IH

10.3 Control Timing of Input/Output Data

Control Timing of Input Data

(Word Mask)

CLK

t

CMS

tCMH

t

CMH

tCMS

DQM

t

DS

t

DH

t

DS

t

DH

t

DS

t

DH

t

DS

tDH

Valid

Data-in

Valid

Data-in

DQ0 -15

(Clock Mask)

CLK

t

CKH

t

CKS

t

CKH

tCKS

CKE

t

DS

t

DH

t

DS

t

DH

t

DS

t

DH

t

DS

tDH

Valid

Data-in

Valid

DQ0 -15

Data-in

Control Timing of Output Data

(Output Enable)

CLK

t

CMH

t

CMS

tCMS

t

CMH

DQM

t

AC

t

HZ

tAC

t

AC

t

AC

t

LZ

t

OH

t

OH

t

OH

t

OH

Valid

Data-Out

Valid

Data-Out

OPEN

DQ0 -15

(Clock Mask)

CLK

t

CKH

t

CKS

t

CKH

tCKS

CKE

t

AC

t

AC

tAC

t

OH

t

OH

t

OH

tOH

Valid

Data-Out

Valid

Data-Out

DQ0 -15

Data-Out

Publication Release Date:May 05, 2008

Revision A01

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W9816G6IH

10.4 Mode Register Set Cycle

tRSC

CLK

tCMS

tCMH

CS

RAS

CAS

WE

tCMS

tCMH

tCMS

tAS

tCMH

tAH

A0-A10

BA

Register

set data

A0

A2 A01 A0

BurstAL0ength

A0

SeqAue0ntial

InteArle0ave

0

1

A00

A10

A00

A10

0

1

0

1

0

1

0

1

A10

A20

A40

A80

A1

A2

Burst Length

A20

A40

A80

A3 Addressing Mode

A4

ResAe0rved

FullAP0age

A5

A6

CAS Latency

A30

A00

A10

AddressAin0g Mode

SeqAue0ntial

InteArle0ave

A07 "0" (Test Mode)

A8 "0"

A09

Reserved

A6 A05 A4

CAS ALa0tency

ResAe0rved

2

0

1

A00

A10

A00

0

1

0

1

0

WriteA0Mode

A10

BAA0

"0"

A30

Reserved

A09

A00

A10

Single Write Mode

Burst read aAn0d Burst write

Burst read aAn0d single write

Publication Release Date:May 05, 2008

Revision A01

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W9816G6IH

11. OPERATING TIMING EXAMPLE

11.1 Interleaved Bank Read (Burst Length = 4, CAS Latency = 3)

(CLK = 100 MHz)

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

CLK

CS

t_RC

RAS

CAS

t_RAS

t_RP

t_RAS

t_RP

t_RAS

WE

BA

t_RCD

A10

RAa

RBb

RAc

RBd

RAe

CBx

A0-A9

DQM

RBb

CAy

RAe

CAw

CBz

CKE

DQ

t_AC

bx3

cy2

bx1

aw0

aw2

aw3

bx0

bx2

cy1

cy3

aw1

cy0

t_RRD

Precharge

Read

Active

Read

Bank #0

Bank #1

Read

Active

Precharge

Read

Precharge

Active

Publication Release Date:May 05, 2008

Revision A01

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W9816G6IH

11.2 Interleaved Bank Read (Burst Length = 4, CAS Latency = 3, Auto-precharge)

(CLK = 100 MHz)

11

12

13

14

15

16

17

18

19

20

21

22

23

0

1

2

3

4

5

6

7

8

9

10

CLK

CS

t_RC

RAS

t_RAS

t_RP

t_RAS

t_RP

t_RAS

CAS

WE

BA

t_RCD

RAe

RBd

RAa

RBb

RAc

A10

A0-A9

DQM

CKE

CBz

RAa

CAw

CAy

RAe

CBx

RBb

RAc

RBd

t_AC

DQ

cy3

aw0

aw1 aw2

aw3

bx0 bx1

bx2

bx3

cy0

cy1

cy2

dz0

t_RRD

Read

AP*

Active

AP*

Read

Active

AP*

Active

Bank #0

Bank #1

Read

Active

* AP is the internal precharge start timing

Publication Release Date:May 05, 2008

Revision A01

- 22 -

W9816G6IH

11.3 Interleaved Bank Read (Burst Length = 8, CAS Latency = 3)

(CLK = 100 MHz)

0

1

2

3

4

5

6

7

8

9

10

11 12 13 14

15 16 17 18 19

20 21

22 23

CLK

CS

t_RC

RAS

t_RAS

t_RP

t_RAS

t_RP

CAS

WE

BA

t_RCD

A10

RAa

RAc

RBb

A0-A9

DQM

CAx

CBy

RAc

CAz

CKE

DQ

t_AC

ax0

ax1

ax2

ax3

ax4

ax5 ax6

by0

by1

by4 by5

by6

by7

CZ0

t_RRD

Read

Active

Precharge

Active

Read

Precharge

Bank #0

Bank #1

Active

Precharge

Read

Publication Release Date:May 05, 2008

Revision A01

- 23 -

W9816G6IH

11.4 Interleaved Bank Read (Burst Length = 8, CAS Latency = 3, Auto-precharge)

(CLK = 100 MHz)

1

2

3

4

5

6

7

8

9

10 11 12 13 14

15 16 17 18 19

20 21

22 23

0

CLK

CS

t_RC

RAS

t_RAS

t_RP

t_RAS

t_RP

CAS

WE

BA

t_RCD

A10

RBb

RAc

RAa

CAz

CAx

A0-A9

DQM

RBb

CBy

CKE

DQ

t_CAC

ax3

ax4

ax0

ax2

ax5 ax6

ax7

by0

by1

by4

by5

by6

ax1

CZ0

t_RRD

AP*

Read

Active

Bank #0 Active

Bank #1

Read

Active

AP*

* AP is the internal precharge start timing

Publication Release Date:May 05, 2008

Revision A01

- 24 -

W9816G6IH

11.5 Interleaved Bank Write (Burst Length = 8)

(CLK = 100 MHz)

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15 16

17

18

19

20 21

22

23

CLK

CS

t_RC

RAS

CAS

WE

t_RAS

t_RP

t_RAS

t_RP

t_RCD

BA

RBb

RAc

A10

RAa

CAx

RBb

CBy

CAz

A0-A9

DQM

CKE

DQ

ax0

ax1

ax4

ax5

ax6

ax7

by0

by1

by2

by3

by4

by5

by6

by7

CZ0

CZ1

CZ2

t_RRD

Active

Write

Precharge

Active

Write

Bank #0

Bank #1

Active

Write

Precharge

Publication Release Date:May 05, 2008

Revision A01

- 25 -

W9816G6IH

11.6 Interleaved Bank Write (Burst Length = 8, Auto-precharge)

(CLK = 100 MHz)

0

1

2

3

4

5

6

7

8

9

10

11

12

13 14

15 16

17

18

19

20 21

22 23

CLK

CS

tRC

RAS

CAS

tRP

tRAS

tRP

WE

BA

tRCD

RAa

RBb

RAb

A10

CAx

CBy

CAz

RAc

A0-A9

DQM

CKE

DQ

ax4

by2

by5

ax0 ax1

ax5

ax6

ax7

by0 by1

by3

by4

by6

by7

CZ0

CZ1

CZ2

tRRD

AP*

Active

Write

Active

Write

Bank #0

Bank #1

Active

Write

AP*

* AP is the internal precharge start timing

Publication Release Date:May 05, 2008

Revision A01

- 26 -

W9816G6IH

11.7 Page Mode Read (Burst Length = 4, CAS Latency = 3)

(CLK = 100 MHz)

6

7

8

9

10

11

12

13

14

15 16

17

18

19

20 21

22 23

1

2

3

4

5

0

CLK

CS

t_CCD

t_RAS

t_RP

t_RAS

t_RP

RAS

CAS

WE

BA

t_RCD

RAa

RBb

A10

A0-A9

CAm

CBz

CAI

CBx

CAy

DQM

CKE

t_AC

a0

a1

a2

a3

bx0

bx1

Ay0

Ay1

Ay2

am0 am1

am2

bz0

bz1

bz2

bz3

DQ

t_RRD

Read

Bank #0 Active

Bank #1

Read

Precharge

AP*

Active

Read

* AP is the internal precharge start timing

Publication Release Date:May 05, 2008

Revision A01

- 27 -

W9816G6IH

11.8 Page Mode Read / Write (Burst Length = 8, CAS Latency = 3)

(CLK = 100 MHz)

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

CLK

CS

t_RAS

t_RP

RAS

CAS

WE

BA

t_RCD

A10

RAa

CAx

CAy

A0-A9

DQM

CKE

t_AC

t_WR

ax5

ay1

ax0

ax1

ax3

ay0

ay2

ay4

ax2

ax4

ay3

DQ

Q

D

Bank #0

Bank #1

Active

Read

Write

Precharge

Publication Release Date:May 05, 2008

Revision A01

- 28 -

W9816G6IH

11.9 Auto Precharge Read (Burst Length = 4, CAS Latency = 3)

(CLK = 100 MHz)

16

17

18

19

20

21

22

23

6

7

8

9

10

11

12

13

14

15

1

2

3

4

5

0

CLK

CS

t_RC

RAS

t_RAS

t_RP

t_RAS

t_RP

CAS

WE

BA

t_RCD

A10

RAa

RAb

A0-A9

CAx

RAa

CAw

RAb

DQM

CKE

DQ

t_AC

aw0

aw1 aw2 aw3

bx0

bx1

bx2 bx3

Bank #0

Bank #1

AP*

Active

Read

Active

Read

AP*

* AP is the internal precharge start timing

Publication Release Date:May 05, 2008

Revision A01

- 29 -

W9816G6IH

11.10 Auto Precharge Write (Burst Length = 4)

(CLK = 100 MHz)

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

CLK

CS

tRC

RAS

CAS

tRAS

tRP

tRAS

tRP

WE

BA

tRCD

RAc

RAa

RAb

A10

A0-A9

DQM

CKE

CAw

RAb

CAx

RAc

bx0

aw1 aw2

bx1

bx3

bx2

aw0

aw3

DQ

Active

AP*

Bank #0

Bank #1

Write

Active

Write

Active

AP*

* AP is the internal precharge start timing

Publication Release Date:May 05, 2008

Revision A01

- 30 -

W9816G6IH

11.11 Auto Refresh Cycle

(CLK = 100 MHz)

10 11 12 13 14 15 16 17 18 19 20 21 22 23

0

1

2

3

4

5

6

7

8

9

CLK

CS

t

RP

t

RC

tRC

RAS

CAS

WE

BA

A10

A0-A9

DQM

CKE

DQ

All Banks

Prechage

Auto

Auto Refresh (Arbitrary Cycle)

Refresh

Publication Release Date:May 05, 2008

Revision A01

- 31 -

W9816G6IH

11.12 Self Refresh Cycle

(CLK = 100 MHz)

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

CLK

CS

tRP

RAS

CAS

WE

BA

A10

A0-A9

DQM

tCKS

tSB

CKE

DQ

tCKS

tXSR

Self Refresh Cycle

No Operation / Command Inhibit

Self Refresh

Exit

All Banks

Self Refresh

Entry

Arbitrary Cycle

Precharge

Publication Release Date:May 05, 2008

Revision A01

- 32 -

W9816G6IH

11.13 Burst Read and Single Write (Burst Length = 4, CAS Latency = 3)

(CLK = 100 MHz)

6

7

8

11 12 13

16 17 18

1

2

3

5

9

10

14 15

19

21

0

4

20

22 23

CLK

CS

RAS

CAS

WE

t_RCD

BA

A10

RBa

A0-A9

CBz

RBa

CBv

CBw

CBx CBy

DQM

CKE

t_AC

DQ

av0

av1

av3

aw0

ax0

ay0

az1

az2

az3

az0

av2

Q

D

Q

Read

Active

Single Write

Read

Bank #0

Bank #1

Publication Release Date:May 05, 2008

Revision A01

- 33 -

W9816G6IH

11.14 Power Down Mode

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

CLK

CS

RAS

CAS

WE

BA

RAa

A10

A0-A9

DQM

CAa

CAx

tSB

CKE

DQ

tCKS

ax0

ax2

ax3

ax1

Active

NOP Read

Active Standby

Precharge

NOPActive

Precharge Standby

Power Down mode

Note: The PowerDown Mode is entered by asserting CKE "low".

All Input/Output buffers (except CKE buffers) are turned off in the Power Down mode.

When CKE goes high, command input must be No operation at next CLK rising edge.

Violating refresh requirements during power-down may result in a loss of data.

Publication Release Date:May 05, 2008

Revision A01

- 34 -

W9816G6IH

11.15 Auto-precharge Timing (Read Cycle)

0

1

2

3

4

5

6

7

8

9

10

11

(1) CAS Latency=2

( a ) burst length = 1

Command

Read

AP

Act

t

RP

DQ

Q0

( b ) burst length = 2

Command

Read

AP

Q0

Act

tRP

DQ

Q1

( c ) burst length = 4

Command

AP

Q2

Act

Q4

t

RP

DQ

Q0

Q1

Q3

( d ) burst length = 8

Command

AP

Q6

Act

t

RP

DQ

Q2

Act

Q3

Q5

Q7

(2) CAS Latency=3

( a ) burst length = 1

Read

AP

Command

tRP

DQ

Q0

( b ) burst length = 2

Command

AP

Act

tRP

DQ

Q1

AP

Q1

( c ) burst length = 4

Command

Act

Q4

tRP

DQ

Q2

Q3

( d ) burst length = 8

Command

AP

Q5

Act

tRP

DQ

Q1

Q6

Q7

Note:

Read

represents the Read with Auto precharge command.

represents the start of internal precharging.

represents the Bank Activate command.

AP

Act

When the Auto precharge command is asserted, the period from Bank Activate command to

the start of internal precgarging must be at least tRAS (min).

Publication Release Date:May 05, 2008

Revision A01

- 35 -

W9816G6IH

11.16 Auto-precharge Timing (Write Cycle)

0

1

2

3

4

5

6

7

8

9

10

11

12

CLK

(1) CAS Latency = 2

(a) burst length = 1

Command

Write

D0

AP

tWR

D2

Act

tRP

tWR

DQ

(b) burst length = 2

Command

Write

D0

AP

Act

AP

tRP

DQ

D1

(c) burst length = 4

Command

Act

D7

Write

D0

tRP

tWR

DQ

D3

(d) burst length = 8

Command

Write

D0

AP

Act

tRP

tWR

DQ

D1

D2

AP

D4

D5

D6

(2) CAS Latency = 3

(a) burst length = 1

Write

D0

Act

Command

tRP

tWR

DQ

(b) burst length = 2

Command

Write

D0

AP

Act

tRP

tWR

DQ

D1

(c) burst length = 4

Command

Write

D0

AP

D5

Act

tRP

tWR

DQ

D2

D3

(d) burst length = 8

Command

Act

Write

D0

AP

tWR

tRP

DQ

D4

D6

D7

Note )

represents the Write with Auto precharge command.

represents the start of internal precharing.

represents the Bank Active command.

Write

AP

AAcctt

When the /auto precharge command is asserted,the period from Bank Activate

command to the start of intermal precgarging must be at least tRAS (min).

Publication Release Date:May 05, 2008

Revision A01

- 36 -

W9816G6IH

11.17 Timing Chart of Read to Write Cycle

In the case of Burst Length = 4

1

2

3

4

5

6

7

8

9

10

11

0

(1) CAS Latency=2

( a ) Command

Read Write

DQM

DQ

D0

D1

D2

D1

D3

D2

( b ) Command

Read

Write

DQM

DQ

D0

D3

(2) CAS Latency=3

( a ) Command

DQM

Read Write

DQ

D0

D1

Write

D2

D1

D3

D2

( b ) Command

Read

DQM

DQ

D0

Note: The Output data must be masked by DQM to avoid I/O conflict

11.18Timing Chart of Write to Read Cycle

In the case of Burst Length=4

1

2

3

4

5

6

7

8

9

10

11

0

(1) CAS Latency=2

Write Read

( a ) Command

DQM

DQ

D0

Q0

Q1

Q0

Q2

Q1

Q3

Q2

( b ) Command

DQM

Read

Write

DQ

D0

D1

Q3

(2) CAS Latency=3

( a ) Command

DQM

Write Read

DQ

D0

Write

Q0

Q1

Q0

Q2

Q1

Q3

Q2

( b ) Command

DQM

Read

DQ

D0

D1

Q3

Publication Release Date:May 05, 2008

Revision A01

- 37 -

W9816G6IH

11.19 Timing Chart of Burst Stop Cycle (Burst Stop Command)

0

1

2

3

4

5

6

7

8

9

10

11

(1) Read cycle

( a ) CAS latency =2

Command Read

BST

Q3

DQ

Q0

Q1

Q0

Q2

Q1

Q4

Q3

( b )CAS latency = 3

Command

Read

BST

Q2

DQ

Q4

(2) Write cycle

Command

DQ

Write

Q0

BST

Q1

Q2

Q3

Q4

Note: BST

represents the Burst stop command

11.20Timing Chart of Burst Stop Cycle (Precharge Command)

0

1

2

3

4

5

6

7

8

9

10

11

(1) Read cycle

(a) CAS latency =2

Read

PRCG

Q3

Command

DQ

Q0

Q1

Q0

Q2

Q1

Q4

Q3

(b) CAS latency =3

PRCG

Q2

Command

DQ

Q4

(2) Write cycle

(a) CAS latency =2

PRCG

Write

Command

tWR

DQM

DQ

Q0

Q1

Q2

Q3

Q4

(b) CAS latency =3

Write

Command

DQM

DQ

Q0

Q3

Q4

Publication Release Date:May 05, 2008

Revision A01

- 38 -

W9816G6IH

11.21 CKE/DQM Input Timing (Write Cycle)

1

CLK cycle No.

2

3

4

5

7

6

External

CLK

Internal

CKE

DQM

DQ

D1

D2

2

D3

3

D5

5

D6

7

DQM MASK

CKE MASK

( 1 )

CLK cycle No.

External

4

1

6

CLK

Internal

CKE

DQM

DQ

D1

1

D2

D3

D6

D5

DQM MASK

( 2 )

CKE MASK

2

3

4

5

6

7

CLK cycle No.

External

CLK

Internal

CKE

DQM

DQ

D1

D2

D3

D4

D5

D6

CKE MASK

( 3 )

Publication Release Date:May 05, 2008

Revision A01

- 39 -

W9816G6IH

11.22 CKE/DQM Input Timing (Read Cycle)

1

CLK cycle No.

6

2

3

4

5

7

External

Internal

CLK

CKE

DQM

DQ

Q6

7

Q1

1

Q2

2

Q3

3

Q4

Open

( 1 )

4

5

CLK cycle No.

6

External

Internal

CLK

CKE

DQM

DQ

Q6

7

Q3

Q1

1

Q2

2

Q4

Open

( 2 )

CLK cycle No.

3

4

5

6

External

CLK

Internal

CKE

DQM

DQ

Q6

Q1

Q4

Q5

Q3

Q2

( 3 )

Publication Release Date:May 05, 2008

Revision A01

- 40 -

W9816G6IH

12. PACKAGE SPECIFICATION

12.1 50L-TSOP (II) 400 mill

50

26

H_E

E

1

25

e

b

C

D

q

L

A2

A1

A

L1

ZD

SEATING PLANE

Y

Controlling Dimension: Millimeters

(MM)

(INCH)

NOM. MAX.

0.047

DIMENSION

SYM.

MIN.

NOM. MAX. MIN.

1.20

A

0.15

1.10

0.45

0.20

21.08

10.29

11.96

0.006

A1

0.05

0.90

0.30

0.10

20.82

10.03

11.56

0.10

1.00

0.002 0.004

0.035 0.039

0.012

0.004 0.006

0.820 0.825

0.395 0.400

0.455 0.463

0.031

0.043

0.018

0.008

0.830

0.405

0.471

A2

b

c

0.15

20.95

10.16

11.76

0.80

D

E

H_E

e

0.50

0.80

0.40

0.60

0.10

0.016 0.020

0.031

0.024

0.004

10^o

L

L1

Y

ZD

0.88

0.031

10^o

0^o

o

θ

0

Publication Release Date:May 05, 2008

Revision A01

- 41 -

W9816G6IH

13. REVISION HISTORY

VERSION

DATE

PAGE

DESCRIPTION

A01

May 05, 2008

All

Initial formal data sheet

Important Notice

Winbond products are not designed, intended, authorized or warranted for use as components

in systems or equipment intended for surgical implantation, atomic energy control

instruments, airplane or spaceship instruments, transportation instruments, traffic signal

instruments, combustion control instruments, or for other applications intended to support or

sustain life. Further more, Winbond products are not intended for applications wherein failure

of Winbond products could result or lead to a situation wherein personal injury, death or

severe property or environmental damage could occur.

Winbond customers using or selling these products for use in such applications do so at their

own risk and agree to fully indemnify Winbond for any damages resulting from such improper

use or sales.

Publication Release Date:May 05, 2008

- 42 -

Revision A01

型号:	W9816G6IH-7
是否Rohs认证：	符合
生命周期：	Active
IHS 制造商：	WINBOND ELECTRONICS CORP
零件包装代码：	TSOP2
包装说明：	TSOP2, TSOP50,.46,32
针数：	50
Reach Compliance Code：	compliant
ECCN代码：	EAR99
HTS代码：	8542.32.00.02
风险等级：	5.23
Is Samacsys：	N
访问模式：	DUAL BANK PAGE BURST
最长访问时间：	5 ns
其他特性：	AUTO/SELF REFRESH
最大时钟频率 (fCLK)：	143 MHz
I/O 类型：	COMMON
交错的突发长度：	1,2,4,8
JESD-30 代码：	R-PDSO-G50
长度：	20.95 mm
内存密度：	16777216 bit
内存集成电路类型：	SYNCHRONOUS DRAM
内存宽度：	16
功能数量：	1
端口数量：	1
端子数量：	50
字数：	1048576 words
字数代码：	1000000
工作模式：	SYNCHRONOUS
最高工作温度：	70 °C
最低工作温度：
组织：	1MX16
输出特性：	3-STATE
封装主体材料：	PLASTIC/EPOXY
封装代码：	TSOP2
封装等效代码：	TSOP50,.46,32
封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, THIN PROFILE
峰值回流温度（摄氏度）：	NOT SPECIFIED
电源：	3/3.3 V
认证状态：	Not Qualified
刷新周期：	4096
座面最大高度：	1.2 mm
自我刷新：	YES
连续突发长度：	1,2,4,8,FP
最大待机电流：	0.002 A
子类别：	DRAMs
最大压摆率：	0.1 mA
最大供电电压 (Vsup)：	3.6 V
最小供电电压 (Vsup)：	3 V
标称供电电压 (Vsup)：	3.3 V
表面贴装：	YES
技术：	CMOS
温度等级：	COMMERCIAL
端子形式：	GULL WING
端子节距：	0.8 mm
端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	10.16 mm
Base Number Matches：	1

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