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W986432DH

´ 4 BANKS ´ 32 BITS SDRAM

512K

Table of Contents-

1. GENERAL DESCRIPTION ..................................................................................................................3

2. FEATURES..........................................................................................................................................3

3. AVAILABLE PART NUMBER...............................................................................................................3

4. PIN CONFIGURATION........................................................................................................................4

5. PIN DESCRIPTION..............................................................................................................................5

6. BLOCK DIAGRAM ...............................................................................................................................6

7. FUNCTIONAL DESCRIPTION ............................................................................................................7

Power Up and Initialization................................................................................................................7

Programming Mode Register............................................................................................................7

Bank Activate Command ..................................................................................................................7

Read and Write Access Modes ........................................................................................................7

Burst Read Command ......................................................................................................................8

Burst Command................................................................................................................................8

Read Interrupted by a Read..............................................................................................................8

Read Interrupted by a Write..............................................................................................................8

Write Interrupted by a Write..............................................................................................................8

Write Interrupted by a Read..............................................................................................................8

Burst Stop Command .......................................................................................................................8

Addressing Sequence of Sequential Mode.......................................................................................9

Addressing Sequence of Interleave Mode........................................................................................9

Auto-precharge Command .............................................................................................................10

Precharge Command......................................................................................................................10

Self Refresh Command ..................................................................................................................10

Power Down Mode..........................................................................................................................10

No Operation Command.................................................................................................................11

Deselect Command ........................................................................................................................11

Clock Suspend Mode......................................................................................................................11

8. TABLE OF OPERATING MODES .....................................................................................................12

9. SIMPLIFIED STATE DIAGRAM.........................................................................................................13

10. DC CHARACTERISTICS.................................................................................................................14

Absolute Maximum Rating..............................................................................................................14

11. RECOMMENDED DC OPERATING CONDITIONS........................................................................14

12. CAPACITANCE................................................................................................................................14

13. DC CHARACTERISTICS.................................................................................................................15

Publication Release Date: July 30, 2002

- 1 -

Revision A5

W986432DH

14. AC CHARACTERISTICS .................................................................................................................16

15. TIMING WAVEFORMS....................................................................................................................19

Command Input Timing ..................................................................................................................19

Timing Waveforms, continued .................................................................................................................20

Read Timing ...................................................................................................................................20

Timing Waveforms, continued .................................................................................................................21

Control Timing of Input Data...........................................................................................................21

Timing Waveforms, continued .................................................................................................................22

Control Timing of Output Data........................................................................................................22

Timing Waveforms, continued .................................................................................................................23

Mode Register Set Cycle ................................................................................................................23

16. OPERATING TIMING EXAMPLE ....................................................................................................24

Interleaved Bank Read (Burst Length = 4, CAS Latency = 3) ........................................................24

Interleaved Bank Read (Burst Length = 4, CAS Latency = 3, Autoprecharge)...............................25

Interleaved Bank Read (Burst Length = 8, CAS Latency = 3) ........................................................26

Interleaved Bank Read (Burst Length = 8, CAS Latency = 3, Autoprecharge)...............................27

Interleaved Bank Write (Burst Length = 8) .....................................................................................28

Interleaved Bank Write (Burst Length = 8, Autoprecharge)............................................................29

Page Mode Read (Burst Length = 4, CAS Latency = 3).................................................................30

Page Mode Read/Write (Burst Length = 8, CAS Latency = 3) .......................................................31

Autoprecharge Read (Burst Length = 4, CAS Latency = 3)............................................................32

Autoprecharge Write (Burst Length = 4).........................................................................................33

Autorefresh Cycle ...........................................................................................................................34

Self-refresh Cycle ...........................................................................................................................35

Bust Read and Single Write (Burst Length = 4, CAS Latency = 3).................................................36

Power-down Mode..........................................................................................................................37

Auto-precharge Timing (Write Cycle) .............................................................................................38

Auto-precharge Timing (Read Cycle) .............................................................................................39

Timing Chart of Read to Write Cycle..............................................................................................40

Timing Chart of Write to Read Cycle..............................................................................................41

Timing Chart of Burst Stop Cycle (Burst Stop Command) .............................................................42

Timing Chart of Burst Stop Cycle (Precharge Command)..............................................................43

CKE/DQM Input Timing (Write Cycle) ............................................................................................44

CKE/DQM Input Timing (Read Cycle) ............................................................................................45

Self Refresh/Power Down Mode Exit Timing..................................................................................46

17. PACKAGE DIMENSION ..................................................................................................................47

86L TSOP (II)-400 mil.....................................................................................................................47

18. VERSION HISTORY........................................................................................................................48

- 2 -

W986432DH

1. GENERAL DESCRIPTION

W986432DH is a high-speed synchronous dynamic random access memory (SDRAM), organized as

512K words x 4 banks x 32 bits. Using pipelined architecture and 0.175 mm process technology,

W986432DH delivers a data bandwidth of up to 800M bytes per second (-5). For different application,

W986432DH is sorted into the following speed grades: -5, -6, -7. The -5 parts can run up to 200

MHz/CL3. The -6 parts can run up to 166 MHz/CL3. The -7 parts can run up to 143 MHz/CL3. For

handheld device application, we also provide low power option, the grade of -7L, with Self Refresh

Current under 400 mA and work well at 2.7V during Self Refresh Mode. For special application, we

provide extended temperature option the grade of -6I can work well in wide temperature from -25° C to

85° C.

Accesses to the SDRAM are burst oriented. Consecutive memory location in one page can be

accessed at a burst length of 1, 2, 4, 8 or full page when a bank and row is selected by an ACTIVE

command. Column addresses are automatically generated by the SDRAM internal counter in burst

operation. Random column read is also possible by providing its address at each clock cycle. The

multiple bank nature enables interleaving among internal banks to hide the precharging time.

By having a programmable Mode Register, the system can change burst length, latency cycle,

interleave or sequential burst to maximize its performance. W986432DH is ideal for main memory in

high performance applications.

2. FEATURES

· Byte data controlled by DQM

· Power-down Mode

· 3.3V ±0.3V power supply

· 524288 words x 4 banks x 32 bits organization

· Self Refresh Current: Standard and Low Power

· CAS latency: 2 and 3

· Auto-precharge and controlled precharge

· 4K refresh cycles/64 mS

· Interface: LVTTL

· Burst Length: 1, 2, 4, 8, and full page

· Sequential and Interleave burst

· Burst read, single write operation

· Packaged in 86-pin TSOP II, 400 mil - 0.50

3. AVAILABLE PART NUMBER

SELF REFRESH

CURRENT (MAX.)

OPERATING

TEMPERATURE

PART NUMBER

SPEED (CL = 3)

W986432DH-5

W986432DH-6

W986432DH-6I

W986432DH-7

W986432DH-7L

200 MHz

166 MHz

143 MHz

1 mA

0° C - 70° C

-25° C - 85° C

0° C - 70° C

400 mA

1 mA

400 mA

Publication Release Date: July 30, 2002

Revision A5

- 3 -

W986432DH

4. PIN CONFIGURATION

VCC

DQ0

CC

1

2

86

85

84

83

82

81

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

V

ss

DQ15

SS

V

Q

3

V

Q

DQ1

DQ2

4

DQ14

DQ13

5

V

SS

Q

6

CC

V Q

DQ12

DQ11

DQ3

DQ4

7

8

CC

V Q

9

SS

V Q

DQ5

DQ6

VSSQ

DQ7

NC

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

DQ10

DQ9

VCCQ

DQ8

NC

VCC

DQM0

WE

V

SS

DQM1

NC

CAS

RAS

NC

CLK

CKE

A9

CS

NC

BS0

BS1

A8

A7

A10/AP

A0

A6

A5

A1

A4

A2

A3

DQM2

DQM3

V

CC

V

SS

NC

DQ16

DQ31

V

SS

Q

CC

V Q

DQ17

DQ18

DQ30

DQ29

V

CCQ

VSSQ

DQ19

DQ20

DQ28

DQ27

V

SS

Q

CC

V Q

DQ21

DQ22

DQ26

DQ25

V

CC

DQ23

CC

Q

V

SS

DQ24

SS

Q

V

- 4 -

W986432DH

5. PIN DESCRIPTION

PIN NUMBER

PIN NAME

FUNCTION

DESCRIPTION

Multiplexed pins for row and column address.

Row address: A0 - A10. Column address:

A0 - A7. A10 is sampled during a precharge

command to determine if all banks are to be

precharged or bank selected by BS0, BS1.

24, 25, 26, 27, 60,

Address

A0 - A10

61, 62, 63, 64, 65, 66

Select bank to activate during row address

latch time, or bank to read/write during

address latch time.

22, 23

BS0, BS1

Bank Select

2, 4, 5, 7, 8, 10, 11, 13, 31,

33, 34, 36, 37, 39, 40, 42, 45,

47, 48, 50, 51, 53, 54, 56, 74,

76, 77, 79, 80, 82, 83, 85

DQ0-

Data Input/

Output

Multiplexed pins for data output and input.

DQ31

Disable or enable the command decoder.

When command decoder is disabled, new

command is ignored and previous operation

continues.

20

19

Chip Select

CS

Command input. When sampled at the rising

Row Address

Strobe

RAS

edge of the clock RAS , CAS and WE

define the operation to be executed.

Column

Address Strobe

18

17

CAS

WE

Referred to RAS

Write Enable

Referred to RAS

The output buffer is placed at Hi-Z (with

Input/Output latency of 2) when DQM is sampled high in

DQM0-

16, 28, 59, 71

Mask

read cycle. In write cycle, sampling DQM high

will block the write operation with zero latency.

DQM3

System clock used to sample inputs on the

rising edge of clock.

68

67

CLK

CKE

Clock Inputs

CKE controls the clock activation and

deactivation. When CKE is low, Power Down

mode, Suspend mode, or Self Refresh mode

is entered.

Clock Enable

Power for input buffers and logic circuit inside

DRAM.

1, 15, 29, 43

VCC

VSS

Power (+3.3V)

Ground

Ground for input buffers and logic circuit

inside DRAM.

44, 58, 72, 86

Power (+3.3V) Separated power from VCC, to improve DQ

for I/O Buffer noise immunity.

3, 9, 35, 41, 49, 55, 75, 81

VCCQ

Ground for I/O Separated ground from VSS, to improve DQ

6, 12, 32, 38, 46, 52, 78, 84

14, 21, 30, 57, 69, 70, 73

VSSQ

Buffer

noise immunity.

NC

No Connection No connection

Publication Release Date: July 30, 2002

Revision A5

- 5 -

W986432DH

6. BLOCK DIAGRAM

CLK

CLOCK

BUFFER

CKE

CONTROL

CS

SIGNAL

GENERATOR

RAS

COMMAND

CAS

DECODER

COLUMN DECODER

WE

CELL ARRAY

BANK #0

CELL ARRAY

BANK #1

A10

MODE

REGISTER

A0

SENSE AMPLIFIER

ADDRESS

BUFFER

A9

BS0

BS1

DQ0

DATA CONTROL

CIRCUIT

DQ

BUFFER

DQ31

COLUMN

REFRESH

COUNTER

DQM0~3

COLUMN DECODER

CELL ARRAY

BANK #2

CELL ARRAY

BANK #3

SENSE AMPLIFIER

NOTE:

The cell array configuration is 2048 * 256 * 32

- 6 -

W986432DH

7. FUNCTIONAL DESCRIPTION

Power Up and Initialization

The default power up state of the mode register is unspecified. The following power up and initialization

sequence need to be followed to guarantee the device being preconditioned to each user specific

needs.

During power up, all VCC and VCCQ pins must be ramp up simultaneously to the specified voltage

when the input signals are held in the "NOP" state. The power up voltage must not exceed VCC +0.3V

on any of the input pins or VCC supplies. After power up, an initial pause of 200 mS is required followed

by a precharge of all banks using the precharge command. To prevent data contention on the DQ bus

during power up, it is required that the DQM and CKE pins be held high during the initial pause period.

Once all banks have been precharged, the Mode Register Set Command must be issued to initialize

the Mode Register. An additional eight Auto Refresh cycles (CBR) are also required before or after

programming the Mode Register to ensure proper subsequent operation.

Programming Mode Register

After initial power up, the Mode Register Set Command must be issued for proper device operation. All

banks must be in a precharged state and CKE must be high at least one cycle before the Mode

Register Set Command can be issued. The Mode Register Set Command is activated by the low

signals of RAS, CAS , CS and WE at the positive edge of the clock. The address input data

during this cycle defines the parameters to be set as shown in the Mode Register Operation table. A

new command may be issued following the mode register set command once a delay equal to tRSC has

elapsed. Please refer to the next page for Mode Register Set Cycle and Operation Table.

Bank Activate Command

The Bank Activate command must be applied before any Read or Write operation can be executed.

The operation is similar to RAS activate in EDO DRAM. The delay from when the Bank Activate

command is applied to when the first read or write operation can begin must not be less than the RAS

to CAS delay time (tRCD). Once a bank has been activated it must be precharged before another Bank

Activate command can be issued to the same bank. The minimum time interval between successive

Bank Activate commands to the same bank is determined by the RAS cycle time of the device (tRC).

The minimum time interval between interleaved Bank Activate commands (Bank A to Bank B and vice

versa) is the Bank to Bank delay time (tRRD). The maximum time that each bank can be held active is

specified as TRAS (max.).

Read and Write Access Modes

After a bank has been activated, a read or write cycle can be followed. This is accomplished by setting

RAS high and CAS low at the clock rising edge after minimum of tRCD delay. WE pin voltage

level defines whether the access cycle is a read operation ( WE high), or a write operation ( WE

low). The address inputs determine the starting column address. Reading or writing to a different row

within an activated bank requires the bank be precharged and a new Bank Activate command be

issued. When more than one bank is activated, interleaved bank Read or Write operations are

possible. By using the programmed burst length and alternating the access and precharge operations

between multiple banks, seamless data access operation among many different pages can be

realized. Read or Write Commands can also be issued to the same bank or between active banks on

every clock cycle.

Publication Release Date: July 30, 2002

- 7 -

Revision A5

W986432DH

Burst Read Command

The Burst Read command is initiated by applying logic low level to CS and CAS while holding

RAS and WE high at the rising edge of the clock. The address inputs determine the starting

column address for the burst.

The Mode Register sets type of burst (sequential or interleave) and

the burst length (1, 2, 4, 8, full page) during the Mode Register Set Up cycle. Table 2 and 3 in the next

page explain the address sequence of interleave mode and sequence mode.

Burst Command

The Burst Write command is initiated by applying logic low level to CS, CAS and WE while

holding RAS high at the rising edge of the clock. The address inputs determine the starting column

address. Data for the first burst write cycle must be applied on the DQ pins on the same clock cycle

that the Write Command is issued. The remaining data inputs must be supplied on each subsequent

rising clock edge until the burst length is completed. Data supplied to the DQ pins after burst finishes

will be ignored.

Read Interrupted by a Read

A Burst Read may be interrupted by another Read Command. When the previous burst is interrupted,

the remaining addresses are overridden by the new read address with the full burst length. The data

from the first Read Command continues to appear on the outputs until the CAS latency from the

interrupting Read Command the is satisfied.

Read Interrupted by a Write

To interrupt a burst read with a Write Command, DQM may be needed to place the DQs (output

drivers) in a high impedance state to avoid data contention on the DQ bus. If a Read Command will

issue data on the first and second clocks cycles of the write operation, DQM is needed to insure the

DQs are tri-stated. After that point the Write Command will have control of the DQ bus and DQM

masking is no longer needed.

Write Interrupted by a Write

A burst write may be interrupted before completion of the burst by another Write Command. When the

previous burst is interrupted, the remaining addresses are overridden by the new address and data will

be written into the device until the programmed burst length is satisfied.

Write Interrupted by a Read

A Read Command will interrupt a burst write operation on the same clock cycle that the Read

Command is activated. The DQs must be in the high impedance state at least one cycle before the

new read data appears on the outputs to avoid data contention. When the Read Command is

activated, any residual data from the burst write cycle will be ignored.

Burst Stop Command

A Burst Stop Command may be used to terminate the existing burst operation but leave the bank open

for future Read or Write Commands to the same page of the active bank, if the burst length is full

page. Use of the Burst Stop Command during other burst length operations is illegal. The Burst Stop

Command is defined by having RAS and CAS high with CS and WE low at the rising

edge of the clock. The data DQs go to a high impedance state after a delay, which is equal to the CAS

Latency in a burst read cycle, interrupted by Burst Stop. If a Burst Stop Command is issued during a

full page burst write operation, then any residual data from the burst write cycle will be ignored.

- 8 -

W986432DH

Addressing Sequence of Sequential Mode

A column access is performed by increasing the address from the column address which is input to the

device. The disturb address is varied by the Burst Length as shown in Table 1.

Table 1. Address Sequence of Sequential Mode

DATA

Data 0

Data 1

Data 2

Data 3

Data 4

Data 5

Data 6

Data 7

ACCESS ADDRESS

BURST LENGTH

n

BL = 2 (disturb address is A0)

n + 1

n + 2

n + 3

n + 4

n + 5

n + 6

n + 7

No address carry from A0 to A1

BL = 4 (disturb addresses are A0 and A1)

No address carry from A1 to A2

BL = 8 (disturb addresses are A0, A1 and A2)

No address carry from A2 to A3

Addressing Sequence of Interleave Mode

A column access is started in the input column address and is performed by inverting the address bit in

the sequence shown in Table 2.

Table 2. Address Sequence of Interleave Mode

DATA

Data 0

Data 1

ACCESS ADDRESS

BUST LENGTH

A8 A7 A6 A5 A4 A3 A2 A1 A0

BL = 2

A8 A7 A6 A5 A4 A3 A2 A1 A0

Data 2

Data 3

Data 4

Data 5

Data 6

Data 7

BL = 4

BL = 8

Publication Release Date: July 30, 2002

Revision A5

- 9 -

W986432DH

Auto-precharge Command

If A10 is set to high when the Read or Write Command is issued, then the auto-precharge function is

entered. During auto-precharge, a Read Command will execute as normal with the exception that the

active bank will begin to precharge automatically before all burst read cycles have been completed.

Regardless of burst length, it will begin a certain number of clocks prior to the end of the scheduled

burst cycle. The number of clocks is determined by CAS latency.

A Read or Write Command with auto-precharge cannot be interrupted before the entire burst operation

is completed for the same bank. Therefore, use of a Read, Write, or Precharge Command is prohibited

during a read or write cycle with auto-precharge. Once the precharge operation has started, the bank

cannot be reactivated until the Precharge time (tRP) has been satisfied. Issue of Auto-Precharge

command is illegal if the burst is set to full page length. If A10 is high when a Write Command is

issued, the Write with Auto-Precharge function is initiated. The SDRAM automatically enters the

precharge operation one clock delay from the last burst write cycle. This delay is referred to as write

tDPL. The bank undergoing auto-precharge cannot be reactivated until tDPL and tRP are satisfied. This is

referred to as tDAL, Data-in to Active delay (tDAL = tWR + tRP). When using the Auto-precharge Command,

the interval between the Bank Activate Command and the beginning of the internal precharge

operation must satisfy tRAS (min).

Precharge Command

The Precharge Command is used to precharge or close a bank that has been activated. The

Precharge Command is entered when CS, RAS and WE are low and CAS is high at the

rising edge of the clock. The Precharge Command can be used to precharge each bank separately or

all banks simultaneously. Three address bits, A10, BS0, and BS1 are used to define which bank(s) is

to be precharged when the command is issued. After the Precharge Command is issued, the

precharged bank must be reactivated before a new read or write access can be executed. The delay

between the Precharge Command and the Activate Command must be greater than or equal to the

Precharge time (tRP).

Self Refresh Command

The Self Refresh Command is defined by having CS, RAS, CAS and CKE held low with WE

high at the rising edge of the clock. All banks must be idle prior to issuing the Self Refresh Command.

Once the command is registered, CKE must be held low to keep the device in Self Refresh mode.

When the SDRAM has entered Self Refresh mode all of the external control signals, except CKE, are

disabled. The clock is internally disabled during Self Refresh Operation to save power. The device will

exit Self Refresh operation after CKE is returned high. A minimum delay time is required when the

device exits Self Refresh Operation and before the next command can be issued. This delay is equal

to the tAC cycle time plus the Self Refresh exit time.

If, during normal operation, AUTO REFRESH cycles are issued in bursts (as opposed to being evenly

distributed), a burst of 4,096 AUTO REFRESH cycles should be completed just prior to entering and

just after exiting the self refresh mode.

Power Down Mode

The Power Down mode is initiated by holding CKE low. All of the receiver circuits except CKE are

gated off to reduce the power. The Power Down mode does not perform any refresh operations,

therefore the device can not remain in Power Down mode longer than the Refresh period (tREF) of the

device.

- 10 -

W986432DH

The Power Down mode is exited by bringing CKE high. When CKE goes high, a No Operation

Command is required on the next rising clock edge, depending on tCK. The input buffers need to be

enabled with CKE held high for a period equal to tCKS (min.) + tCK (min.).

No Operation Command

The No Operation Command should be used in cases when the SDRAM is in a idle or a wait state to

prevent the SDRAM from registering any unwanted commands between operations. A No Operation

Command is registered when CS is low with RAS, CAS , and WE held high at the rising

edge of the clock. A No Operation Command will not terminate a previous operation that is still

executing, such as a burst read or write cycle.

Deselect Command

The Deselect Command performs the same function as a No Operation Command. Deselect

Command occurs when CS is brought high, the RAS, CAS , and WE signals become don't

cares.

Clock Suspend Mode

During normal access mode, CKE must be held high enabling the clock. When CKE is registered low

while at least one of the banks is active, Clock Suspend Mode is entered. The Clock Suspend mode

deactivates the internal clock and suspends any clocked operation that was currently being executed.

There is a one clock delay between the registration of CKE low and the time at which the SDRAM

operation suspends. While in Clock Suspend mode, the SDRAM ignores any new commands that are

issued. The Clock Suspend mode is exited by bringing CKE high. There is a one clock cycle delay

from when CKE returns high to when Clock Suspend mode is exited.

Publication Release Date: July 30, 2002

- 11 -

Revision A5

W986432DH

8. TABLE OF OPERATING MODES

Fully synchronous operations are performed to latch the commands at the positive edges of CLK.

Table 3 shows the truth table for the operation commands.

Table 3. Truth Table (Note (1), (2))

DEVICE

STATE

COMMAND

Bank Active

CKEn-1 CKEn DQM BS0, 1 A10 A0

-A9

CS

RAS

CAS

WE

Idle

H

L

x

v

x

v

x

v

L

H

L

H

L

H

v

V

x

v

x

L

H

L

H

L

H

L

H

L

H

L

H

L

x

Bank Precharge

Precharge All

Write

Any

x

L

Active (3)

x

H

L

Write with Autoprecharge Active (3)

Read Active (3)

Read with Autoprecharge Active (3)

x

L

x

L

x

L

Mode Register Set

No-Operation

Idle

Any

x

L

x

H

x

H

x

Burst Stop

Active (4)

Any

x

Device Deselect

Auto-Refresh

x

Idle

H

L

H

x

L

H

x

Self-Refresh Entry

Idle

x

L

x

Idle

(S.R)

Self Refresh Exit

L

x

H

x

Clock suspend Mode

Entry

Active

H

L

x

H

L

x

H

L

x

X

H

Idle

Active (5)

Power Down Mode Entry

H

Clock Suspend Mode

Exit

Active

L

H

x

X

Any

(power

down)

L

H

x

H

L

x

X

H

Power Down Mode Exit

H

Data write/Output Enable

Active

H

x

L

x

Data Write/Output

Disable

H

Notes:

(1) v = valid, x = Don't care, L = Low Level, H = High Level

(2) CKEn signal is input leve l when commands are provided.

(3) These are state of bank designated by BS0, BS1 signals.

(4) Device state is full page burst operation.

(5) Power Down Mode can not be entered in the burst cycle.

When this command asserts in the burst cycle, device state is clock suspend mode.

- 12 -

W986432DH

9. SIMPLIFIED STATE DIAGRAM

Self

Refresh

Mode

Register

Set

MRS

REF

CBR

Refresh

IDLE

CKE

Power

Down

CKE

Active

Power

Down

ROW

ACTIVE

Write

Read

CKE

Read

WRITE

READ

WRITE

READ

SUSPEND

Write

CKE

WRITEA

SUSPEND

READA

SUSPEND

READA

WRITEA

POWER

ON

Precharge

Automatic sequence

Manual input

MRS = Mode Register Set

REF = Refresh

ACT = Active

PRE = Precharge

WRITEA = Write with Auto precharge

READA = Read with Auto precharge

Publication Release Date: July 30, 2002

Revision A5

- 13 -

W986432DH

10. DC CHARACTERISTICS

Absolute Maximum Rating

PARAMETER

Input, Column Output Voltage

Power Supply Voltage

SYM.

VIN, VOUT

VCC, VCCQ

TOPR

RATING

-0.3 - VCC +0.3

-0.3 - 4.6

0 - 70

UNIT

V

NOTES

1

V

Operating Temperature (-5/-6/-7/-7L)

Operating Temperature(6I)

Storage Temperature

°C

W

TOPR

-25 - 85

-55 - 150

260

TSTG

Soldering Temperature (10s)

Power Dissipation

TSOLDER

PD

1

Short Circuit Output Current

IOUT

50

mA

Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability

of the device.

11. RECOMMENDED DC OPERATING CONDITIONS

(TA = 0 to 70° C)

PARAMETER

Power Supply Voltage

SYM.

MIN.

TYP.

MAX.

UNIT NOTES

VCC

3.0

3.3

3.6

V

2

Supply voltage for W986432DH-7L

during self refresh mode

VCC

2.7

3.3

3.6

Power Supply Voltage (for I/O Buffer)

Input High Voltage

VCCQ

VIH

3.0

2.0

3.3

3.6

VCC +0.3

0.8

V

2

-

Input Low Voltage

VIL

-0.3

Note: VIH (max.) = VCC/VCCQ +1.2V for pulse width < 5 nS

VIL (min.) = VSS/VSSQ -1.2V for pulse width < 5 nS

12. CAPACITANCE

(VCC = 3.3V, TA = 25° C, f = 1 MHz)

PARAMETER

SYM.

MIN.

MAX.

UNIT

Input Capacitance

Ci1

2.5

4

pF

(A0 to A11, BS0, BS1, CS , RAS , CAS , WE , CKE)

Input Capacitance (CLK)

CCLK

Co

2.5

4

pF

6.5

5.5

Input/Output Capacitance (DQ0 - DQ15)

Input Capacitance DQM

Ci2

3.0

Note: These parameters are periodically sampled and not 100% tested

- 14 -

W986432DH

13. DC CHARACTERISTICS

(VCC = 3.3V ±0.3V, TA = 0°- 70°C for -5/-6/-7/-7L,TA = -25 to 85°C for -6I)

-5

-6/-6I

MAX.

-7/-7L

MAX.

PARAMETER

SYM.

UNIT

NOTES

MAX.

Operating Current

tCK = min., tRC = min.

1 bank operation

CKE = VIH

ICC1

110

90

80

3

Active precharge command

cycling without burst operation

Standby Current

ICC2

45

1

35

1

30

1

3

tCK = min., CS = VIH

VIH/L = VIH (min.)/VIL (max.)

CKE = VIL (Power

Down mode)

Bank: inactive state

Standby Current

ICC2P

CKE = VIH

ICC2S

8

CLK = VIL, CS = VIH

VIH/L = VIH (min.)/VIL (max.)

CKE = VIL (Power

Down mode)

BANK: inactive state

ICC2PS

ICC3

1

70

5

1

60

5

1

55

5

mA

No Operating Current

CKE = VIH

tCK = min., CS = VIH (min.)

CKE = VIL (Power

Down mode)

BANK: active state (4 banks)

ICC3P

ICC4

Burst Operating Current

Read/Write command cycling

Auto Refresh Current

Auto refresh command cycling

Self Refresh Current

CKE = 0.2V

(tCK = min.)

190

165

145

3, 4

3

(tCK = min.)

ICC5

125

120

110

Standard (-5/-6/-7)

Low Power(-6I/,-7L)

ICC6

1

-

1

ICC6L

400

mA

Self refresh mode

PARAMETER

Input Leakage Current

SYMBOL

MIN.

MAX.

UNIT

NOTES

II(L)

-5

2.4

-

5

mA

(0V £ VIN £ VCC, all other pins not under test = 0V)

Output Leakage Current

(Output disable, 0V £ VOUT £ VCCQ)

VO(L)

VOH

5

-

mA

V

²

LVTTL Output H Level Voltage

(IOUT = -2 mA)

"

²

LVTTL Output L Level Voltage

(IOUT = 2 mA)

VOL

0.4

V

Publication Release Date: July 30, 2002

Revision A5

- 15 -

W986432DH

14. AC CHARACTERISTICS

(VCC = 3.3V ±0.3V, VSS = 0V, TA = 0 to 70° C for -5/-6/-7/-7L,TA = -40 to 85° C for -6I) (Notes: 5, 6.)

-5

MIN. MAX.

54

-6/-6I

MAX.

-7/-7L

PARAMETER

SYM.

UNIT

NOTE

MIN.

60

MIN.

MAX.

Ref/Active to Ref/Active Command Period

Active to precharge Command Period

Active to Read/Write Command Delay Time

tRC

tRAS

tRCD

65

45

20

nS

40

14

100000

42

100000

18

Read/Write(a) to Read/Write(b) Command

Period

tCCD

1

Cycle

nS

Precharge to Active(b) Command Period

Active(a) to Active(b) Command Period

tRP

14

10

7

18

12

7.5

6

20

14

8

tRRD

Wreite Recovery Time

CL* = 2

CL* = 3

CL* = 2

CL* = 3

tWR

tCK

5

7

CLK Cycle Time

7

1000

7.5

6

1000

8

1000

5

7

CLK High Level

tCH

tCL

2

CLK Low Level

2

Access Time from CLK

CL* = 2

CL* = 3

5.5

4.5

5.5

5

6

tAC

5.5

Output Data Hold Time

tOH

tHZ

1.5

0

2

Output Data High Impedance Time

Output Data Low Impedance Time

Power Down Mode Entry Time

Transition Time of CLK (Rise and Fall)

Data-in-Set-up Time

5

6

7

tLZ

0

tSB

0

5

0

6

0

7

tT

0.5

1.5.

1

10

0.5

1.5

1

10

0.5

1.5

1

10

tDS

Data-in Hold Time

tDH

Address Set-up Time

tAS

1.5

1

1.5

1

1.5

1

Address Hold Time

tAH

CKE Set-up Time

tCKS

tCKH

tCMS

tCMH

tREF

tRSC

1.5

1

1.5

1

1.5

1

CKE Hold Time

Command Set-up Time

Command Hold Time

1.5

1

1.5

1

1.5

1

Refresh Time

64

mS

nS

Mode Register Set Cycle Time

10

12

14

Notes:

1. Operation exceeds "ABSOLUTE MAXIMUM RATING" may cause permanent damage to the devices.

2. All voltages are referenced to VSS.

3. These parameters depend on the cycle rate and listed values are measured at a cycle rate with the minimum values of tCK

and tRC.

4. These parameters depend on the output loading conditions. Specified values are obtained with output open.

- 16 -

W986432DH

5. Power up Sequence

(1) Power up must be performed in the following sequence.

(2) Power must be applied to VCC and VCCQ (simultaneously) while all input signals are held in the "NOP" state. The CLK

signals must be started at the same time.

(3) After power-up a pause of at least 200 mS is required. It is required that DQM and CKE signals then be held "high"

(VCC levels) to ensure that the DQ output is impedance.

(4) All banks must be precharged.

(5) The Mode Register Set command must be asserted to initialize the Mode Register.

(6) A minimum of eight Auto Refresh dummy cycles is required to stabilize the internal circuitry of the device.

6. AC Testing Conditions

PARAMETER

Output Reference Level

CONDITIONS

1.4V

Output Load

See diagram below

2.4V/0.4V

1 nS

Input Signal Levels (VIH/VIL)

Transition Time (Rise and Fall) of Input Signal

Input Reference Level

1.4V

1.4 V

50 ohms

30pF

output

Z = 50 ohms

AC TEST LOAD

1. Transition times are measured between VIH and VIL.

2. tHZ defines the time at which the outputs achieve the open circuit condition and is not referenced to output level.

3. These parameters account for the number of clock cycles and depend on the operating frequency of the clock,

as follows the number of clock cycles = specified value of timing/ clock period

(count fractions as whole number)

(1) tCH is the pulse width of CLK measured from the positive edge to the negative edge referenced to VIH (min.).

tCL is the pulse width of CLK measured from the negative edge to the positive edge referenced to VIL (max.).

Publication Release Date: July 30, 2002

- 17 -

Revision A5

W986432DH

(2) A.C Latency Characteristics

CKE to clock disable (CKE Latency)

1

2

0

Cycle

DQM to output to HI-Z (Read DQM Latency)

DQM to output to HI-Z (Write DQM Latency)

Write command to input data (Write Data Latency)

0

CS to Command input ( CS Latency)

Precharge to DQ Hi-Z Lead time

CL = 2

CL = 3

CL = 2

CL = 3

CL = 2

CL = 3

CL = 2

CL = 3

CL = 2

CL = 3

CL = 2

CL = 3

2

3

1

2

3

1

2

Precharge to Last Valid data out

Bust Stop Command to DQ Hi-Z Lead time

Bust Stop Command to Last Valid Data out

BL + tRP

Cycle + nS

Read with Auto-precharge Command to Active/Ref

Command

Write with Auto-precharge Command to Active/Ref

Command

- 18 -

W986432DH

15. TIMING WAVEFORMS

Command Input Timing

t

CL

t

CH

t

CK

VIH

CLK

CS

V^IL

tT

t

CMS

tCMH

t

CMH

tCMS

t

CMH

RAS

CAS

WE

t

CMS

t

CMH

tAS

tAH

A0-A10

BS0, 1

tCKS

t

CKH

tCKH

t

CKS

tCKS

tCKH

CKE

Publication Release Date: July 30, 2002

Revision A5

- 19 -

W986432DH

Timing Waveforms, continued

Read Timing

Read CAS Latency

CLK

CS

RAS

CAS

WE

A0-A10

BS0, 1

t^AC

tAC

t^HZ

t^OH

tOH

tLZ

Valid

Data-Out

Valid

Data-Out

DQ

Read Command

Burst Length

- 20 -

W986432DH

Timing Waveforms, continued

Control Timing of Input Data

(Word Mask)

CLK

t

CMS

t

CMH

t

CMH

tCMS

DQM0

DQM1

t

CMH

t

CMS

t

CMH

t

CMS

t

DS

t

DH

DS

DH

DS

DH

DS

Valid

Data-in

Valid

Data-in

Valid

Data-in

Valid

Data-in

DQ0 -DQ7

DQ8-DQ15

t

DS

t

DH

t

DS

t

DH

t

DS

t

DH

t

DS

t

DH

Valid

Data-in

Valid

Data-in

Valid

Data-in

Valid

Data-in

t

DH

t

DH

t

tDH

t

DS

t

DH

DS

t

DH

DS

Valid

Data-in

Valid

Data-in

Valid

Data-in

Valid

Data-in

Valid

Data-in

DQ16 -DQ23

DQ24-DQ31

t

DH

t

DH

t

DS

t

DH

DS

tDH

t

DH

Valid

Data-in

Valid

Data-in

Valid

Data-in

Valid

Data-in

Valid

Data-in

*DQM2,3="L"

(Clock Mask)

CLK

t

CKH

t

CKS

t

CKH

tCKS

CKE

t

DS

t

DH

t

DS

t

DH

t

DS

t

DH

t

DS

t

DH

Valid

Data-in

Valid

Data-in

Valid

Data-in

Valid

Data-in

DQ0 -DQ7

DQ8 -DQ15

DQ16 -DQ23

DQ24 -DQ31

t

DH

t

DH

t

DH

t

DH

Valid

Data-in

Valid

Data-in

Valid

Data-in

Valid

Data-in

t

DS

t

DH

DS

t

DH

t

DS

t

DH

t

DS

t

DH

Valid

Data-in

Valid

Data-in

Valid

Data-in

Valid

Data-in

t

DH

t

DH

t

DH

t

DH

Valid

Data-in

Valid

Data-in

Valid

Data-in

Valid

Data-in

Publication Release Date: July 30, 2002

Revision A5

- 21 -

W986432DH

Timing Waveforms, continued

Control Timing of Output Data

(Output Enable)

CLK

t

CMH

t

CMS

t

CMH

t

CMS

DQM0

DQM1

t

CMS

tCMH

tCMS

tCMH

t

AC

t

AC

OH

t

HZ

OH

t

AC

t

AC

tOH

t

tLZ

tOH

OPEN

Valid

Data-Out

Valid

Data-Out

Valid

Data-Out

DQ0 -DQ7

DQ8 -DQ15

DQ16 -DQ23

DQ24 -DQ31

t

AC

t

AC

t

AC

tHZ

t

AC

t

OH

t

OH

t

OH

t

OH

t

LZ

Valid

Data-Out

OPEN

Valid

Data-Out

Valid

Data-Out

t

AC

t

AC

t

HZ

t

AC

t

OH

t

OH

t

OH

t

LZ

t

OH

Valid

Data-Out

Valid

Data-Out

Valid

Data-Out

Valid

Data-Out

t

AC

t

OH

t

HZ

AC

t

AC

tOH

t

OH

t

OH

tOH

Valid

Data-Out

Valid

Data-Out

Valid

Data-Out

Valid

Data-Out

*DQM2,3="L"

(Clock Mask)

CLK

t

CKH

t

CKS

t

CKH

t

CKS

CKE

t

AC

t

AC

t

AC

t

AC

t

OH

t

OH

t

OH

t

OH

Valid

Data-Out

Valid

Data-Out

Valid

Data-Out

DQ0 -DQ7

t

AC

t

AC

t

OH

tOH

t

OH

t

OH

Valid

Data-Out

Valid

Data-Out

Valid

Data-Out

DQ8 -DQ15

t

AC

t

AC

t

AC

t

AC

t

OH

t

OH

t

OH

tOH

Valid

Data-Out

Valid

Data-Out

Valid

Data-Out

DQ16 -DQ23

tAC

t

AC

t

AC

t

OH

tOH

Valid

Data-Out

Valid

Data-Out

Valid

Data-Out

DQ24 -DQ31

- 22 -

W986432DH

Timing Waveforms, continued

Mode Register Set Cycle

tRSC

CLK

tCMS

t^CMH

tCMH

CS

RAS

CAS

WE

tCMS

tCMH

t^AS

t_AH

A0-A10

BS0,1

Register

set data

A0

A2 A01 A0

BurstAL0ength

A0

A1

A2

SeqAue0ntial

InteArl0eave

Burst Length

0

1

A00

A10

A00

A0

0

A10

0

1

0

1

0

1

0

1

A10

A20

A40

A80

A20

A40

A80

A3 Addressing Mode

A4

ResAe0rved

FullAP0age

ResAe0rved

A5

A6

CAS Latency

A30

A00

A10

AddressAin0g Mode

SeqAue0ntial

InteArl0eave

A07 "0" (Test Mode)

A8 "0"

A09

Reserved

A6 A05 A4

CAS ALa0tency

ResAe0rved

2

A30

Reserved

0

1

A00

A10

A00

0

1

0

1

0

WriteA0Mode

A10 "0"

"0"

AA101

ResAe0rved

BS0 "0"

BAS01 "0"

A90

A00

A10

Single Write Mode

Burst read aAn0d Burst write

Burst read aAn0d single write

Publication Release Date: July 30, 2002

Revision A5

- 23 -

W986432DH

16. OPERATING TIMING EXAMPLE

Interleaved Bank Read (Burst Length = 4, CAS Latency = 3)

(CLK = 100 MHz)

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

0

1

2

3

4

5

CLK

CS

t

RC

tRC

t

RC

tRC

RAS

CAS

WE

t

RAS

t

RP

t

RAS

RP

tRP

t

RAS

t

tRAS

BS0

BS1

t

RCD

t

RCD

t

RCD

tRCD

RAa

RBb

RAc

RBd

A10

RAe

CAw

CBx

CAy

CBz

A0-A9

DQM

CKE

DQ

t

AC

t

AC

tAC

cy2

bx1

bx3

aw0

aw2 aw3

bx0

bx2

cy1

cy3

aw1

cy0

tRRD

t

RRD

t

RRD

tRRD

Precharge

Read

Active

Read

Precharge

Bank #0

Bank #1

Bank #2

Bank #3

Read

Precharge

Read

Active

Idle

- 24 -

W986432DH

Operating Timing Example, continued

Interleaved Bank Read (Burst Length = 4, CAS Latency = 3, Autoprecharge)

(CLK = 100 MHz)

11

12

13

14

15

16

17

18

19

20

21

22

23

1

2

3

4

5

6

7

8

9

10

0

CLK

CS

tRC

t^RC

RAS

CAS

tRAS

tRP

tRAS

t^RP

tRP

t^RAS

WE

BS0

BS1

A10

t^RCD

tRCD

RAe

RBd

RAa

RBb

RAc

A0-A9

DQM

CKE

RAa

CAw

CAy

CBz

RAe

CBx

RBb

RAc

RBd

tAC

cy3

aw0 aw1 aw2

aw3

bx0 bx1

bx2 bx3

cy0

cy1 cy2

dz0

DQ

tRRD

t^RRD

Read

Active

AP*

Read

Active

AP*

Active

Bank #0

Bank #1

Bank #2

Bank #3

Read

Active

AP*

Idle

* AP is the internal precharge start timing

Publication Release Date: July 30, 2002

Revision A5

- 25 -

W986432DH

Operating Timing Example, continued

Interleaved Bank Read (Burst Length = 8, CAS Latency = 3)

(CLK = 100 MHz)

8

9

10 11 12 13 14 15 16 17 18

1

2

3

4

5

6

7

19 20 21 22 23

0

CLK

CS

tRC

RAS

CAS

tRAS

tRP

tRAS

tRP

WE

BS0

BS1

A10

tRCD

RAa

RAc

RBb

CAx

CBy

CAz

A0-A9

DQM

CKE

DQ

tAC

t^AC

tAC

ax0 ax1

ax2

ax3

ax4

ax5 ax6

by0

by1

by4 by5

by6

by7

CZ0

tRRD

Read

Active

Idle

Precharge

Active

Read

Precharge

Bank #0

Bank #1

Bank #2

Bank #3

Precharge

Active

Read

- 26 -

W986432DH

Operating Timing Example, continued

Interleaved Bank Read (Burst Length = 8, CAS Latency = 3, Autoprecharge)

(CLK = 100 MHz)

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20 21 22 23

0

CLK

CS

tRC

RAS

tRAS

tRP

tRAS

CAS

WE

BS0

BS1

tRCD

A10

RBb

RAc

RAa

A0-A9

DQM

CAz

CAx

RAc

RBb

CBy

CKE

DQ

tCAC

ax3

ax4

ax0

ax2

ax5 ax6

ax7

by0

by1

by4

by5

by6

ax1

CZ0

tRRD

AP*

Read

Active

Bank #0 Active

Bank #1

Read

Active

Read

AP*

Bank #2

Idle

Bank #3

* AP is the internal precharge start timing

Publication Release Date: July 30, 2002

Revision A5

- 27 -

W986432DH

Operating Timing Example, continued

Interleaved Bank Write (Burst Length = 8)

(CLK = 100 MHz)

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20 21 22 23

1

2

3

4

5

0

CLK

CS

tRC

RAS

CAS

tRAS

tRP

tRAS

tRCD

WE

BS0

BS1

RBb

RAc

RAa

A10

CAx

RBb

CBy

RAc

CAz

A0-A9

DQM

CKE

DQ

ax0 ax1

ax4

ax5

ax6

ax7

by0

by1

by2

by3

by4

by5

by6

by7

CZ0

CZ1

CZ2

t^RRD

tRRD

Active

Write

Precharge

Active

Write

Bank #0

Bank #1

Bank #2

Bank #3

Active

Write

Precharge

Idle

- 28 -

W986432DH

Operating Timing Example, continued

Interleaved Bank Write (Burst Length = 8, Autoprecharge)

(CLK = 100 MHz)

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20 21 22 23

CLK

CS

tRC

RAS

CAS

tRAS

tRP

tRAS

WE

BS0

BS1

tRCD

RAa

RBb

RAb

A10

CAx

CBy

CAz

RAc

A0-A9

DQM

CKE

DQ

ax4

by2

by5

ax0

ax1

ax5

ax6

ax7

by0 by1

by3

by4

by6

by7 CZ0

CZ1

CZ2

tRRD

AP*

Write

AP*

Active

Write

Bank #0

Bank #1

Bank #2

Bank #3

Active

Write

Idle

* AP is the internal precharge start timing

Publication Release Date: July 30, 2002

Revision A5

- 29 -

W986432DH

Operating Timing Example, continued

Page Mode Read (Burst Length = 4, CAS Latency = 3)

(CLK = 100 MHz)

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20 21 22 23

CLK

CS

tCCD

tRAS

RAS

CAS

WE

BS0

BS1

t^RCD

RAa

RBb

A10

A0-A9

DQM

CKE

CBx

CAy

CAm

CBz

CAI

tAC

am1

am2 bz0

bz1

bz2

bz3

a0

a1

a3

bx0

Ay0

Ay1

Ay2

am0

a2

bx1

DQ

tRRD

Read

Bank #0 Active

Bank #1

Read

Precharge

AP*

Active

Read

Bank #2

Idle

Bank #3

* AP is the internal precharge start timing

- 30 -

W986432DH

Operating Timing Example, continued

Page Mode Read/Write (Burst Length = 8, CAS Latency = 3)

(CLK = 100 MHz)

6

7

8

11

12

13

16

17

18

1

2

3

5

9

10

14

15

19

21

0

4

20

22

23

CLK

CS

tRAS

RAS

CAS

WE

BS0

BS1

tRCD

RAa

A10

CAx

A0-A9

CAy

DQM

CKE

tAC

tWR

ax5

ay1

ax0

ax1

ax3

ay0

ay2

ay4

ax2

ax4

ay3

DQ

Q

D

Bank #0 Active

Bank #1

Read

Write

Precharge

Bank #2

Idle

Bank #3

Publication Release Date: July 30, 2002

Revision A5

- 31 -

W986432DH

Operating Timing Example, continued

Autoprecharge Read (Burst Length = 4, CAS Latency = 3)

(CLK = 100 MHz)

1

2

3

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

21

0

4

20

22

23

CLK

CS

t

RC

RAS

tRAS

tRP

tRAS

CAS

WE

BS0

BS1

A10

t

RCD

tRCD

RAa

RAb

RAa

CAw

CAx

RAb

A0-A9

DQM

CKE

t

AC

tAC

aw0

aw1 aw2 aw3

bx1

bx2

bx3

bx0

DQ

Bank #0

Bank #1

Bank #2

Bank #3

AP*

Active

Idle

Read

Active

Read

AP*

* AP is the internal precharge start timing

- 32 -

W986432DH

Operating Timing Example, continued

Autoprecharge Write (Burst Length = 4)

(CLK = 100 MHz)

1

2

3

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

21

0

4

20

22

23

CLK

CS

t

RC

t

RC

RAS

CAS

t

RAS

t

RP

t

RAS

t

RP

WE

BS0

BS1

tRCD

t

RCD

RAc

RAa

RAb

A10

A0-A9

DQM

CKE

CAw

RAb

CAx

RAc

aw0 aw1 aw2 aw3

bx0

bx1

bx3

bx2

DQ

Active

Idle

Bank #0

Bank #1

Bank #2

Bank #3

Write

Active

Write

Active

AP*

* AP is the internal precharge start timing

Publication Release Date: July 30, 2002

Revision A5

- 33 -

W986432DH

Operating Timing Example, continued

Autorefresh Cycle

(CLK = 100 MHz)

1

2

3

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19

21

0

4

20

22 23

CLK

CS

tRP

tRC

RAS

CAS

WE

BS0,1

A10

A0-A9

DQM

CKE

DQ

All Banks

Prechage

Auto

Refresh

Auto Refresh (Arbitrary Cycle)

- 34 -

W986432DH

Operating Timing Example, continued

Self-refresh Cycle

(CLK = 100 MHz)

6

7

8

11

12

13

16

17

18

1

2

3

5

9

10

14

15

19

21

0

4

20

22

23

CLK

CS

t

RP

RAS

CAS

WE

BS0,1

A10

A0-A9

DQM

tCKS

t

CKS

tSB

CKE

DQ

tCKS

tRC

Self Refresh Cycle

No Operation Cycle

All Banks

Precharge

Self Refresh

Entry

Arbitrary Cycle

Publication Release Date: July 30, 2002

Revision A5

- 35 -

W986432DH

Operating Timing Example, continued

Bust Read and Single Write (Burst Length = 4, CAS Latency = 3)

(CLK = 100 MHz)

6

7

8

11 12 13

16 17 18

1

2

3

5

9

10

14 15

19

21

0

4

20

22 23

CLK

CS

RAS

CAS

tRCD

WE

BS0

BS1

A10

RBa

CBz

A0-A9

RBa

CBv

CBw

CBx CBy

DQM

CKE

t^AC

DQ

av0

av1

av3

aw0

ax0

ay0

az1

az2

az3

az0

av2

Q

D

Q

Read

Active

Idle

Single Write

Read

Bank #0

Bank #1

Bank #2

Bank #3

- 36 -

W986432DH

Operating Timing Example, continued

Power-down Mode

(CLK = 100 MHz)

6

7

8

11

12

13

16

17

18

1

2

3

5

9

10

14

15

19

21

0

4

20

22

23

CLK

CS

RAS

CAS

WE

BS

RAa

A10

A0-A9

DQM

CAa

RAa

CAx

t

SB

t

SB

CKE

DQ

tCKS

t

CKS

tCKS

t

CKS

ax0

ax1

ax2

ax3

Active

NOP

Precharge

NOPActive

Read

Precharge Standby

Power Down mode

Active Standby

Power Down mode

Note: The PowerDown Mode is entered by asserting CKE "low".

All Input/Output buffers (except CKE buffers) are turned off in the PowerDown mode.

When CKE goes high, command input must be No operation at next CLK rising edge.

Publication Release Date: July 30, 2002

Revision A5

- 37 -

W986432DH

Operating Timing Example, continued

Auto-precharge Timing (Write Cycle)

0

1

2

3

4

5

6

7

8

9

10

11

(1) CAS

Latency = 2

( a ) burst length = 1

Command

Write

D0

AP

Act

t_WR

t_RP

DQ

( b ) burst length = 2

Command

Write

D0

AP

Act

AP

t_WR

t_RP

DQ

( c ) burst length = 4

Command

D1

Write

D0

Act

D6

t_WR

t_RP

DQ

D2

D3

( d ) burst length = 8

Write

D0

AP

Act

Command

t_WR

t_RP

DQ

D1

AP

D4

D5

D7

(2) CAS

Latency = 3

Write

D0

Act

( a ) burst length = 1

Command

t_WR

t_RP

DQ

( b ) burst length = 2

Command

Write

D0

AP

Act

t_WR

t_RP

DQ

( c ) burst length = 4

Command

D1

Write

D0

AP

Act

D7

t_WR

t_RP

DQ

D2

D3

( d ) burst length = 8

Command

DQ

AP

Act

Write

D0

t_WR

t_RP

D5

D6

D4

Note:

Write

represents the Write with Auto precharge comm

represents the start of internal prechargi

represents the Bank Activate comma

AP

Act

When the Auto precharge command is asserted, the period from B

command to the start of internal precgarging must be at least tR

- 38 -

W986432DH

Operating Timing Example, continued

Auto-precharge Timing (Read Cycle)

0

1

2

3

4

5

6

7

8

9

10

11

(1) CAS

Latency=2

( a ) burst length = 1

Command

Read

AP

Act

t

RP

DQ

Q0

( b ) burst length = 2

Command

Read

AP

Q0

Act

t

RP

DQ

Q1

( c ) burst length = 4

Command

AP

Q2

Act

Q4

t

RP

DQ

Q0

Q1

Q3

( d ) burst length = 8

Command

AP

Q6

Act

t

RP

DQ

Q2

Act

Q3

Q5

Q7

(2) CAS

Latency=3

( a ) burst length = 1

Command

Read

AP

t

RP

DQ

Q0

( b ) burst length = 2

Command

AP

Act

tRP

DQ

Q1

AP

Q1

( c ) burst length = 4

Command

Act

Q4

t

RP

DQ

Q2

Q3

( d ) burst length = 8

Command

AP

Q5

Act

t

RP

DQ

Q1

Q6

Q7

Note:

Read

AP

Act

represents the Read with Auto precharge command.

represents the start of internal precharging.

represents the Bank Activate command.

When the Auto precharge command is asserted, the period from Bank Activate command to

the start of internal precgarging must be at least Rt AS (min).

Publication Release Date: July 30, 2002

Revision A5

- 39 -

W986432DH

Operating Timing Example, continued

Timing Chart of Read to Write Cycle

In the case of Burst Length = 4

1

2

3

4

5

6

7

8

9

10

11

0

(1) CAS Latency=2

( a ) Command

Read

Write

DQM

DQ

D0

D1

D2

D3

( b ) Command

Read

Write

DQM

DQ

D0

D1

D2

D3

(2) CAS Latency=3

( a ) Command

Read

Write

D0

DQM

D1

DQ

( b ) Command

Write

DQM

DQ

D0

D1

D2

D3

Note: The Output data must be masked by DQM to avoid I/O conflict.

- 40 -

W986432DH

Operating Timing Example, continued

Timing Chart of Write to Read Cycle

In the case of Burst Length = 4

1

2

3

4

5

6

7

8

9

10

11

0

(1) CAS Latency = 2

( a ) Command

DQM

Write

Read

DQ

D0

Q0

Q1

Q0

Q2

Q1

Q3

Q2

( b ) Command

Read

Write

DQM

DQ

D0

D1

Q3

(2) CAS Latency = 3

( a ) Command

Read

Write

DQM

DQ

D0

Q0

Q1

Q0

Q2

Q1

Q3

Q2

( b ) Command

DQM

Write

Read

D0

D1

Q3

DQ

Publication Release Date: July 30, 2002

Revision A5

- 41 -

W986432DH

Operating Timing Example, continued

Timing Chart of Burst Stop Cycle (Burst Stop Command)

0

1

2

3

4

5

6

7

8

9

10

11

(3) Read cycle

( a ) CAS latency =2

Read

BST

Command

DQ

Q4

Q3

Q0

Q1

Q0

Q2

Q1

Q3

BST

Q2

( b ) CAS latency = 3

Command

Read

DQ

Q4

(2) Write cycle

BST

Write

D0

Command

DQ

D1

D2

D3

D4

Note:

BST

represents the Burst stop command

- 42 -

W986432DH

Operating Timing Example, continued

Timing Chart of Burst Stop Cycle (Precharge Command)

In the case of Burst Lenght = 8

0

1

2

3

4

5

6

7

8

9

10

11

(1) Read cycle

( a )CAS latency =2

Commad

Read

PRCG

DQ

Q4

Q3

Q0

Q1

Q0

Q2

Q1

Q3

( b )CAS latency = 3

Commad

PRCG

Read

Q4

DQ

Q2

(2) Write cycle

( a ) CAS latency =2

PRCG

Commad

Write

t

WR

DQM

DQ

D4

D0

D1

D2

D3

( b ) CAS latency = 3

PRCG

WR

Commad

Write

DQM

DQ

D0

D1

D2

PRCG

Note:

represents the Precharge command

Publication Release Date: July 30, 2002

Revision A5

- 43 -

W986432DH

Operating Timing Example, continued

CKE/DQM Input Timing (Write Cycle)

1

CLK cycle No.

2

3

4

5

7

6

External

CLK

Internal

CKE

DQM

DQ

D1

D2

D3

D5

D6

DQM MASK

CKE MASK

( 1 )

CLK cycle No.

External

2

3

4

5

7

1

6

CLK

Internal

CKE

DQM

DQ

D1

D2

D3

D6

D5

DQM MASK

( 2 )

CKE MASK

1

2

3

4

5

6

7

CLK cycle No.

External

CLK

Internal

CKE

DQM

DQ

D1

D2

D3

D4

D5

D6

CKE MASK

( 3 )

- 44 -

W986432DH

Operating Timing Example, continued

CKE/DQM Input Timing (Read Cycle)

1

CLK cycle No.

6

2

3

4

5

7

External

Internal

CLK

CKE

DQM

DQ

Q6

Q1

Q2

Q3

Q4

Open

( 1 )

1

2

3

4

5

7

CLK cycle No.

6

External

Internal

CLK

CKE

DQM

DQ

Q6

Q3

Q1

1

Q2

Q4

Open

( 2 )

CLK cycle No.

2

3

4

5

6

7

External

CLK

Internal

CKE

DQM

DQ

Q6

Q1

Q4

Q5

Q3

Q2

( 3 )

Publication Release Date: July 30, 2002

Revision A5

- 45 -

W986432DH

Operating Timing Example, continued

Self Refresh/Power Down Mode Exit Timing

Asynchronous Control

CKS (min.) + tCK (min.)

Input Buffer turn on time (Power down mode exit time) is specified by t

A ) tCK < tCKS (min.) + tCK (min.)

tCK

CLK

CKE

t

CKS(min)+tCK(min)

Command

NOP

Input Buffer Enable

B) tCK >= tCKS (min.) + tCK (min.)

tCK

CLK

CKE

t

^CKS(min)+t^CK(min)

Command

Input Buffer Enable

Note:

All Input Buffer (Include CLK Buffer) are turned off in the Power Down mode

and Self Refresh mode

NOP

Represents the No-Operation command

Command

Represents one command

- 46 -

W986432DH

17. PACKAGE DIMENSION

86L TSOP (II)-400 mil

86

44

H _E

E

1

43

e

b

C

D

q

L

A2

A1

A

L1

ZD

Y

SEATING PLANE

Controlling Dimension: Millimeters

DIMENSION

(MM)

DIMENSION

(INCH)

SYM.

MIN.

NOM.

MAX.

MIN.

MAX.

NOM.

1.20

0.15

0.047

0.006

A

A1

0.05

0.002

1.00

0.039

A2

b

0.17

0.12

0.27

0.21

0.007

0.005

0.011

0.008

0.905

0.404

c

22.12

10.06

11.56

22.22

10.16

11.76

0.50

22.62

10.26

11.96

0.871

0.396

0.455

0.875

0.400

0.463

0.020

0.032

D

E

0.471

0.024

0.004

H _E

e

0.40

0.50

0.60

0.10

0.016

L

0.80

L1

Y

ZD

0.024

0.61

Publication Release Date: July 30, 2002

Revision A5

- 47 -

W986432DH

18. VERSION HISTORY

VERSION

DATE

PAGE

DESCRIPTION

Preliminary datasheet

A3

A4

A5

Auguest 2001

Apr. 11, 2002

July 30, 2002

-

12

5

Change CI/O capacitance value

Change CLK pin number

Headquarters

Winbond Electronics Corporation America Winbond Electronics (Shanghai) Ltd.

27F, 2299 Yan An W. Rd. Shanghai,

2727 North First Street, San Jose,

No. 4, Creation Rd. III,

Science-Based Industrial Park,

Hsinchu, Taiwan

TEL: 886-3-5770066

FAX: 886-3-5665577

200336 China

CA 95134, U.S.A.

TEL: 1-408-9436666

FAX: 1-408-5441798

TEL: 86-21-62365999

FAX: 86-21-62365998

http://www.winbond.com.tw/

Taipei Office

Winbond Electronics Corporation Japan

7F Daini-ueno BLDG, 3-7-18

Shinyokohama Kohoku-ku,

Yokohama, 222-0033

Winbond Electronics (H.K.) Ltd.

Unit 9-15, 22F, Millennium City,

No. 378 Kwun Tong Rd.,

Kowloon, Hong Kong

9F, No.480, Rueiguang Rd.,

Neihu Chiu, Taipei, 114,

Taiwan, R.O.C.

TEL: 886-2-8177-7168

FAX: 886-2-8751-3579

TEL: 81-45-4781881

FAX: 81-45-4781800

TEL: 852-27513100

FAX: 852-27552064

Please note that all data and specifications are subject to change without notice.

All the trade marks of products and companies mentioned in this data sheet belong to their respective owners.

- 48 -

型号:	W986432DH-6
是否Rohs认证：	不符合
生命周期：	Obsolete
零件包装代码：	TSOP2
包装说明：	TSSOP, TSSOP86,.46,20
针数：	86
Reach Compliance Code：	not_compliant
ECCN代码：	EAR99
HTS代码：	8542.32.00.02
风险等级：	5.3
访问模式：	FOUR BANK PAGE BURST
最长访问时间：	5 ns
其他特性：	AUTO/SELF REFRESH
最大时钟频率 (fCLK)：	166 MHz
I/O 类型：	COMMON
交错的突发长度：	1,2,4,8
JESD-30 代码：	R-PDSO-G86
长度：	22.22 mm
内存密度：	67108864 bit
内存集成电路类型：	SYNCHRONOUS DRAM
内存宽度：	32
功能数量：	1
端口数量：	1
端子数量：	86
字数：	2097152 words
字数代码：	2000000
工作模式：	SYNCHRONOUS
最高工作温度：	70 °C
最低工作温度：
组织：	2MX32
输出特性：	3-STATE
封装主体材料：	PLASTIC/EPOXY
封装代码：	TSSOP
封装等效代码：	TSSOP86,.46,20
封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：	NOT SPECIFIED
电源：	3.3 V
认证状态：	Not Qualified
刷新周期：	4096
座面最大高度：	1.2 mm
自我刷新：	YES
连续突发长度：	1,2,4,8,FP
最大待机电流：	0.001 A
子类别：	DRAMs
最大压摆率：	0.165 mA
最大供电电压 (Vsup)：	3.6 V
最小供电电压 (Vsup)：	3 V
标称供电电压 (Vsup)：	3.3 V
表面贴装：	YES
技术：	CMOS
温度等级：	COMMERCIAL
端子形式：	GULL WING
端子节距：	0.5 mm
端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	10.16 mm
Base Number Matches：	1

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