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产品型号WJCE6355的概述

芯片WJCE6355的概述 WJCE6355是一款专为无线通信应用设计的高集成度单芯片。该芯片主要用于Wi-Fi和蓝牙等无线协议的实施,广泛应用于智能家居设备、可穿戴技术、工业控制以及IoT领域。WJCE6355以其低功耗、高性能和支持多种通信协议的特点,使得设计工程师在开发新产品时能更加灵活地选择方案。 WJCE6355采用了先进的制造工艺,集成了数字信号处理模块(DSP)、射频单元(RF)以及基带处理器,能够高效地处理各种无线数据传输任务。这款芯片支持多种数据传输模式,包括点对点链路和网状网络,使用户能够在各种应用场景中获得更好的性能。 芯片WJCE6355的详细参数 WJCE6355的详细参数如下: - 工作电压: 3.0V至3.6V - 工作温度范围: -40°C至85°C - 功耗: 待机功耗...

产品型号WJCE6355882211的Datasheet PDF文件预览

CE6355  
Nordig Unified DVB-T COFDM Terrestrial  
Demodulator for  
PC-TV and hand-held Digital TV (DTV)  
Data Sheet  
Document no. D55755-002  
November 2006  
Features  
Compliant with ETSI 300 744 DVB-T, Nordig-Unified  
1.0.2 and DTG performance specifications.  
High performance with fast fully blind acquisition and  
tracking capability.  
Low power consumption: less than 0.32 W, and  
eco-friendly standby and sleep modes.  
Digital filtering of adjacent channels.  
Single 8 MHz SAW filter for 6, 7 & 8 MHz OFDM.  
Superior single frequency network performance.  
Fast AGC to track out signal fades.  
Good Doppler tracking capability.  
Enhanced frequency capture range to include triple  
offsets.  
External 4 MHz clock or single low-cost 20.48 MHz  
crystal, tolerance up to +/-200 ppm.  
Automatic mode (2 K/8 K), guard and spectral inversion  
detection.  
Ordering Information  
WJCE6355 882211  
64 Pin LQFP* Trays  
WJCE6355 S L9G7 882212 64 Pin LQFP* Tape and Reel  
* Pb Free Matte Tin (RoHS compliant)  
Working temperature range: -40°C to +85°C  
A high performance 10 bit on-chip ADC is used to sample the  
44 or 36 MHz IF analog signal. Advanced digital filtering of  
the upper and lower channel enables a single 8 MHz channel  
SAW filter to be used for 6, 7 and 8 MHz OFDM signal  
reception. All sampling and other internal clocks are derived  
from a single 20.48 MHz crystal or a 4 MHz clock input, the  
tolerance of which may be relaxed as much as 200 ppm.  
The CE6355 has a wide frequency capture range able to  
automatically compensate for the combined offset intro-  
duced by the tuner xtal and broadcaster triple frequency  
offsets.  
Very low driver software overhead due to on-chip  
state-machine control.  
Novel RF level detect facility via a separate ADC.  
Pre and post Viterbi-decoder bit error rates, and  
uncorrectable block count.  
An on-chip state machine controls all acquisition and tracking  
operations of the CE6355 as well as controlling the tuner via  
a 2-wire bus. Any frequency range can be automatically  
scanned for digital TV channels. This mechanism ensures  
minimal interaction, maximum flexibility and fast acquisition  
- very low software overhead.  
Applications  
Digital terrestrial set-top boxes  
Integrated digital televisions  
Personal video recorders  
PC-TV receivers  
Also included in the design is a 7-bit ADC to detect the RF  
signal strength and thereby efficiently control the tuner RF  
AGC.  
Portable applications  
Users have access to all the relevant signal quality infor-  
mation, including input signal power level, signal-to-noise  
ratio, pre-Viterbi BER, post-Viterbi BER, and the uncor-  
rectable block counts. The error rate monitoring periods are  
programmable over a wide range.  
Description  
The CE6355 is a superior fourth generation fully compliant  
ETSI ETS300 744 COFDM demodulator that exceeds, with  
margin, the performance requirements of all known DVB-T  
digital terrestrial television standards, including Unified  
Nordig and DTG.  
The device is packaged in a 7 x 7 mm 64-pin LQFP and is  
very low power.  
Figure 1 - Block Diagram  
Intel Corporation  
Intel and the Intel logo are registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries.  
*Other names and brands may be claimed as the property of others.  
Copyright © 2006 Intel Corporation. All rights reserved.  
Data Sheet  
CE6355  
Legal information  
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY  
ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN  
INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS  
ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES  
RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER  
INTELLECTUAL PROPERTY RIGHT.  
Intel products are not intended for use in medical, life saving, life sustaining applications.  
Intel may make changes to specifications and product descriptions at any time, without notice.  
Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel  
reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future  
changes to them.  
This manual may contain design defects or errors known as errata, which may cause the product to deviate from published  
specifications. Current characterized errata are available on request.  
This manual as well as the software described in it, is furnished under license and may only be used or copied in accordance with the  
terms of the license. The information in this document is furnished for informational use only, is subject to change without notice, and  
should not be construed as a commitment by Intel Corporation. Intel Corporation assumes no responsibility or liability for any errors or  
inaccuracies that may appear in this document or any software that may be provided in association with this document.  
Except as permitted by such license, no part of this document may be reproduced, stored in a retrieval system, or transmitted in any  
form or by any means without the express written consent of Intel Corporation.  
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.  
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by  
calling 1-800-548-4725 or by visiting Intel's website at http://www.intel.com.  
BunnyPeople, Celeron, Celeron Inside, Centrino, Centrino logo, Chips, Core Inside, Dialogic, EtherExpress, ETOX, FlashFile, i386, i486,  
i960, iCOMP, InstantIP, Intel, Intel logo, Intel386, Intel486, Intel740, IntelDX2, IntelDX4, IntelSX2, Intel Core, Intel Inside, Intel Inside  
logo, Intel. Leap ahead., Intel. Leap ahead. logo, Intel NetBurst, Intel NetMerge, Intel NetStructure, Intel SingleDriver, Intel SpeedStep,  
Intel StrataFlash, Intel Viiv, Intel XScale, IPLink, Itanium, Itanium Inside, MCS, MMX, MMX logo, Optimizer logo, OverDrive, Paragon,  
PDCharm, Pentium, Pentium II Xeon, Pentium III Xeon, Performance at Your Command, Pentium Inside, skoool, Sound Mark, The  
Computer Inside., The Journey Inside, VTune, Xeon, Xeon Inside and Xircom are trademarks or registered trademarks of Intel  
Corporation or its subsidiaries in the United States and other countries.  
MPEG is an international standard for video compression/decompression promoted by ISO. Implementations of MPEG CODECs, or MPEG  
enabled platforms may require licenses from various entities, including Intel Corporation.  
*Other names and brands may be claimed as the property of others.  
Copyright © 2006, Intel Corporation  
TECHNICAL DOCUMENTATION - NOT FOR RESALE  
Change History  
Issue  
Date  
Description  
D55755-002  
November  
2006  
Added package drawing, minor corrections to pin outline drawing, removal of  
non-lead-free part numbers and improvements in the descriptions in electrical  
characteristics. Corrections to the current capability of the MPEG and STATUS  
outputs in the “Pin Description Table” on page 9 and the MOCLK output current in  
*
“DC Electrical Characteristics” on page 22 .  
D55755-001  
1.00  
April 2006  
Converted to Intel format  
February 2005 First issue of document  
*. Note that these are only corrections to bring the documentation in line with actual device performance, and do not imply any change to the CE6355  
or to any applications.  
2
Intel Corporation  
CE6355  
Data Sheet  
Table of Contents  
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1  
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1  
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1  
Legal information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2  
Change History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2  
1 Pin & Package Details.......................................................................................................................................................................7  
1.1 Package dimensions........................................................................................................................................................... 7  
1.2 Pin Outline...............................................................................................................................................................................7  
1.3 Pin Allocation.........................................................................................................................................................................8  
1.4 Pin Description......................................................................................................................................................................9  
2 Functional Description..................................................................................................................................................................11  
2.1 Analogue-to-Digital Converter..................................................................................................................................12  
2.2 Automatic Gain Control.................................................................................................................................................12  
2.3 IF to Baseband Conversion.........................................................................................................................................12  
2.4 Adjacent Channel Filtering..........................................................................................................................................13  
2.5 Interpolation and Clock Synchronisation.............................................................................................................13  
2.6 Carrier Frequency Synchronisation........................................................................................................................13  
2.7 Symbol Timing Synchronisation...............................................................................................................................13  
2.8 Fast Fourier Transform.................................................................................................................................................13  
2.9 Common Phase Error Correction .............................................................................................................................13  
2.10 Channel Equalisation ...................................................................................................................................................13  
2.11 Impulse Filtering.............................................................................................................................................................13  
2.12 Transmission Parameter Signalling (TPS)........................................................................................................13  
2.13 De-Mapper.........................................................................................................................................................................14  
2.14 Symbol and Bit De-Interleaving.............................................................................................................................14  
2.15 Viterbi Decoder...............................................................................................................................................................14  
2.16 MPEG Frame Aligner....................................................................................................................................................14  
2.17 De-interleaver.................................................................................................................................................................14  
2.18 Reed-Solomon Decoder .............................................................................................................................................14  
2.19 De-scrambler....................................................................................................................................................................14  
2.20 MPEG Transport Interface........................................................................................................................................14  
3 Interfaces.............................................................................................................................................................................................15  
3.1 2-Wire Bus............................................................................................................................................................................15  
3.1.1 Host............................................................................................................................................................................................................................15  
3.1.2 Tuner.........................................................................................................................................................................................................................15  
3.1.3 Examples of 2-wire bus messages:..........................................................................................................................................................16  
3.1.4 Primary 2-wire bus timing.............................................................................................................................................................................16  
3.2 MPEG........................................................................................................................................................................................17  
3.2.1 Data Output Header Format........................................................................................................................................................................17  
3.2.2 MPEG Data Output Signals............................................................................................................................................................................18  
3.2.3 MPEG Output Timing ........................................................................................................................................................................................18  
3.2.4 MOCLKINV = 1......................................................................................................................................................................................................18  
3.2.5 MOCLKINV = 0......................................................................................................................................................................................................19  
4 Electrical Characteristics .............................................................................................................................................................21  
4.1 Operating Conditions......................................................................................................................................................21  
4.2 Absolute Maximum Ratings........................................................................................................................................21  
4.3 DC Electrical Characteristics.......................................................................................................................................22  
4.4 AC Electrical Characteristics.......................................................................................................................................22  
4.5 Crystal Specification and External Clocking......................................................................................................23  
4.5.1 Selection of External Components...........................................................................................................................................................24  
4.5.1.1 Loop Gain Equation..............................................................................................................................................................................24  
3
Intel Corporation  
Data Sheet  
CE6355  
Table of Contents  
4.5.1.2 List of Equation Parameters..........................................................................................................................................................24  
4.5.1.3 Calculating Crystal Power Dissipation ......................................................................................................................................25  
4.5.1.4 Capacitor Values ...................................................................................................................................................................................25  
4.5.1.5 Oscillator/Clock Application Notes..............................................................................................................................................25  
5 Application Circuit........................................................................................................................................................................... 27  
4
Intel Corporation  
CE6355  
Data Sheet  
List of Figures  
Figure 1 - Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1  
Figure 2 - Package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7  
Figure 3 - Pin Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7  
Figure 4 - OFDM Demodulator Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11  
Figure 5 - FEC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12  
Figure 6 - Primary 2-Wire Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16  
Figure 7 - DVB Transport Packet Header Byte. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17  
Figure 8 - MPEG Output Data Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18  
Figure 9 - MPEG Timing - MOCLKINV = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19  
Figure 10 - MPEG Timing - MOCLKINV = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19  
Figure 11 - VIN & VIN equivalent circuit for inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23  
Figure 12 - VIN & VIN input impedance (approximate) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23  
Figure 13 - RFLEV equivalent circuit for input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23  
Figure 14 - Crystal Oscillator Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24  
Figure 15 - External Clocking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26  
Figure 16 - Typical Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27  
5
Intel Corporation  
Data Sheet  
CE6355  
List of Tables  
Table 1 - Pin Names - numeric . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8  
Table 2 - Pin Names - alphabetical order. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8  
Table 3 - 2-wire bus address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15  
Table 4 - Timing of 2-Wire Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17  
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Intel Corporation  
CE6355  
Data Sheet  
1
Pin & Package Details  
1.1  
Package dimensions  
Figure 2 - Package dimensions  
1.2  
Pin Outline  
Figure 3 - Pin Outline  
7
Intel Corporation  
Data Sheet  
CE6355  
1.3  
Pin Allocation  
Table 1 - Pin Names - numeric  
Pin  
Function  
Vss  
Pin  
17  
Function  
Pin  
33  
Function  
Vdd  
Pin  
49  
Function  
1
SADD1  
SADD0  
CVdd  
Vss  
MDO0  
MDO1  
MDO2  
MDO3  
MDO4  
Vdd  
2
3
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
34  
35  
36  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
50  
51  
52  
53  
54  
55  
56  
57  
58  
59  
60  
61  
62  
63  
64  
Vdd  
RFLEV  
CLK2/GPP0  
DATA2/GPP1  
CVdd  
Vss  
4
CLK1  
DATA1  
IRQ  
5
PLLVdd  
PLLGND  
XTI  
6
Vss  
7
CVdd  
Vss  
CVdd  
Vss  
8
XTO  
Vss  
MDO5  
MDO6  
MDO7  
CVdd  
Vss  
9
RESET  
SLEEP  
STATUS  
SADD4  
Vdd  
Vss  
AGC2/GPP2  
AGC1  
10  
11  
12  
13  
14  
15  
16  
PLLTEST  
OSCMODE  
AVdd  
AGnd  
VIN  
GPP3  
SMTEST  
Vdd  
MOCLK  
BKERR  
Vss  
Vss  
SADD3  
SADD2  
VIN  
MOSTRT  
MOVAL  
MICLK  
CVdd  
AGnd  
Table 2 - Pin Names - alphabetical order  
Function  
AGC1  
Pin  
42  
Function  
Pin  
43  
Function  
Pin  
26  
Function  
Pin  
54  
30  
31  
1
GPP3  
PLLTEST  
PLLVdd  
RESET  
RFLEV  
SADD0  
SADD1  
SADD2  
SADD3  
SADD4  
SLEEP  
SMTEST  
STATUS  
Vdd  
Vdd  
VIN  
VIN  
Vss  
Vss  
Vss  
Vss  
Vss  
Vss  
Vss  
Vss  
Vss  
Vss  
Vss  
XTI  
XTO  
41  
29  
32  
28  
62  
4
6
49  
50  
51  
52  
53  
56  
57  
58  
63  
61  
47  
48  
27  
22  
21  
9
AGC2/GPP2  
AGnd  
IRQ  
MDO0  
MDO1  
MDO2  
MDO3  
MDO4  
MDO5  
MDO6  
MDO7  
MICLK  
MOCLK  
MOSTRT  
MOVAL  
OSCMODE  
PLLGND  
34  
18  
17  
16  
15  
12  
10  
44  
11  
2
AGnd  
3
AVdd  
8
BKERR  
CLK1  
14  
20  
25  
38  
40  
46  
55  
60  
23  
24  
35  
7
CLK2/GPP0  
CVdd  
19  
37  
39  
59  
64  
5
CVdd  
CVdd  
CVdd  
CVdd  
13  
33  
45  
CVdd  
Vdd  
DATA1  
DATA2/GPP1  
Vdd  
36  
Vdd  
8
Intel Corporation  
CE6355  
Data Sheet  
1.4  
Pin Description  
Pin Description Table  
Pin No  
MPEG pins  
47  
Name  
Pin Description  
I/O  
Type  
V
mA  
MOSTRT  
MOVAL  
MPEG packet start  
O
O
O
O
O
I
3.3  
3.3  
3.3  
3.3  
3.3  
3.3  
3.3  
5
48  
MPEG data valid  
MPEG data bus  
MPEG clock out  
Block error  
2
49-53, 56-58  
MDO(0:4)/MDO(5:7)  
CMOS Tristate  
61  
62  
63  
11  
12  
2
MOCLK  
BKERR  
MICLK  
STATUS  
IRQ  
MPEG clock in  
Status output  
Interrupt output  
CMOS  
O
O
2
6
6
Open drain  
Control pins  
4
Serial clock  
I
CMOS  
5
5
CLK1  
5
Serial data  
I/O  
I
Open drain  
6
DATA1  
23  
Low phase noise oscillator  
XTI  
24  
XTO  
O
I
10  
SLEEP  
Device power down  
Serial address set  
Production test (only set low)  
Serial clock tuner  
Serial data tuner  
Primary AGC  
3.3  
3.3  
3.3  
5
12, 15-18  
44  
SADD(4:0)  
SMTEST  
I
CMOS  
I
35  
CLK2/GPP0  
DATA2/GPP1  
AGC1  
I/O  
I/O  
O
I/O  
I/O  
I
6
6
6
6
6
36  
5
42  
Open drain  
5
41  
AGC2/GPP2  
GPP(3)  
Secondary AGC  
5
43  
General purpose I/O  
Device reset  
5
9
CMOS  
5
RESET  
27  
OSCMODE  
Crystal oscillator mode  
PLL analog test  
I
CMOS  
3.3  
26  
PLLTEST  
O
(tristated)  
Analog inputs  
30  
VIN  
positive input  
negative input  
I
I
31  
VIN  
34  
RF level  
I
RFLEV  
Supply pins  
21  
PLLVdd  
PLLGnd  
CVdd  
PLL supply  
S
S
S
S
1.8  
0
22  
7, 19, 37, 39, 59, 64  
2, 13, 45, 54,  
Core logic power  
I/O ring power  
1.8  
3.3  
Vdd  
9
Intel Corporation  
Data Sheet  
CE6355  
Pin Description Table (continued)  
Pin No  
Name  
Pin Description  
I/O  
S
Type  
V
mA  
1, 3, 8, 14, 20, 25,  
Vss  
Core and I/O ground  
0
38, 40, 46, 55, 60  
28  
AVdd  
AGnd  
Vdd  
ADC analog supply  
S
S
S
1.8  
0
29, 32  
33  
2nd ADC supply  
3.3  
10  
Intel Corporation  
CE6355  
Data Sheet  
2
Functional Description  
A functional block diagram of the CE6355 OFDM demodulator is shown in Figure 4. This accepts an IF analogue signal and  
delivers a stream of demodulated soft decision data to the on-chip Viterbi decoder. Clock, timing and frequency synchroni-  
zation operations are all digital and there are no analogue control loops except the AGC. The frequency capture range is  
large enough for all practical applications. This demodulator has novel algorithms to combat impulse noise as well as  
co-channel and adjacent channel interference. If the modulation is hierarchical, the OFDM outputs both high and low  
priority data streams. Only one of these streams is FEC-decoded, but the FEC can be switched from one stream to another  
with minimal interruption to the transport stream.  
Figure 4 - OFDM Demodulator Diagram  
The FEC module shown in Figure 5 consists of a concatenated convolutional (Viterbi) and Reed-Solomon decoder  
separated by a depth-12 convolutional de-interleaver. The Viterbi decoder operates on 5-bit soft decisions to provide the  
best performance over a wide range of channel conditions. The trace-back depth of 128 ensures minimum loss of perfor-  
mance due to inevitable survivor truncation, especially at high code rates. Both the Viterbi and Reed-Solomon decoders  
are equipped with bit-error monitors. The former provides the bit error rate (BER) at the OFDM output. The latter is the  
more useful measure as it gives the Viterbi output BER. The error collecting intervals of these are programmable over a  
very wide range.  
11  
Intel Corporation  
Data Sheet  
CE6355  
Figure 5 - FEC Block Diagram  
The FSM controller shown in Figure 4 controls both the demodulator and the FEC. It also drives the 2-wire bus to the  
tuner. The controller facilitates the automated search of all parameters or any sub-set of parameters of the received  
signal. It can also be used to scan any defined frequency range searching for OFDM channels. This mechanism provides  
the fast channel scan and acquisition performance, whilst requiring minimal software overhead in the host driver.  
The algorithms and architectures used in the CE6355 have been optimized to minimize power consumption.  
2.1  
Analogue-to-Digital Converter  
The CE6355 has a high performance 10-bit analogue-to-digital converter (ADC) which can sample a 6, 7 or 8 MHz  
bandwidth OFDM signal, with its spectrum centred at:  
36.17 MHz IF  
43.75 MHz IF  
5 - 10 MHz near-zero IF  
An on-chip programmable phase locked loop (PLL) is used to generate the ADC sampling clock. The PLL is highly program-  
mable allowing a wide choice of sampling frequencies to suit any IF frequency, and all signal bandwidths.  
2.2  
Automatic Gain Control  
An AGC module compares the absolute value of the digitized signal with a programmable reference. The error signal is  
filtered and is used to control the gain of the amplifier. A sigma-delta modulated output is provided, which has to be RC  
low-pass filtered to obtain the voltage to control the amplifier.  
The programmable AGC reference has been optimized. A large value for the reference leads to excessive ADC clipping and  
a small value results in excessive quantization noise. Hence the optimum value has been determined assuming the input  
signal amplitude to be Gaussian distributed. The latter is justified by applying the central limit theorem in statistics to the  
OFDM signal, which consists of a large number of randomly modulated carriers. This reference or target value may have to  
be lowered slightly for some applications. Slope control bits have been provided for the AGCs and these have to be set  
correctly depending on the gain-versus-voltage slope of the gain control amplifiers.  
The bandwidth of the AGC is set to a large value for quick acquisition then reduced to a small value for tracking. The AGC  
is free running during OFDM channel changes and locks to the new channel while the tuner lock is being established. This  
is one of the features of CE6355 used to minimize acquisition time. A robust AGC lock mechanism is provided and the  
other parts of the CE6355 begin to acquire only after the AGC has locked.  
2.3  
IF to Baseband Conversion  
Sampling a 36.17 MHz IF signal at 45 MHz results in a spectrally inverted OFDM signal centred at approximately 8.9 MHz.  
The first step of the demodulation process is to convert this signal to a complex (in-phase and quadrature) signal in  
baseband. A correction for spectral inversion is implemented during this conversion process. Note also that the CE6355  
has control mechanisms to search automatically for an unknown spectral inversion status.  
12  
Intel Corporation  
CE6355  
Data Sheet  
2.4  
Adjacent Channel Filtering  
Adjacent channels, in particular the Nicam digital sound signal associated with analogue channels, are filtered prior to the  
FFT.  
2.5  
Interpolation and Clock Synchronisation  
CE6355 uses digital timing recovery and this eliminates the need for an external VCXO. The ADC samples the signal at a  
fixed rate, for example, 45.056 MHz. Conversion of the 45.056 MHz signal to the OFDM sample rate is achieved using the  
time-varying interpolator. The OFDM sample rate is 64/7 MHz for 8 MHz and this is scaled by factors 6/8 and 7/8 for 6  
and 7 MHz channel bandwidths. The nominal ratio of the ADC to OFDM sample rate is programmed in a CE6355 register  
(defaults are for 45 MHz sampling and 8 MHz OFDM). The clock recovery phase locked loop in the CE6355 compensates  
for inaccuracies in this ratio due to uncertainties of the frequency of the sampling clock.  
2.6  
Carrier Frequency Synchronisation  
There can be frequency offsets in the signal at the input to OFDM, partly due to tuner step size and partly due to  
broadcast frequency shifts, typically 1/6 MHz. These are tracked out digitally, up to 1 MHz in 2 K and 8 K modes, without  
the need for an analogue frequency control (AFC) loop.  
The default frequency capture range has been set to ±286 kHz in the 2 K and 8 K mode. However, these values can be  
increased, if necessary, by programming an on-chip register (see details in the design manual). It is recommended that a  
larger capture range be used for channel scan in order to find channels with broadcast frequency shifts, without having to  
adjust the tuner. After the OFDM module has locked (the AFC will have been previously disabled), the frequency offset  
can be read from an on-chip register.  
2.7  
Symbol Timing Synchronisation  
This module computes the optimum sample position to trigger the FFT in order to eliminate or minimize inter-symbol  
interference in the presence of multi-path distortion. Furthermore, this trigger point is continuously updated to dynami-  
cally adapt to time-variations in the transmission channel.  
2.8  
Fast Fourier Transform  
The FFT module uses the trigger information from the timing synchronization module to set the start point for an FFT. It  
then uses either a 2 K or 8 K FFT to transform the data from the time domain to the frequency domain. An extremely  
hardware-efficient and highly accurate algorithm has been used for this purpose.  
2.9  
Common Phase Error Correction  
This module subtracts the common phase offset from all the carriers of the OFDM signal to minimize the effect of the  
tuner phase noise on system performance.  
2.10  
Channel Equalisation  
This consists of two parts. The first part involves estimating the channel frequency response from pilot information.  
Efficient algorithms have been used to track time-varying channels with a minimum of hardware.  
The second part involves applying a correction to the data carriers based on the estimated frequency response of the  
channel. This module also generates dynamic channel state information (CSI) for every carrier in every symbol.  
2.11  
Impulse Filtering  
CE6355 contains several mechanisms to reduce the impact of impulse noise on system performance.  
2.12  
Transmission Parameter Signalling (TPS)  
An OFDM frame consists of 68 symbols and a superframe is made up of four such frames. There is a set of TPS carriers in  
every symbol and all these carry one bit of TPS. These bits, when combined, include information about the transmission  
mode, guard ratio, constellation, hierarchy and code rate, as defined in ETS 300 744. In addition, the first eight bits of the  
cell identifier are contained in even frames and the second eight bits of the cell identifier are in odd frames. The TPS  
module extracts all the TPS data, and presents these to the host processor in a structured manner.  
13  
Intel Corporation  
Data Sheet  
CE6355  
2.13  
De-Mapper  
This module generates soft decisions for demodulated bits using the channel-equalized in-phase and quadrature compo-  
nents of the data carriers as well as per-carrier channel state information (CSI). The de-mapping algorithm depends on the  
constellation (QPSK, 16 QAM or 64 QAM) and the hierarchy (α = 0, 1, 2 or 4). Soft decisions for both low- and high-priority  
data streams are generated.  
2.14  
Symbol and Bit De-Interleaving  
The OFDM transmitter interleaves the bits within each carrier and also the carriers within each symbol. The de-interleaver  
modules consist largely of memory to invert these interleaving functions and present the soft decisions to the FEC in the  
original order.  
2.15  
Viterbi Decoder  
The Viterbi decoder accepts the soft decision data from the OFDM demodulator and outputs a decoded bit-stream. The  
decoder does the de-puncturing of the input data for all code rates other than 1/2. It then evaluates the branch metrics  
and passes these to a 64-state path-metric updating unit, which in turn outputs a 64-bit word to the survivor memory.  
The Viterbi decoded bits are obtained by tracing back the survivor paths in this memory. A trace-back depth of 128 is  
used to minimize any loss in performance, especially at high code rates.  
The decoder re-encodes the decoded bits and compares these with received data (delayed) to compute bit errors at its  
input, on the assumption that the Viterbi output BER is significantly lower than its input BER.  
2.16  
MPEG Frame Aligner  
The Viterbi decoded bit stream is aligned into 204-byte frames. A robust synchronization algorithm is used to ensure  
correct lock and to prevent loss of lock due to noise impulses.  
2.17  
De-interleaver  
Errors at the Viterbi output occur in bursts and the function of the de-interleaver is to spread these errors over a number  
of 204-byte frames to give the Reed-Solomon decoder a better chance of correcting these. The de-interleaver is a  
memory unit which implements the inverse of the convolutional interleaving function introduced by the transmitter.  
2.18  
Reed-Solomon Decoder  
Every 188-byte transport packet is encoded by the transmitter into a 204-byte frame, using a truncated version of a  
systematic (255,239) Reed-Solomon code. The corresponding (204,188) Reed-Solomon decoder is capable of correcting  
up to eight byte errors in a 204-byte frame. It may also detect frames with more than eight byte errors.  
In addition to efficiently performing this decoding function, the Reed-Solomon decoder in CE6355 keeps a count of the  
number of bit errors corrected over a programmable period and the number of uncorrectable blocks. This information can  
be used to compute the post-Viterbi BER.  
2.19  
De-scrambler  
The de-scrambler de-randomizes the Reed-Solomon decoded data by generating the exclusive-OR of this with a  
pseudo-random bit sequence (PRBS). This outputs 188-byte MPEG transport packets. The TEI bit of the packet header  
may be set if required to indicate uncorrectable packets.  
2.20  
MPEG Transport Interface  
MPEG data can be output in parallel or serial mode. The output clock frequency is automatically chosen to present the  
MPEG data as uniformly spaced as possible to the transport processor. This frequency depends on the guard ratio,  
constellation, hierarchy and code rate. There is also an option for the data to be extracted from the CE6355 with a clock  
provided by the user.  
14  
Intel Corporation  
CE6355  
Data Sheet  
3
Interfaces  
2-Wire Bus  
Host  
3.1  
3.1.1  
The primary 2-wire bus serial interface uses pins:  
DATA1 (pin5) serial data, the most significant bit is sent first.  
CLK1 (pin 4) serial clock.  
The 2-wire bus address is determined by a combination of internal settings and applying Vdd or Gnd to the SADD[4:0]  
pins:  
Table 3 - 2-wire bus address  
ADDR[7]  
Gnd  
ADDR[6]  
Gnd  
ADDR[5]  
SADD[4]  
Gnd  
ADDR[4]  
SADD[3]  
Vdd  
ADDR[3]  
SADD[2]  
Vdd  
ADDR[2]  
SADD[1]  
Vdd  
ADDR[1]  
SADD[0]  
Vdd  
Address bits  
Internal/external settings  
Normal TNIM settings  
Gnd  
Gnd  
When the CE6355 is powered up, the RESET pin 9 should be held low for at least 50 ms after Vdd has reached normal  
operation levels. As the RESET pin goes high, the logic levels on SADD[4:0] are latched as the 2-wire bus address. ADDR[0]  
is the R/W bit.  
The circuit works as a slave transmitter with the lsb set high or as a slave receiver with the lsb set low. In receive mode,  
the first data byte is written to the RADD virtual register, which forms the register sub-address. The RADD register takes  
an 8-bit value that determines which of 256 possible register addresses is written to by the following byte. Not all  
addresses are valid and many are reserved registers that must not be changed from their default values. Multiple byte  
reads or writes will auto-increment the value in RADD, but care should be taken not to access the reserved registers  
accidentally.  
Following a valid chip address, the 2-wire bus STOP command resets the RADD register to 00. If the chip address is not  
recognized, the CE6355 will ignore all activity until a valid chip address is received. The 2-wire bus START command does  
NOT reset the RADD register to 00. This allows a combined 2-wire bus message, to point to a particular read register with  
a write command, followed immediately with a read data command. If required, this could next be followed with a write  
command to continue from the latest address. RADD would not be sent in this case. Finally, a STOP command should be  
sent to free the bus.  
When the 2-wire bus is addressed (after a recognized STOP command) with the read bit set, the first byte read out is the  
contents of register 00.  
3.1.2  
Tuner  
The CE6355 has a General Purpose Port that can be configured to provide a secondary 2-wire bus.  
Master control mode is selected by setting register SCAN_CTL (0x62) [b3] = 1.  
*
The allocation of the pins is: GPP0 pin 35 = CLK2 , GPP1 pin 36 = DATA2.  
*. Please note that in this configuration, this pin is an output only and therefore does not allow a clock-hold function in the slave device.  
Intel Corporation  
15  
Data Sheet  
CE6355  
3.1.3  
KEY:  
Examples of 2-wire bus messages:  
S
Start condition  
Stop condition  
Acknowledge  
CE6355 output  
W
Write (= 0)  
P
R
Read (= 1)  
A
NA  
RADD  
NOT Acknowledge  
Register Address  
Italics  
Write operation - as a slave receiver:  
S
DEVICE  
W
A
RADD  
(n)  
A
DATA  
A
DATA  
A
P
ADDRESS  
(reg n)  
(reg n+1)  
Read operation - CE6355 as a slave transmitter:  
S
DEVICE  
R
A
DATA  
A
DATA  
A
DATA  
NA  
P
ADDRESS  
(reg 0)  
(reg 1)  
(reg 2)  
Write/read operation with repeated start - CE6355 as a slave transmitter:  
S
DEVICE  
W
A
RADD  
(n)  
A
S
DEVICE  
R
A
DATA  
A
DATA  
NA  
P
ADDRESS  
ADDRESS  
(reg n)  
(reg n+1)  
3.1.4  
Primary 2-wire bus timing  
Figure 6 - Primary 2-Wire Bus Timing  
tBUFF  
Sr  
P
DATA1  
tLOW  
tR  
tF  
CLK1  
P
S
tSU;STO  
tHIGH  
tSU;DAT tSU;STA  
tHD;STA  
tHD;DAT  
Where:  
S = Start  
Sr = Restart, i.e., start without stopping first.  
P = Stop.  
16  
Intel Corporation  
CE6355  
Data Sheet  
Table 4 - Timing of 2-Wire Bus  
Values with 20.48 MHz  
clock*  
Values with 4MHz clock  
Parameter  
Symbol  
Unit  
Min.  
0
Max.  
100  
Min.  
Max.  
400  
fCLK  
CLK clock frequency (Primary)  
0
kHz  
µs  
Bus free time between a STOP and START  
condition.  
tBUFF  
4.7  
1.3  
Hold time (repeated) START condition.  
LOW period of CLK clock.  
tHD;STA  
tLOW  
4.0  
4.7  
4.0  
4.7  
0
0.6  
1.3  
0.6  
0.6  
0
µs  
µs  
µs  
µs  
µs  
ns  
ns  
HIGH period of CLK clock.  
tHIGH  
tSU;STA  
tHD;DAT  
tSU;DAT  
tR  
Set-up time for a repeated START condition.  
Data hold time (when input).  
Data set-up time  
3.45  
0.9  
250  
100  
Rise time of both CLK and DATA signals.  
1000  
300  
20 + 0.1C  
20 + 0.1C  
0.6  
300  
300  
b
b
Fall time of both CLK and DATA signals, (100pF to  
ground).  
tF  
ns  
µs  
Set-up time for a STOP condition.  
tSU;STO  
4.0  
*. Or 27.00 MHz clock  
†. Cb = the total capacitance on either clock or data line in pF to maximum of 400pF.  
3.2  
MPEG  
3.2.1  
Data Output Header Format  
Figure 7 - DVB Transport Packet Header Byte  
188 byte packet output  
184 Transport packet bytes  
Transport  
Packet  
Header  
4 bytes  
1st byte  
2nd byte  
0
1
0
0
0
1
1
1
TEI  
MDO[7]  
MDO[0]  
After decoding the 188-byte MPEG packet, it is output on the MDO pins in 188 consecutive clock cycles.  
Additionally when the TEI_En bit in the OP_CTRL_0 register (0x5A) is set high (default), the TEI bit of any uncorrectable  
packet will automatically be set to ‘1’. If TEI_En bit is low then TEI bit will not be changed (but note that if this bit is already  
1, for example, due to a channel error which has not been corrected, it will remain high at output).  
17  
Intel Corporation  
Data Sheet  
CE6355  
3.2.2  
MPEG Data Output Signals  
The MPEGEN bit in the CONFIG register must be set low to enable the MPEG data. The maximum movement in the packet  
synchronization byte position is limited to ±1 output clock period. MOCLK will be a continuously running clock once symbol  
lock has been achieved, and is derived from the symbol clock. MOCLK is shown in Figure 8 with MOCLKINV = ‘1’, the default  
state, see register 0x50.  
All output data and signals (MDO[7:0], MOSTRT, MOVAL & BKERR) change on the negative edge of MOCLK (MOCLKINV = 1)  
to present stable data and signals on the positive edge of the clock.  
A complete packet is output on MDO[7:0] on 188 consecutive clocks and the MDO[7:0] pins will remain low during the  
inter-packet gaps. MOSTRT goes high for the first byte clock of a packet. MOVAL goes high on the first byte of a packet  
and remains high until the last byte has been clocked out. BKERR goes low on the first byte of a packet where uncor-  
rectable bytes are detected and will remain low until the last byte has been clocked out.  
Figure 8 - MPEG Output Data Waveforms  
188 byte packet n  
1st byte packet n  
1st byte packet n+1  
MOCLKINV=1  
MOCLK  
MDO7:0  
MOSTRT  
MOVAL  
BKERR  
Tp  
Ti  
3.2.3  
MPEG Output Timing  
o
Maximum delay conditions: Vdd = 3.0V, CVdd = 1.62V, Tamb = 85 C, Output load = 10pF.  
o
Minimum delay conditions: Vdd = 3.6V, CVdd = 1.98V, Tamb = -40 C, Output load = 10pF.  
MOCLK frequency = 45.06 MHz.  
3.2.4  
MOCLKINV = 1  
Delay conditions  
Maximum Minimum  
3.0 1.0  
Parameter  
Data output delay t  
Units  
ns  
D
Setup Time t  
7.0  
7.0  
10.0  
10.0  
SU  
Hold Time t  
H
18  
Intel Corporation  
CE6355  
Data Sheet  
Figure 9 - MPEG Timing - MOCLKINV = 1  
MOCLK  
tD  
MDO  
MOSTRT  
MOVAL  
}
tSU  
BKERR  
tH  
3.2.5  
MDOSWAP = 0  
MOCLKINV = 0  
Delay Conditions  
Maximum Minimum  
3.0 1.0  
Parameter  
Data output delay t  
Units  
D
Setup Time t  
18.0  
1.0  
20.0  
0.2  
ns  
SU  
Hold Time t  
H
The hold time is better when MOCLKINV = 1, therefore this should be used if possible.  
Figure 10 - MPEG Timing - MOCLKINV = 0  
MOCLK  
tD  
MDO  
MOSTRT  
MOVAL  
}
BKERR  
tSU  
tH  
19  
Intel Corporation  
Data Sheet  
CE6355  
20  
Intel Corporation  
CE6355  
Data Sheet  
4
Electrical Characteristics  
4.1  
Operating Conditions  
Recommended Operating Conditions  
Parameter  
Symbol  
Vdd  
Min.  
Typ.  
Max.  
Units  
V
Power supply voltage:  
periphery  
core  
3.0  
3.3  
1.8  
1
3.6  
CVdd  
IddP  
V
1.62  
1.98  
Power supply current:  
periphery *  
core  
mA  
mA †  
MHz  
kHz  
°C  
IddC  
170  
20.48  
Input clock frequency ‡  
XTI  
16.00  
-40  
25.00  
CLK1 primary serial clock frequency **  
Ambient operating temperature  
fCLK  
400  
85  
*. Current from the 3.3 V supply will be mainly dependent on the external loads.  
†. Current given is for optimum performance, lower current is possible with reduced performance.  
‡. The min/max frequencies given are those supported by the oscillator cell. Required system frequencies are as defined in the design manual. Frequen-  
cies outside these limits are acceptable with an external clock signal.  
**. If operating with an external 4 MHz clock, the serial clock frequency is reduced to 100 kHz maximum.  
4.2  
Absolute Maximum Ratings  
Maximum Operating Conditions  
Parameter  
Symbol  
Min.  
Max.  
+3.6  
Unit  
Conditions  
Vdd  
V
V
V
V
V
V
V
Power supply  
CVdd  
+2.0  
5.5  
Voltage on input pins (5 V rated)  
Voltage on input pins (3.3 V rated)  
Voltage on analog input pins (VIN & VIN)  
Voltage on output pins (5 V rated)  
Voltage on output pins (3.3V rated)  
VI  
-0.3  
Vdd + 0.3  
Pin 33 = Vdd  
5.5  
VO  
Vdd + 0.3  
ESD ratings (all pins):  
HBM  
CDM  
V
V
±2000  
±800  
Storage temperature  
TSTG  
TOP  
TJ  
-55  
-40  
150  
85  
°C  
°C  
°C  
Operating ambient temperature  
Junction temperature  
125  
Note: Stresses exceeding these listed under absolute maximum ratings may induce failure. Exposure to absolute maximum ratings for  
extended periods may reduce reliability. Functionality at or above these conditions is not implied.  
21  
Intel Corporation  
Data Sheet  
CE6355  
4.3  
DC Electrical Characteristics  
DC Electrical Characteristics  
Parameter  
Conditions  
Pins  
Symbol  
Vdd  
Min.  
Typ.  
Max. Unit  
Operating  
voltage  
periphery  
V
3.0  
3.3  
1.8  
3.6  
core  
V
CVdd  
1.62  
1.98  
Supply current *  
1.62>CVdd>1.98  
mA  
µA  
Idd  
170  
300  
C
Supply current sleep mode  
Outputs  
IOH 2mA  
V
V
V
V
V
VOH  
VOL  
VOH  
VOL  
VOL  
2.4  
2.4  
3.0>Vdd>3.6  
MDO(7:0), MOVAL, MOSTRT,  
STATUS, BKERR  
IOL 2mA  
3.0>Vdd>3.6  
0.4  
IOH 12mA  
3.0>Vdd>3.6  
Output levels  
MOCLK  
IOL 12mA  
3.0>Vdd>3.6  
0.4  
0.4  
IOL 6mA  
3.0>Vdd>3.6  
GPP(3:0), DATA1, AGC1,  
AGC2, IRQ  
MDO(7:0), MOVAL, MOSTRT,  
MOCLK, STATUS, BKERR  
pF  
pF  
µA  
3.0  
Output capacitance  
Not including track  
GPP(3:0), DATA1, AGC1,  
AGC2,IRQ  
3.6  
Output leakage (tri-state)  
Inputs  
1
Input levels  
3.0>Vdd>3.6  
-0.5 Vin ≥  
Vdd+0.5V  
MICLK, SADD(4:0)SLEEP,  
OSCMODE  
V
V
VIH  
2.0  
2.0  
Input levels  
3.0>Vdd>3.6  
-0.5 Vin +5.5V  
GPP(3:0), CLK1, DATA1,  
RESET  
VIH  
VIL  
Input levels  
All inputs  
V
0.8  
±1  
3.0>Vdd>3.6  
Input leakage Current  
Input capacitance  
Input capacitance  
SLEEP, SMTEST, MICLK, CLK1,  
OSCMODE  
µA  
pF  
pF  
Capacitances do not  
include track  
1.8  
3.6  
SADD(4:0), DATA1, GPP(3:0)  
*. Current given is for optimum performance, lower current is possible with reduced performance.  
4.4  
AC Electrical Characteristics  
AC Electrical Characteristics  
Parameter  
Conditions  
Pins  
Min.  
Typ.  
0.8  
Max. Unit  
Notes  
Analogue Inputs  
3.0>Vdd>3.6  
-0.5 Vin Vdd+0.5V VIN and VIN  
Nominal conditions for all 1’s on the  
*
Vp-p ADC outputs.See Figure 11 for  
more detail.  
Input levels  
3.0>Vdd>3.6  
RFLEV  
V
See Figure 13 for more detail.  
0.0  
Vdd  
-0.5 Vin +5.5V  
VIN, VIN  
3.0>Vdd>3.6  
See Figure 12 for more detail.  
D.C. signal  
Input impedance  
RFLEV  
25k  
*. capacitively coupled signal.  
†. for normal use, the AGC must control the level on the VIN/VIN pins.  
22  
Intel Corporation  
CE6355  
Data Sheet  
Figure 11 - VIN & VIN equivalent circuit for inputs  
Figure 12 - VIN & VIN input impedance (approximate)  
Figure 13 - RFLEV equivalent circuit for input  
4.5  
Crystal Specification and External Clocking  
Parallel resonant fundamental frequency (preferred)  
Tolerance over operating temperature range  
Tolerance overall  
20.4800 MHz  
± 150 ppm  
± 200 ppm  
23  
Intel Corporation  
Data Sheet  
CE6355  
Typical load capacitance  
Drive level  
Equivalent series resistance  
20 pF  
0.4 mW max  
<40 Ω  
Figure 14 - Crystal Oscillator Circuit  
XTI  
XT0  
OSCMODE  
XTI  
C1  
C2  
4.5.1  
Selection of External Components  
The capacitor values used must ensure correct operation of the Pierce oscillator such that the total loop gain is greater  
than unity. Correct selection of the two capacitors is very important and the following method is recommended to obtain  
values for C1 and C2. Alternatively there is a calculator available (ZLAN-125) that will calculate the external component  
values for you.  
4.5.1.1  
Loop Gain Equation  
Although oscillation may still occur if the loop gain is just above 1, a loop gain of between 5 and 25 is optimum to ensure  
that oscillations will occur across all variations in temperature, process and supply voltage, and that the circuit will exhibit  
good start-up characteristics.  
C
.g  
C
+ C  
in  
1
1
-1  
out  
m
out  
Equation 1 -  
- A =  
+
+
C
R .C  
Z
Z
o
in  
f
in  
in  
1
Equation 2 -  
4.5.1.2  
- Z =  
in  
2
(2.π.f.C ) .ESR  
out  
List of Equation Parameters  
A
total loop gain (between 5 and 25)  
Cin  
C1 + Cpar  
C2 + Cpar  
Cout  
Cpar  
parasitic capacitance associated with each oscillator pin (XTI and XTO). It consists of track capacitances,  
package capacitance and cell input capacitance. Normally Cpar 4pF.  
Zo  
gm  
Rf  
9.143k- output impedance of amplifier at 1.8V operation - typical  
8.736mA/V - transconductance of amplifier at 1.8V operation -typical  
2.3M- internal feedback resistor  
ESR  
f
maximum equivalent series resistance of crystal - given by crystal manufacturer ()  
fundamental frequency of crystal (Hz)  
24  
Intel Corporation  
CE6355  
Data Sheet  
4.5.1.3  
Calculating Crystal Power Dissipation  
To calculate the power dissipated in a crystal the following equation can be used.  
2
V
pp  
P =  
Equation 3 -  
c
8.Z  
in  
Pc = power dissipated in crystal at resonant frequency (W)  
Vpp = maximum peak to peak output swing of amplifier is 1.8V for all CVdd  
Zin = crystal network impedance (see Equation 2)  
4.5.1.4  
Capacitor Values  
Using the loop gain limits (5 < A < 25), the maximum and minimum values for C1 and C2 can be calculated with Equation 4  
below.  
g
A
2
1
Z
o
1
m
.
C = C  
=
-
-
Equation 4 -  
in  
out  
2
when: C = C = C - C  
par  
(2.π.f) .ESR  
1
2
out  
R
f
Note: Equation 4 was derived from Equation 1 and Equation 2 using the premise that C1 = C2.  
Within these limits, any value for C1 and C2 can now be selected. Normally C1 and C2 are chosen such that the resulting  
crystal load capacitance C (see Equation 5) is close to the crystal manufacturers recommended C (standard values for C  
L
L
L
are 15pF, 20pF and 30pF). The crystal will then operate very near its specified frequency.  
C
. C  
in  
out  
- C =  
C
par12  
+
Equation 5 -  
L
C
+ C  
out  
in  
C
par12 = parasitic capacitance between the XTI and XTO pins. It consists of the IC package’s pin-to-pin capacitance  
(including any socket used) and the printed circuit board’s track-to-track capacitance.  
C
2pF.  
par12  
If some frequency pulling can be tolerated, a crystal load capacitance different from the crystal manufacturer’s recom-  
mended C may be acceptable. Larger values of C tend to reduce the influence of circuit variations and tolerances on  
L
L
frequency stability. Smaller values of C tend to reduce startup time and crystal power dissipation. Care must however be  
L
taken that C does not fall outside the crystal pulling range or the circuit may fail to start up altogether. It is also possible  
L
to quote C to the crystal manufacturer who can then cut a crystal to order which will resonate, under the specified load  
L
conditions, at the desired frequency.  
Finally the power dissipation in the crystal must be checked. If Pc is too high C1 and C2 must be reduced. If this is not  
feasible C2 alone may be reduced. Unbalancing C1 and C2 will, however, require checking if the loop gain condition is still  
satisfied. This must be done using Equation 1.  
C
C
2
1
Note:  
2 >  
> 0.5  
4.5.1.5  
Oscillator/Clock Application Notes  
On the printed circuit board, the tracks to the crystal and capacitors must be made as short as possible. Other  
signal tracks must not be allowed to cross through this area. The component tracks should preferably be ringed by  
a ground track connected to the chip ground (0V) on adjacent pins either side of the crystal pins. It is also  
advisable to provide a ground plane for the circuit to reduce noise.  
External clock signals, applied to XTI and/or XTO, must not exceed the cell supply limits (i.e., 0V and CVdd) and  
current into or out of XTI and/or XTO must be limited to less than 10mA to avoid damaging the cell’s amplitude  
clamping circuit.  
An external, DC coupled, single ended square wave clock signal may be applied to XTI if OSCMODE = 0. To limit the  
current taken from the signal source a resistor should be placed between the clock source and XTI. The  
recommended value for this series resistor is 470 for a clock signal switching between 0V and CVdd. The  
current the clock source needs to source/sink is then 1.9 mA. The XTO pin must be left unconnected in this  
configuration. See Figure 15.  
AC coupling of a single ended external clock to XTI, with OSCMODE = 0, is not recommended. The duty cycle of the  
25  
Intel Corporation  
Data Sheet  
CE6355  
OSCOUT signal cannot be guaranteed in such a configuration.  
AC coupling of a single ended external clock to XTI, with OSCMODE = 1, is possible. It is recommended that the  
circuit shown in Figure 15 be used to correctly bias the oscillator inputs: The common-mode voltage V for XTI  
CM  
and XTO, (set by the 36 kand 22 kresistors) must be in the range 800 mV to CVdd and the amplitude Vpp of  
the clock signal must be >100 mV. See Figure 15.  
Figure 15 - External Clocking  
External, differential clock signals may be applied to XTI and XTO if OSCMODE = 1. The common-mode voltage V  
CM  
for the differential clock signals must be in the range 800 mV to CVdd, and the peak-to-peak signal amplitude Vpp  
must be >100 mV. It is recommended that differential clock signals have V = 1.0V. For Vpp > 400 mV a resistor  
CM  
of 390 in series with XTI or XTO may be required to limit the current taken from or supplied to the clock  
sources.  
26  
Intel Corporation  
CE6355  
Data Sheet  
5
Application Circuit  
Figure 16 - Typical Application Circuit  
27  
Intel Corporation  
Data Sheet  
CE6355  
28  
Intel Corporation  
配单直通车
WJCE6355882211产品参数
型号:WJCE6355882211
是否Rohs认证: 符合
生命周期:Obsolete
零件包装代码:QFP
包装说明:QFP, QFP64,.35SQ,16
针数:64
Reach Compliance Code:compliant
风险等级:5.83
商用集成电路类型:VIDEO DISCRIMINATOR
JESD-30 代码:S-XQFP-G64
JESD-609代码:e3
功能数量:1
端子数量:64
最高工作温度:85 °C
最低工作温度:-40 °C
封装主体材料:UNSPECIFIED
封装代码:QFP
封装等效代码:QFP64,.35SQ,16
封装形状:SQUARE
封装形式:FLATPACK
峰值回流温度(摄氏度):NOT SPECIFIED
电源:1.8,3.3 V
认证状态:Not Qualified
子类别:Receiver ICs
最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3 V
表面贴装:YES
温度等级:INDUSTRIAL
端子面层:MATTE TIN
端子形式:GULL WING
端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED
Base Number Matches:1
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