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WM8533

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24-bit 192kHz Stereo DAC with 2Vrms Ground Referenced Line Output

DESCRIPTION

FEATURES

The WM8533 is a stereo DAC with integral charge pump and

software control interface. This provides 2Vrms line driver

outputs using a 3.3V power supply rail.



High performance stereo DAC with ground referenced line

driver

Audio performance





106dB SNR (‘A-weighted’)

-89dB THD @ -1dBFS

The device features ground-referenced outputs and the use

of a DC servo to eliminate the need for line driving coupling

capacitors and effectively eliminate power on pops and

clicks.



Digital volume control ranging from -100dB to +12dB

120dB mute attenuation

All common sample rates from 8kHz to 192kHz supported

I²C/SPI compatible and hardware control modes

Data formats: LJ, RJ, I²S, DSP

The device is controlled and configured either via the

I2C/SPI compliant serial control interface or a hardware

control interface.

De-emphasis supported

Maximum 1mV DC offset on line outputs

Pop/click suppressed power up/down sequencer

AVDD and LINEVDD +3.3V ±10% allowing single supply

DBVDD supply supports +1.8V or +3.3V digital I/O

1.842 x 1.772mm 20-ball WCSP

The device supports all common audio sampling rates

between 8kHz and 192kHz using all common MCLK / fs

ratios. Master and slave modes are available and de-

emphasis is also supported.

The WM8533 has a 1.8 to 3.3V tolerant digital interface,

allowing logic up to 3.3V to be connected.

The device is available in a 1.842 x 1.772mm 20-ball WCSP.

APPLICATIONS



Consumer digital audio applications requiring 2Vrms output



Set Top Box

Digital TV

DVD Players

Games Consoles

A/V Receivers

BLOCK DIAGRAM

W

WM8533

CONTROL

INTERFACE

LEFT

DAC

LINEOUTL

LINEREF

MCLK

BCLK

LRCLK

DACDAT

DIGITAL

AUDIO

INTERFACE

DIGITAL

FILTERS

RIGHT

DAC

LINEOUTR

CHARGE PUMP

WOLFSON MICROELECTRONICS plc

Production Data, July 2012, Rev 4.0

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Copyright 2012 Wolfson Microelectronics plc

WM8533

Production Data

TABLE OF CONTENTS

DESCRIPTION....................................................................................................... 1

FEATURES............................................................................................................ 1

APPLICATIONS .................................................................................................... 1

BLOCK DIAGRAM ................................................................................................ 1

TABLE OF CONTENTS......................................................................................... 2

PIN CONFIGURATION.......................................................................................... 3

ORDERING INFORMATION.................................................................................. 3

PIN DESCRIPTION................................................................................................ 4

ABSOLUTE MAXIMUM RATINGS........................................................................ 5

RECOMMENDED OPERATING CONDITIONS..................................................... 5

ELECTRICAL CHARACTERISTICS ..................................................................... 6

TERMINOLOGY............................................................................................................... 7

TYPICAL PERFORMANCE................................................................................... 7

TYPICAL POWER CONSUMPTION................................................................................ 7

SIGNAL TIMING REQUIREMENTS ...................................................................... 8

SYSTEM CLOCK TIMING................................................................................................ 8

AUDIO INTERFACE TIMING – MASTER MODE ............................................................ 9

AUDIO INTERFACE TIMING – SLAVE MODE.............................................................. 10

CONTROL INTERFACE TIMING – I²C MODE .............................................................. 11

CONTROL INTERFACE TIMING – SPI MODE ............................................................. 12

POWER ON RESET ...................................................................................................... 13

DEVICE DESCRIPTION ...................................................................................... 15

INTRODUCTION............................................................................................................ 15

SOFTWARE CONTROL INTERFACE........................................................................... 15

DIGITAL AUDIO INTERFACE........................................................................................ 19

DIGITAL AUDIO INTERFACE CONTROL..................................................................... 21

DIGITAL AUDIO DATA SAMPLING RATES.................................................................. 23

DAC FEATURES............................................................................................................ 24

HARDWARE CONTROL INTERFACE .......................................................................... 28

REGISTER MAP.................................................................................................. 30

REGISTER BITS BY ADDRESS.................................................................................... 31

DIGITAL FILTER CHARACTERISTICS .............................................................. 35

TERMINOLOGY............................................................................................................. 35

DAC FILTER RESPONSES........................................................................................... 36

DIGITAL DE-EMPHASIS CHARACTERISTICS............................................................. 37

RECOMMENDED EXTERNAL COMPONENTS ................................................. 38

RECOMMENDED ANALOGUE LOW PASS FILTER .................................................... 39

RELEVANT APPLICATION NOTES .............................................................................. 39

PACKAGE DIMENSIONS.................................................................................... 40

IMPORTANT NOTICE ......................................................................................... 41

ADDRESS......................................................................................................................41

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PIN CONFIGURATION

1

2

3

4

5

A

LINEOUTR

LINEOUTL

CPVOUTN

CPCB

CPCA

AVDD

B

AGND

VMID

CIFMODE

BCLK

LINEGND

DACDAT

LRCLK

LINEREF

C

D

SCLK/

AIFMODE1

SDA/

AIFMODE0

LINEVDD

CS/MUTE

MCLK

DBVDD

ORDERING INFORMATION

MOISTURE

SENSITIVITY LEVEL

PEAK SOLDERING

TEMPERATURE

DEVICE

RANGE

PACKAGE

20-ball W-CSP

(Pb-free, tape and reel)

WM8533ECSN/R

-40 to +85^oC

MSL1

260^oC

Note:

Reel quantity = 5000

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PIN DESCRIPTION

PIN NO

A1

NAME

AVDD

TYPE

DESCRIPTION

Analogue supply

Right line output

Left line output

Supply

A2

LINEOUTR

LINEOUTL

CPVOUTN

CPCB

Analogue Out

Supply

A3

Charge pump negative rail decoupling pin

Charge pump fly back capacitor pin

Analogue ground

A4

A5

B1

AGND

Ground feedback from output jack

Analogue midrail decoupling pin

Charge pump ground

B2

LINEREF

VMID

Analogue Input

Analogue Out

Supply

B3

B4

LINEGND

CPCA

Charge pump fly back capacitor pin

B5

Analogue Out

HARDWARE

I2C SOFTWARE

MODE

SPI SOFTWARE

MODE

I²C control interface

clock input pin

SPI control interface

clock input pin

SCLK/

AIFMODE [1:0]

00 = 24-bit LJ

01 = 24-bit I2S

10 = 16-bit RJ

11 = 24-bit RJ

C1

C2

C3

Digital I/O

AIFMODE1

I²C interface data input

SPI control interface

data input pin

SDA/

AIFMODE0

0 = select I²C control

interface mode

1 = select SPI control

interface mode

Z = select hardware

mode

Digital In

Tri-Level

CIFMODE

Digital audio interface data input

Charge pump supply

C4

C5

DACDAT

LINEVDD

Digital In

Supply

I²C address select:

0 = Mute enabled

1 = Mute disabled

SPI control interface

chip select

D1

C¯¯S / M¯¯U¯T¯E¯

Digital In

0 = 0x34

1 = 0x36

Master clock

Digital audio interface bit clock

Digital audio interface left/right clock

Digital interface supply (for digital audio and I2C interfaces)

D2

D3

D4

D5

MCLK

BCLK

Digital In

Digital I/O

Supply

LRCLK

DBVDD

Note: Tri-level pins which require the ‘Z’ state to be selected should be left floating (open)

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ABSOLUTE MAXIMUM RATINGS

Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously

operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given

under Electrical Characteristics at the test conditions specified.

ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically

susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling

and storage of this device.

Wolfson tests its package types according to IPC/JEDEC J-STD-020B for Moisture Sensitivity to determine acceptable storage

conditions prior to surface mount assembly. These levels are:

MSL1 = unlimited floor life at <30C / 85% Relative Humidity. Not normally stored in moisture barrier bag.

MSL2 = out of bag storage for 1 year at <30C / 60% Relative Humidity. Supplied in moisture barrier bag.

MSL3 = out of bag storage for 168 hours at <30C / 60% Relative Humidity. Supplied in moisture barrier bag.

The Moisture Sensitivity Level for each package type is specified in Ordering Information.

CONDITION

MIN

-0.3V

MAX

+4.5V

AVDD, LINEVDD, DBVDD

Voltage range digital inputs

Voltage range analogue inputs

Temperature range, T_A

AGND -0.3V

-40°C

DBVDD +0.3V

AVDD +0.3V

+85°C

Storage temperature after soldering

-65°C

+150°C

RECOMMENDED OPERATING CONDITIONS

PARAMETER

SYMBOL

AVDD, LINEVDD

DBVDD

TEST CONDITIONS

MIN

2.97

1.62

TYP

MAX

3.63

UNIT

Analogue supply range

Digital buffer supply range

Ground

3.3

V

AGND, LINEGND

0

Notes

1. Analogue grounds must always be within 0.3V of each other.

2. LINEVDD and AVDD must always be within 0.3V of each other.

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ELECTRICAL CHARACTERISTICS

Test Conditions

LINEVDD=AVDD=3.3V, DBVDD=1.8V, LINEGND=AGND=0V, T_A=+25ºC,

Slave Mode, fs=48kHz, MCLK=256fs, 24-bit data, unless otherwise stated.

PARAMETER

SYMBOL

TEST CONDITIONS

0dBFS

MIN

TYP

MAX

UNIT

Analogue Output

Output Level

1.89

1

2.1

2.31

Vrms

kΩ

Load Impedance

Load Capacitance

No external RC filter

300

1

pF

With filter shown in

Figure 36

µF

DAC Performance

Signal to Noise Ratio

SNR

R_L= 10kΩ

100

106

104

106

-89

-86

dB

A-weighted

R_L= 10kΩ

Un-weighted

Dynamic Range

DNR

THD

R_L= 10kΩ

A-weighted

Total Harmonic Distortion

R_L= 10kΩ

dB

-1dBFS

R_L= 10kΩ

-78

0dBFS

Power Supply Rejection Ratio

(AVDD or LINEVDD)

PSRR

100Hz

1kHz

54

50

95

72

0

dB

20kHz

Channel Separation

1kHz

20Hz to 20kHz

1kHz

System Absolute Phase

Channel Level Matching

Hardware Mute Attenuation

Digital Soft Mute Attenuation

Degrees

dB

0.1

120

100

0

dB

DC Offset at LINEOUTL and

LINEOUTR

+/-1

mV

LINEREF Rejection

1kHz

55

37

dB

20kHz

Digital Logic Levels

Input HIGH Level

V_IH

V_IL

0.7

DBVDD

V

Input LOW Level

Output HIGH Level

Output LOW Level

0.3

DBVDD

V_OH

V_OL

0.9

DBVDD

I_OH= 1mA

I_OL= -1mA

0.1

DBVDD

Input Capacitance

Input Leakage

10

0

pF

+/-0.9

A

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TERMINOLOGY

1. Signal-to-Noise Ratio (dB) – SNR is a measure of the difference in level between the maximum theoretical full scale

output signal and the output with no input signal applied.

2. Total Harmonic Distortion (dB) – THD is the level of the rms value of the sum of harmonic distortion products relative

to the amplitude of the measured output signal.

3. All performance measurements carried out with 20kHz low pass filter, and where noted an A-weighted filter. Failure to

use such a filter will result in higher THD and lower SNR readings than are found in the Electrical Characteristics. The

low pass filter removes out of band noise; although it is not audible it may affect dynamic specification values.

4. Mute Attenuation – This is a measure of the difference in level between the full scale output signal and the output with

mute applied.

TYPICAL PERFORMANCE

TYPICAL POWER CONSUMPTION

Test Conditions

LINEVDD=AVDD=3.3V, DBVDD=1.8V, LINEGND=AGND=0V, T_A=+25°C, Slave Mode, quiescent (no signal)

TEST CONDITIONS

I_AVDD

I_LINEVDD

I_DBVDD

TOTAL

(mA)

(mW)

(mA)

(mW)

(mA)

(mW)

(mA)

(mW)

No clocks applied

Off

0.7

2.31

0.9

2.97

0.05

0.09

1.65

5.37

SYS_ENA [1:0]=00

fs=48kHz, MCLK=256fs

Standby

SYS_ENA [1:0]=01

SYS_ENA [1:0]=11

0.2

4.4

0.66

2.0

6.0

6.6

0.1

0.18

2.3

7.44

34.5

Playback

14.52

19.8

10.5

fs=96kHz, MCLK=256fs

Standby

SYS_ENA [1:0]=01

SYS_ENA [1:0]=11

0.2

4.9

0.66

2.8

8.5

9.24

0.1

0.18

3.1

10.08

44.4

Playback

16.17

28.05

13.5

fs=192kHz, MCLK=128fs

Standby

SYS_ENA [1:0]=01

SYS_ENA [1:0]=11

0.2

4.9

0.66

2.8

8.5

9.24

0.1

0.18

3.1

10.08

44.4

Playback

16.17

28.05

13.5

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SIGNAL TIMING REQUIREMENTS

SYSTEM CLOCK TIMING

Figure 1 System Clock Timing Requirements

Test Conditions

The following timing information is valid across the full range of recommended operating conditions.

PARAMETER

SYMBOL

MIN

TYP

MAX

UNIT

Master Clock Timing Information

MCLK cycle time

t_MCLKY

t_MCLKH

t_MCLKL

27

11

500

ns

%

MCLK high time

MCLK low time

11

MCLK duty cycle (t_MCLKH/t_MCLKL)

40:60

60:40

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AUDIO INTERFACE TIMING – MASTER MODE

Figure 2 Master Mode Digital Audio Data Timing

Test Conditions

The following timing information is valid across the full range of recommended operating conditions.

PARAMETER

SYMBOL

MIN

TYP

MAX

UNIT

Audio Data Input Timing Information

LRCLK propagation delay from BCLK falling edge

DACDAT setup time to BCLK rising edge

DACDAT hold time from BCLK rising edge

t_DL

4

16

ns

t_DST

t_DHT

22

25

Table 1 Master Mode Audio Interface Timing

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AUDIO INTERFACE TIMING – SLAVE MODE

Figure 3 Digital Audio Data Timing – Slave Mode

Test Conditions

The following timing information is valid across the full range of recommended operating conditions.

PARAMETER

SYMBOL

MIN

TYP

MAX

UNIT

Audio Data Input Timing Information

BCLK cycle time

t_BCY

t_BCH

t_BCL

t_LRSU

t_LRH

t_DH

27

11

7

ns

BCLK pulse width high

BCLK pulse width low

LRCLK set-up time to BCLK rising edge

LRCLK hold time from BCLK rising edge

DACDAT hold time from BCLK rising edge

DACDAT set-up time to BCLK rising edge

Table 2 Slave Mode Audio Interface Timing

5

t_DS

7

Note: BCLK period should always be greater than or equal to MCLK period.

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CONTROL INTERFACE TIMING – I²C MODE

I²C mode is selected by driving the CIFMODE pin low.

Figure 4 Control Interface Timing – I²C Control Mode

Test Conditions

The following timing information is valid across the full range of recommended operating conditions.

PARAMETER

Program Register Input Information

SCLK Frequency

SYMBOL

MIN

TYP

MAX

UNIT

400

kHz

ns

SCLK Low Pulse-Width

t₁

t₂

t₃

t₄

t₅

t₆

t₇

t₈

t₉

100

600

100

SCLK High Pulse-Width

Hold Time (Start Condition)

Setup Time (Start Condition)

Data Setup Time

SDA, SCLK Rise Time (see Note)

SDA, SCLK Fall Time

300

Setup Time (Stop Condition)

Data Hold Time

600

2

900

8

Pulse width of spikes that will be suppressed

Table 3 Control Interface Timing – I²C Control Mode

Note: When SCLK frequency ≤ 100kHz, the maximum rise time for SDA and SCLK is increased to 1000ns.

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CONTROL INTERFACE TIMING – SPI MODE

SPI mode is selected by connecting the CIFMODE pin high.

Figure 5 Control Interface Timing – SPI Control Mode

Test Conditions

The following timing information is valid across the full range of recommended operating conditions.

PARAMETER

SYMBOL

MIN

TYP

MAX

UNIT

Program Register Input Information

¯¯

SCLK rising edge to CS falling edge

t_CSU

t_CHO

t_SCY

t_SCL

t_SCH

t_DSU

t_DHO

t_ps

40

160

64

20

40

2

ns

¯¯

SCLK falling edge to CS rising edge

SCLK pulse cycle time

SCLK pulse width low

SCLK pulse width high

SDA to SCLK set-up time

SDA to SCLK hold time

Pulse width of spikes that will be suppressed

Table 4 Control Interface Timing –SPI Control Mode

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POWER ON RESET

Figure 6 Internal Power on Reset Circuit Schematic

The WM8533 includes an internal Power-On-Reset circuit, as shown in Figure 6, which is used to

reset the DAC digital logic into a default state after power up. The POR circuit is powered by AVDD

and has as its inputs VMID and LINEVDD. It asserts POR low if VMID or LINEVDD are below a

minimum threshold.

Figure 7 Typical Power Timing Requirements

Figure 7 shows a typical power-up sequence where LINEVDD comes up with AVDD. When AVDD

goes above the minimum threshold, V_pora, there is enough voltage for the circuit to guarantee POR is

asserted low and the chip is held in reset. In this condition, all writes to the control interface are

ignored. After VMID rises to V_{pord_hi}and AVDD rises to V_{pora_hi,}POR is released high and all registers

are in their default state and writes to the control interface may take place.

On power down, POR is asserted low whenever LINEVDD or AVDD drop below the minimum

threshold V_{pora_low}

.

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Test Conditions

LINEVDD = AVDD = 3.3V, DBVDD = 1.8V, AGND = LINEGND = 0V, T_A= +25ºC

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Power Supply Input Timing Information

VDD level to POR defined

(LINEVDD/AVDD rising)

V_pora

Measured from LINEGND

158

0.8

mV

V

VDD level to POR rising edge

(VMID rising)

V_{pord_hi}

V_{pora_hi}

V_{pora_lo}

0.63

1.44

0.96

1

VDD level to POR rising edge

(LINEVDD/AVDD rising)

1.8

2.18

1.97

V

VDD level to POR falling edge

(LINEVDD/AVDD falling)

1.46

V

Table 5 Power on Reset

Note: All values are simulated results

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DEVICE DESCRIPTION

INTRODUCTION

The WM8533 provides high fidelity, 2V_rmsground referenced stereo line output from a single supply

line with minimal external components. The integrated DC servo eliminates the requirement for

external mute circuitry by minimising DC transients at the output during power up/down. The device

is well-suited to both stereo and multi-channel systems.

The device supports all common audio sampling rates between 8kHz and 192kHz using common

MCLK / fs ratios. Master and slave modes are available.

The WM8533 supports both hardware and software control modes.

In hardware control mode, the digital audio interface format is switchable between 16 to 24bits LJ, RJ

and I²S, and a mute control pin is also available.

In software control modes, the digital audio interface is fully programmable, with two control interface

addresses to allow multiple WM8533 devices to be configured independently.

SOFTWARE CONTROL INTERFACE

Software control mode is selected by logic 1 or 0 on the CIFMODE pin. The logic level is referenced

to the DBVDD power domain. When software mode is selected, the associated multi-function control

pins are defined as described in Table 6.

PIN NAME

DESCRIPTION

REF

SDA

Serial Data Input

Serial Data Clock

I²C Mode - Device Address

C2

C1

D1

SCLK

C¯¯S

SPI Mode - Chip Select

CIFMODE

Control Interface Mode

0 = I²C Mode

C3

1 = SPI Mode

Z = Hardware Mode

Table 6 Software Control Pin Configuration

In software control mode, the WM8533 is controlled by writing to its control registers. Readback is

available for all registers, including device ID and power management status bits, in I²C control mode

only. The control interface can operate as an I²C or SPI control interface: register read-back is

provided on the bi-directional pin SDA in I²C mode. Note that Readback is not available in SPI mode.

The WM8533 software control interface is supplied by the DBVDD power domain.

The available software control interface modes are summarised as follows:



I²C mode uses pins SCLK and SDA.

SPI mode uses pins C¯¯S, SCLK and SDA.

I²C mode is selected by setting the CIFMODE pin to logic 0.

SPI mode is selected by setting the CIFMODE pin to logic 1.

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I²C CONTROL MODE

In I²C mode, the WM8533 is a slave device on the control interface; SCLK is a clock input, while SDA

is a bi-directional data pin. To allow arbitration of multiple slaves (and/or multiple masters) on the

same interface, the WM8533 transmits logic 1 by tri-stating the SDA pin, rather than pulling it high.

An external pull-up resistor is required to pull the SDA line high so that the logic 1 can be recognised

by the master.

In order to allow many devices to share a single I²C control bus, every device on the bus has a

unique 8-bit device ID (this is not the same as the 8-bit address of each register in the WM8533).

¯¯

The device ID is determined by the logic level on the CS pin as shown in Table 7. The LSB of the

device ID is the R/¯W¯ bit; this bit is set to logic 1 for “Read” and logic 0 for “Write”.

¯¯

CS

DEVICE ID

0

1

0011 0100 (34h)

0011 0110 (36h)

Table 7 Control Interface Device ID Selection

The WM8533 operates as an I²C slave device only. The controller indicates the start of data transfer

with a high to low transition on SDA while SCLK remains high. This indicates that a device ID,

register address and data will follow. The WM8533 responds to the start condition and shift in the

next eight bits on SDA (8-bit device ID, including Read/Write bit, MSB first). If the device ID received

matches the device address of the WM8533, then the WM8533 responds by pulling SDA low on the

next clock pulse (ACK). If the device ID is not recognised or the R/¯W¯ bit is set incorrectly, the

WM8533 returns to the idle condition and waits for a new start condition and valid address.

If the device ID matches the device ID of the WM8533, the data transfer continues as described

below. The controller indicates the end of data transfer with a low to high transition on SDA while

SCLK remains high. After receiving a complete address and data sequence the WM8533 returns to

the idle state and waits for another start condition. If a start or stop condition is detected out of

sequence at any point during data transfer (i.e. SDA changes while SCLK is high), the device returns

to the idle condition.

The WM8533 supports the following read and write operations:



Single write

Single read

The sequence of signals associated with a single register write operation is illustrated in Figure 8.

Figure 8 Control Interface I²C Register Write

The sequence of signals associated with a single register read operation is illustrated in Figure 9.

Figure 9 Control Interface I²C Register Read

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Figure 10 Single Register Write to Specified Address

Figure 11 Single Register Read from Specified Address

SPI CONTROL MODE

The WM8533 can also be controlled by writing to registers through a SPI control interface. A control

word consists of 24 bits. The first bit is the read/write bit (R/¯W¯) which must always be 0, which is

followed by 7 address bits (A6 to A0) that determine which control register is accessed. The

remaining 16 bits (B15 to B0) are data bits, corresponding to the 16 bits in each control register.

Volume update registers R06h and R07h are unavailable in SPI control mode. To use volume update

in software control mode, I²C mode must be used.

In SPI mode, every rising edge of SCLK clocks in one data bit from the SDA pin. A rising edge on

C¯¯S latches in a complete control word consisting of the last 24 bits.

The SPI mode write operation protocol is illustrated in Figure 12.

Figure 12 SPI Control Interface – Write operation

In Write operations (R/¯W¯=0), all SDA bits are driven by the controlling device.

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REGISTER RESET

Any write to register R0 (00h) will reset the WM8533. All register bits are reset to their default values.

CHIP ID AND REVISION

Reading from register R0 (00h) returns the Chip ID. Reading from register R1 returns the Chip

revision number.

REGISTER

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R0 (00h)

Chip ID

15:0

CHIP_ID

[15:0]

8523h

DEVICE_ID

Writing to this register resets all registers to

their default state.

Reading from this register will indicate the

Chip ID 8523h.

R1 (01h)

Chip Revision

2:0

CHIP_REV

[2:0]

001

REVISION

Indicates the Chip Revision number

Table 8 Chip ID and Revision Number

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DIGITAL AUDIO INTERFACE

The digital audio interface is used for inputting audio data to the WM8533. The digital audio interface

uses three pins:



DACDAT: DAC data input

LRCLK: Left/Right data alignment clock

BCLK: Bit clock, for synchronisation

MASTER AND SLAVE MODE OPERATION

The WM8533 digital audio interface can operate as a master or as a slave as shown in Figure 13 and

Figure 14.

Figure 13 Slave Mode

Figure 14 Master Mode

INTERFACE FORMATS

The WM8533 supports five different audio data formats:



Left justified

Right justified

I2S

DSP Mode A

DSP Mode B

PCM operation is supported using the DSP mode. All of these modes are MSB first. They are

described in the following sections. Refer to the “Signal Timing Requirements” section for timing

information. Refer to Table 10 for interface control format register settings.

AUDIO DATA FORMATS

In Right Justified mode, the LSB is available on the last rising edge of BCLK before a LRCLK

transition. All other bits are transmitted before (MSB first). Depending on word length, BCLK

frequency and sample rate, there may be unused BCLK cycles after each LRCLK transition.

Figure 15 Right Justified Audio Interface (assuming n-bit word length)

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In Left Justified mode, the MSB is available on the first rising edge of BCLK following a LRCLK

transition. The other bits up to the LSB are then transmitted in order. Depending on word length,

BCLK frequency and sample rate, there may be unused BCLK cycles before each LRCLK transition.

Figure 16 Left Justified Audio Interface (assuming n-bit word length)

In I²S mode, the MSB is available on the second rising edge of BCLK following a LRCLK transition.

The other bits up to the LSB are then transmitted in order. Depending on word length, BCLK

frequency and sample rate, there may be unused BCLK cycles between the LSB of one sample and

the MSB of the next.

Figure 17 I²S Justified Audio Interface (assuming n-bit word length)

In DSP mode, the left channel MSB is available on either the 1^st(mode B) or 2^nd(mode A) rising edge

of BCLK (selectable by AIF_LRCLK_INV) following a rising edge of LRCLK. Right channel data

immediately follows left channel data. Depending on word length, BCLK frequency and sample rate,

there may be unused BCLK cycles between the LSB of the right channel data and the next sample.

In device master mode, the LRCLK output will resemble the frame pulse shown in Figure 18 and

Figure 19. In device slave mode, Figure 20 and Figure 21, it is possible to use any length of frame

pulse less than 1/fs, providing the falling edge of the frame pulse occurs greater than one BCLK

period before the rising edge of the next frame pulse.

Figure 18 DSP Mode Audio Interface (mode A, AIF_LRCLK_INV=0, Master)

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Figure 19 DSP Mode Audio Interface (mode B, AIF_LRCLK_INV=1, Master)

Figure 20 DSP Mode Audio Interface (mode A, AIF_LRCLK_INV=0, Slave)

Figure 21 DSP Mode Audio Interface (mode B, AIF_LRCLK_INV=1, Slave)

DIGITAL AUDIO INTERFACE CONTROL

The control of the audio interface in software mode is achieved by register write. Dynamically

changing the audio data format may cause erroneous operation and is not recommended.

Digital audio data is transferred to the WM8533 via the digital audio interface. The DAC operates in

master or slave mode.

The DAC audio interface requires left/right frame clock (LRCLK) and bit clock (BCLK). These can be

supplied externally (slave mode) or they can be generated internally (master mode). Selection of

master and slave mode is achieved by setting AIF_MSTR bit in Register 3.

The frequency of LRCLK in master mode is dependent upon the DAC master clock frequency and the

AIF_SR [2:0] bits. The frequency of BCLK in master mode can be selected by AIF_BCLKDIV [2:0].

In slave mode, the MCLK to LRCLK ratio can be auto-detected or set manually using the AIF_SR

[2:0] bits.

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REGISTER

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

Master/Slave Select

R3 (03h)

7

AIF_MSTR

0

AIF_CTRL1

0 = Slave

1 = Master

R4 (04h)

BCLK Divider Control (Master Mode)

000 = MCLK/4

5:3

2:0

AIF_BCLKD

IV [2:0]

000

AIF_CTRL2

001 = MCLK/8

010 = 32fs

011 = 64fs

100 = 128fs

101 to 111 = Reserved

MCLK:LRCLK Ratio

000 = Auto detect

001 = 128fs

AIF_SR

[2:0]

010 = 192fs

011 = 256fs

100 = 384fs

101 = 512fs

110 = 768fs

111 = 1152fs

Table 9 DAC Clocking Mode Control

Interface timing is such that the input data and left/right clock are sampled on the rising edge of

BCLK. By setting the appropriate BCLK and LRCLK polarity bits, the WM8533 DAC can sample data

on the opposite clock edges.

The control of audio interface formats and clock polarities is summarised in Table 10.

REGISTER

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R3 (03h)

LRCLK Inversion Control

0 = Normal polarity

6

AIF_LRCLK

_INV

0

AIF_CTRL1

1 = Inverted polarity

When AIF_FMT [1:0]=11 (DSP Mode):

0 = Mode A (2nd clock)

1 = Mode B (1st clock)

BCLK Inversion Control

Slave mode:

5

AIF_BCLK_

INV

0

0 = use rising edge

1 = use falling edge

Master mode:

0 = BCLK normal

1 = BCLK inverted

Audio Data Word Length

00 = 16 bits

4:3

1:0

AIF_WL

[1:0]

10

01 = 20 bits

10 = 24 bits

11 = 32 bits

Audio Data Interface Format

00 = Right justified

01 = Left justified

AIF_FMT

[1:0]

10 = I2S format

11 = DSP mode

Table 10 Audio Interface Control

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DIGITAL AUDIO DATA SAMPLING RATES

The external master clock is applied directly to the MCLK input pin. In a system where there are a

number of possible sources for the reference clock, it is recommended that the clock source with the

lowest jitter be used for the master clock to optimise the performance of the WM8533.

In slave mode the WM8533 has a detection circuit that automatically determines the relationship

between the master clock frequency (MCLK) and the sampling rate (LRCLK), to within ±32 system

clock periods. The MCLK must be synchronised with the LRCLK, although the device is tolerant of

phase variations or jitter on the MCLK.

If the device is configured in slave mode using auto-detect or in hardware mode, and during sample

rate change the ratio between MCLK and LRCLK varies more than once within 1026 LRCLK periods,

then it is recommended that the device be taken into the standby state or the off state before the

sample rate change and held in standby until the sample rate change is complete. This will ensure

correct operation of the detection circuit on the return to the enabled state. For details on the standby

state, please refer to the “Software Control Interface” (software mode, page 15) and “Power Up and

Down Control In Hardware Mode” sections of the datasheet (hardware mode, on page 29).

The DAC supports MCLK to LRCLK ratios of 128fs to 1152fs and sampling rates of 8kHz to 192kHz,

provided the internal signal processing of the DAC is programmed to operate at the correct rate.

Table 11 shows typical master clock frequencies and sampling rates supported by the WM8533 DAC.

MASTER CLOCK (MCLK) FREQUENCY (MHz)

SAMPLE RATE

(LRCLK)

128fs

Unavailable

11.2896

192fs

Unavailable

16.9344

256fs

2.048

384fs

3.072

512fs

4.096

768fs

6.144

1152fs

9.216

8kHz

32kHz

8.192

12.288

16.384

24.576

36.864

44.1kHz

48kHz

11.2896

12.288

16.9344

18.432

22.5792

33.8688

Unavailable

24.576

36.864

88.2kHz

96kHz

22.5792

24.576

33.8688

36.864

Unavailable

12.288

18.432

176.4kHz

192kHz

22.5792

33.8688

Unavailable

24.576

36.864

Table 11 MCLK Frequencies and Audio Sample Rates

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DAC FEATURES

SYSTEM ENABLE

The WM8533 includes a number of enable and disable mechanisms to allow the device to be

powered on and off in a pop-free manner. The SYS_ENA [1:0] control bits enable the DAC and

analogue paths.

REGISTER

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

System Power Control

R2 (02h)

1:0

SYS_ENA

[1:0]

00

PSCTRL1

00 = Off

01 = Power down

10 = Power up (Digital Soft Mute)

11 = Power up (un-muted)

Table 12 System Enable Control

Note: MCLK must be present at all times when using the SYS_ENA [1:0] bits. If MCLK is stopped at

any point the device will power down to the ‘off’ state, but all register settings will remain. Restarting

MCLK will start the device internal power sequence and the device will return to the power state set

by the SYS_ENA [1:0] bits.

The power up and power down sequences are summarised in Figure 22. There is no requirement to

manually cycle the device through the sequence via register writes, as the device will always

automatically step through each stage in the sequence.

Power Up

When SYS_ENA [1:0]=00, the internal clocks are stopped and all analogue and digital blocks are

disabled for maximum power saving. The device starts up in this state in software mode. Setting

SYS_ENA [1:0]=01 enables the internal charge pump and required control circuitry, but the signal

path remains powered down. When SYS_ENA [1:0]=10 all blocks are powered up sequentially and

full system configuration is achieved. Once this is complete, the device is ready to pass audio but is

muted with a digital soft mute. Setting SYS_ENA [1:0]=11 releases the digital soft mute and audio

playback begins.

Power Down

When SYS_ENA [1:0]=11 the device is powered up and passing audio. Changing SYS_ENA

[1:0]=10 applies a digital soft mute to the output, with attenuation of 100dB on the input signal.

Setting SYS_ENA [1:0]=01 sequentially powers down all circuit blocks but leaves the charge pump

and required control circuitry enabled. This state is equivalent to the Hardware Mode mute state, and

will give 120dB attenuation on the input signal. This can be considered the low-power standby state.

Finally, setting SYS_ENA [1:0]=00 will disable all circuit blocks including the charge pump, and full

system initialisation will be required to restart the device.

Figure 22 SYS_ENA [1:0] Power Up and Down Sequences

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DIGITAL VOLUME CONTROL

The WM8533 DAC includes digital volume control, allowing the digital gain to be adjusted between

−100dB and +12dB in 0.25dB steps. Volume update bits allow the user to write both left and right

channel volume changes before the volume is updated.

Note that digital volume control is only available in I²C mode.

REGISTER

ADDRESS

BIT

9

LABEL

DEFAULT

DESCRIPTION

R6 (06h)

DAC Digital Volume Update

DACL_VU

DACR_VU

0

DAC_GAINL

0 = Latch DAC volume setting into Register

Map but do not update volume

1 = Latch DAC volume setting into Register

Map and update left and right channels

simultaneously

R7 (07h)

9

DAC_GAINR

R6 (06h)

DAC Digital Volume

000h = −100dB

8:0

DACL_VOL

[8:0]

190h

DAC_GAINL

001h = −99.75dB

002h = −99.5dB

…0.25dB steps

R7 (07h)

DACR_VOL

[8:0]

DAC_GAINR

190h = 0dB

…0.25dB steps

1BEh = +11.75dB

1BFh to 1FFh = +12dB

Table 13 DAC Digital Volume Control

VOLUME CHANGE MODES

Volume can be adjusted by step change (either using zero cross or not) or by soft ramp. The volume

change mode is controlled by the DAC_VOL_DOWN_RAMP and DAC_VOL_UP_RAMP bits in R5:

REGISTER

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R5 (05h)

DAC Digital Volume Increase Control

0 = Apply volume increases instantly (step)

1 = Ramp volume increases

1

DAC_VOL

_UP_RAM

P

0

DAC_CTRL3

DAC Digital Volume Decrease Control

0 = Apply volume decreases instantly (step)

1 = Ramp volume decreases

0

DAC_VOL

_DOWN_

RAMP

1

Table 14 Volume Ramp Control

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The effect of the volume ramp is illustrated in Figure 23.

Figure 23 Volume Ramp Functionality

Ramp Volume Changes

If ramp volume changes are selected, the ramp rate is dependent upon the sampling rate. The ramp

rates for common audio sample rates are shown in Table 15.

SAMPLE RATE FOR DAC (kHz)

GAIN RAMP RATE

(ms/dB)

1

8

32

0.25

0.18

0.17

0.1

44.1

48

88.2

96

0.08

0.05

0.04

176.4

192

Table 15 Volume Ramp Rate

For example, when using a sample rate of 48kHz, the time taken for a volume change from an initial

setting of 0dB to -20dB is calculated as follows:

Volume Change (dB) x Volume Ramp Rate (ms/dB) = 20 x 0.17 = 3.4ms

Zero cross is not used when ramping. The volume level in the DAC is set by the user in 0.25dB

increments, but during the volume ramp increments of 0.125dB are actually used. This step size is

inaudible and means there is no requirement to wait until a zero crossing occurs. Another benefit of

not using zero cross when ramping is that predictable ramp times are produced – there is no signal

dependency on the ramp time.

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Step Volume Changes and Zero Cross

The step volume control includes optional zero cross functionality. When zero cross is enabled, by

setting DAC_ZC=1, volume changes are not applied until the signal crosses zero so no discontinuity

is seen in the output signal. Zero cross helps to prevent pop and click noise when changing volume

settings and is therefore recommended if using step volume changes.

The zero cross function includes a timeout which forces volume changes if a zero cross event does

not occur. The timeout period is 14400 samples, equivalent to 300ms at 48kHz sample rate.

REGISTER

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R5 (05h)

Zero Cross Enable

4

DAC_ZC

0

DAC_CTRL3

0 = Do not use zero cross

1 = Use zero cross

Table 16 Zero Cross Control

Table 17 gives a summary of the volume mode settings and their effect.

DAC_VOL_

UP_RAMP

DAC_VOL_

DAC_ZC

VOLUME CHANGE

UP

VOLUME CHANGE

DOWN

DOWN_RAMP

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Step, no zero cross

Ramp

Step, no zero cross

Ramp

Step, no zero cross

Ramp

Step, use zero cross Step, use zero cross

Step, use zero cross

Ramp

Step, use zero cross

Ramp

Table 17 Volume Change Summary

MUTE

A digital mute can be applied to left and right channels independently.

REGISTER

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R5 (05h)

Right DAC Mute

3

DACR_MU

TE

0

DAC_CTRL3

0 = Normal operation

1 = Mute

Left DAC Mute

0 = Normal operation

1 = Mute

2

DACL_MUT

E

0

Table 18 DAC Mute Control

The DAC mute function in software mode is controlled by the register settings DAC_VOL_UP_RAMP,

DAC_VOL_DOWN_RAMP and DAC_ZC as described in Table 17.

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DIGITAL MONOMIX CONTROL

The DAC can be set to output a range of mono and stereo options using DAC_OP_MUX [1:0].

REGISTER

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R4 (04h)

DAC Digital Monomix

7:6

DAC_OP_

MUX [1:0]

00

AIF_CTRL2

00 = Stereo (Normal Operation)

01 = Mono (Left data to DACR)

10 = Mono (Right data to DACL)

11 = Digital Monomix, (L+R)/2

Table 19 Digital Monomix Control

DE-EMPHASIS

A digital de-emphasis filter may be applied to the DAC output when the sampling frequency is

44.1kHz. Operation at 48kHz and 32kHz is also possible, but with an increase in the error from the

ideal response. Details of the de-emphasis filter characteristic for 32kHz, 44.1kHz and 48kHz can be

seen in Figure 29 to Figure 34.

REGISTER

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

DAC De-emphasis

R3 (03h)

8

DAC_DEE

MP

0

AIF_CTRL1

0 = No de-emphasis

1 = Apply de-emphasis

Table 20 De-emphasis Control

HARDWARE CONTROL INTERFACE

The WM8533 can be controlled in hardware mode or in software modes. In hardware mode, the

device is configured according to logic levels applied to hardware pins.

Hardware control mode is selected by leaving CIFMODE pin open-circuit (high-impedance). When

hardware mode is selected, the associated multi-function control pins are defined as described in

Table 21.

PIN NAME

DESCRIPTION

AIFMODE0 /

AIFMODE1

AIFMODE0

FORMAT

0

1

0

1

0

1

24-bit Left Justified

24-bit I²S

16-bit Right Justified

24-bit Right Justified

M¯¯U¯T¯E¯

Mute Control

0 = Mute

1 = Normal operation

CIFMODE

Control Interface Mode

0 = I²C Mode

1 = SPI Mode

Z = Hardware Mode

Table 21 Hardware Control Pin Configuration

MUTE

In hardware mode, the M¯¯U¯T¯E¯ pin controls the DAC mute to both left and right channels. When the

mute is asserted a softmute is applied to ramp the signal down, with the ramp rate related to the

sample rate as defined in Table 15 on page 26. When the mute is de-asserted the DAC output

returns to normal in one step.

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POWER UP AND DOWN CONTROL IN HARDWARE MODE

In hardware mode the MCLK, BCLK and M¯¯U¯T¯E¯ pins are monitored to control how the device powers

up or down, and this is summarised in Figure 24 below.

Figure 24 Hardware Power Sequence Diagram

Off to Enable

To power up the device to enabled, start MCLK and BCLK and set M¯¯U¯T¯E¯ = 1.

Off to Standby

To power up the device to standby, start MCLK and BCLK and set M¯¯U¯T¯E¯ = 0. Once the device is in

standby mode, BCLK can be disabled and the device will remain in standby mode.

Standby to Enable

To transition from the standby state to the enabled state, set the M¯¯U¯T¯E¯ pin to logic 1 and start BCLK.

Enable to Standby

To power down to a standby state leaving the charge pump running, either set the M¯¯U¯T¯E¯ pin to logic

0 or stop BCLK. MCLK must continue to run in these situations. The device will automatically mute

and power down quietly in either case.

Note: It is recommended that the device is placed in standby mode before sample rate change if the

sample rate changes more than once in 1026 LRCLK periods, as detailed in “Digital Audio Data

Sampling Rates” on page 23.

Enable to Off

To power down the device completely, stop MCLK at any time. It is recommended that the device is

placed into standby mode as described above before stopping MCLK to allow a quiet shutdown.

For the timing of the off state to enabled state transition (power on to audio out timing), and the

enabled state to standby state transition (the shutdown timing), please refer to WTN0302.

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REGISTER MAP

The complete register map is shown below. The detailed description can be found in the relevant text of the device

description. The WM8533 can be configured using the Control Interface. All unused bits should be set to '0' and access to

unlisted registers should be avoided.

REG

NAME

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

DEFAULT

DEVICE_ID /

SW RESET

R0 (0h)

CHIP_ID [15:0]

8523h

R1 (1h)

R2 (2h)

R3 (3h)

R4 (4h)

0

CHIP_REV [2:0]

REVISION

PSCTRL1

0001h

0000h

1812h

0000h

0

SYS_ENA [1:0]

AIF_FMT [1:0]

DAC_

DEEM

P

AIF_L AIF_B

AIF_M

STR

RCLK_ CLK_I AIF_WL [1:0]

AIF_CTRL1

AIF_CTRL2

INV

NV

DAC_OP_MUX

[1:0]

0

AIF_BCLKDIV [2:0]

AIF_SR [2:0]

DAC_ DAC_

DACR

DAC_

ZC

DACL_ VOL_ VOL_D

MUTE UP_R OWN_

AMP RAMP

R5 (5h)

0

_MUT

E

DAC_CTRL3

0001h

DACL_

VU

R6 (6h)

R7 (7h)

0

DACL_VOL [8:0]

DACR_VOL [8:0]

DAC_GAINL

DAC_GAINR

0190h

DACR

_VU

Table 22 Register Map

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REGISTER BITS BY ADDRESS

REGISTER

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

REFER TO

Chip ID

R0 (00h)

DEVICE_ID/

SW RESET

15:0

CHIP_ID [15:0] 1000_0101_0010_0011

Page 18

Writing to this register resets all registers to

their default state.

Reading from this register will indicate the

Chip ID 8523h.

Register 00h DEVICE_ID / SW RESET

REGISTER

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

REFER TO

Chip Revision

R1 (01h)

2:0

CHIP_REV [2:0]

001

Page 18

REVISION

Indicates the Chip Revision number

Register 01h REVISION

REGISTER

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

REFER TO

System Power Control

00 = Off

R2 (02h)

PSCTRL1

1:0

SYS_ENA [1:0]

00

Page 24

01 = Power down

10 = Power up (muted)

11 = Power up (unmuted)

Register 02h PSCTRL1

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REGISTER

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

DAC De-emphasis Control

REFER TO

R3 (03h)

AIF_CTRL1

8

DAC_DEEMP

0

Page 28

Page 21

0 = No de-emphasis

1 = De-emphasis enabled

Master/Slave Select

0 = Slave mode

7

6

AIF_MSTR

0

1 = Master mode

LRCLK Inversion Control

0 = Normal polarity

AIF_LRCLK_INV

1 = Inverted polarity

When AIF_FMT [1:0]=11 (DSP Mode):

0 = Mode A (2nd clock)

1 = Mode B (1st clock)

BCLK Inversion Control

Slave mode:

5

AIF_BCLK_INV

0

Page 21

0 = Use rising edge

1 = Use falling edge

Master mode:

0 = BCLK normal

1 = BCLK inverted

Audio Data Word Length

00 = 16 bits

4:3

AIF_WL [1:0]

10

Page 21

01 = 20 bits

10 = 24 bits

11 = 32 bits

Reserved

2

Reserved

0

Audio Data Interface Format

00 = Right justified

01 = Left justified

10 = I²S format

2:0

AIF_FMT [1:0]

10

11 = DSP mode

Register 03h AIF_CTRL1

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REGISTER

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

Digital Monomix Control

REFER TO

R4 (04h)

AIF_CTRL2

7:6

DAC_OP_MUX

[1:0]

00

Page 28

00 = Stereo (Normal operation)

01 = Mono (Left data to DACR)

10 = Mono (Right data to DACL)

11 = Digital Monomix, (L+R)/2

BCLK Divider Control (Master Mode)

000 = MCLK/4

5:3

2:0

AIF_BCLKDIV

[2:0]

000

Page 21

001 = MCLK/8

010 = 32fs

011 = 64fs

100 = 128fs

101 to 111 = Reserved

MCLK:LRCLK Ratio

000 = Auto detect

001 = 128fs

AIF_SR [2:0]

Page 21

010 = 192fs

011 = 256fs

100 = 384fs

101 = 512fs

110 = 768fs

111 = 1152fs

Register 04h AIF_CTRL2

REGISTER

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

REFER TO

Zero Cross Enable

0 = Do not use zero cross

1 = Use zero cross

R5 (05h)

DAC_CTRL3

4

DAC_ZC

0

Page 25

Right DAC Mute

0 = Normal operation

1 = Mute

3

2

1

0

DACR_MUTE

DACL_MUTE

0

1

Page 27

Page 25

Left DAC Mute

0 = Normal operation

1 = Mute

DAC Digital Volume Increase Control

0 = Apply volume increases instantly (step)

1 = Ramp volume increases

DAC_VOL_

UP_RAMP

DAC Digital Volume Decrease Control

0 = Apply volume decreases instantly (step)

1 = Ramp volume decreases

DAC_VOL_

DOWN_RAMP

Register 05h DAC_CTRL3

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REGISTER

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

REFER TO

Left DAC Digital Volume Update

R6 (06h)

DAC_GAINL

9

DACL_VU

0

Page 25

0 = Latch Left DAC volume setting into register map

but do not update volume

1 = Latch Left DAC volume setting into register map

and update left and right channels simultaneously

Left DAC Digital Volume Control

000h = -100dB

8:0

DACL_VOL [8:0] 1_1001_0000

001h = -99.75dB

002h = -99.5dB

…0.25dB steps

190h = 0dB

…0.25dB steps

1BEh = +11.75dB

1BFh to 1FFh = +12dB

Register 06h DAC_GAINL

REGISTER

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

REFER TO

Right DAC Digital Volume Update

0 = Latch Right DAC volume setting into register

map but do not update volume

R7 (07h)

DAC_GAINR

9

DACR_VU

0

Page 25

1 = Latch Right DAC volume setting into register

map and update left and right channels

simultaneously

Right DAC Digital Volume Control

000h = -100dB

8:0

DACR_VOL

[8:0]

1_1001_0000

Page 25

001h = -99.75dB

002h = -99.5dB

…0.25dB steps

190h = 0dB

…0.25dB steps

1BEh = +11.75dB

1BFh to 1FFh = +12dB

Register 07h DAC_GAINR

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DIGITAL FILTER CHARACTERISTICS

PARAMETER

TEST CONDITIONS

MIN

TYP

14.5fs

6.5fs

MAX

UNIT

DAC Filter – 256fs to 1152fs

Passband

 0.1dB

f > 0.546fs

 0.1dB

0.454fs

0.1

Passband Ripple

Stopband

dB

0.546fs

-50

Stopband attenuation

Group Delay

DAC Filter – 128fs and 192fs

Passband

0.247fs

0.1

Passband Ripple

Stopband

dB

0.753fs

-50

Stopband attenuation

Group Delay

f > 0.753fs

TERMINOLOGY

1. Stop Band Attenuation (dB) – the degree to which the frequency spectrum is attenuated (outside audio band)

2. Pass-band Ripple – any variation of the frequency response in the pass-band region

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WM8533

Production Data

DAC FILTER RESPONSES

0.2

0.15

0.1

0

-20

0.05

0

-40

-60

-0.05

-0.1

-0.15

-0.2

-80

-100

-120

0

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0.4

0.45

0.5

Frequency (Fs)

0

0.5

1

1.5

2

2.5

3

Frequency (Fs)

Figure 25 DAC Digital Filter Frequency Response

– 256fs to 1152fs Clock Modes

Figure 26 DAC Digital Filter Ripple – 256fs to 1152fs Clock

Modes

0.2

0

-20

-0.2

-0.4

-0.6

-0.8

-1

-40

-60

-80

0

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0.4

0.45

0.5

-100

Frequency (Fs)

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

Frequency (Fs)

Figure 27 DAC Digital Filter Frequency Response

– 128fs and 192fs Clock Modes

Figure 28 DAC Digital Filter Ripple – 128fs to 192fs Clock

Modes

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Production Data

WM8533

DIGITAL DE-EMPHASIS CHARACTERISTICS

0

1

0.5

0

-2

-4

-0.5

-1

-6

-1.5

-2

-8

-2.5

-3

-10

0

2

4

6

8

10

12

14

16

0

2

4

6

8

10

12

14

16

Frequency (kHz)

Figure 29 De-Emphasis Frequency Response (32kHz)

Figure 30 De-Emphasis Error (32kHz)

Figure 31 De-Emphasis Frequency Response (44.1kHz)

Figure 32 De-Emphasis Error (44.1kHz)

0

1

0.8

0.6

0.4

0.2

0

-2

-4

-6

-0.2

-0.4

-0.6

-0.8

-1

-8

-10

0

5

10

15

20

0

5

10

15

20

Frequency (kHz)

Figure 33 De-Emphasis Frequency Response (48kHz)

Figure 34 De-Emphasis Error (48kHz)

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WM8533

Production Data

RECOMMENDED EXTERNAL COMPONENTS

Figure 35 Recommended External Components

Notes:

1. Wolfson recommend using a single, common ground plane. Where this is not possible, care should be taken to

optimise split ground configuration for audio performance.

2. Charge Pump fly-back capacitor C5 should be placed as close to WM8533 as possible, followed by Charge Pump

decoupling capacitor C1, then LINEVDD and VMID decoupling capacitors.

3. Capacitor types should be chosen carefully. Capacitors with very low ESR are recommended for optimum

performance.

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Production Data

WM8533

RECOMMENDED ANALOGUE LOW PASS FILTER

Figure 36 Recommended Analogue Low Pass Filter (one channel shown)

An external single-pole RC filter is recommended if the device is driving a wideband amplifier. Other

filter architectures may provide equally good results.

The filter shown in Figure 36 has a -3dB cut-off at 105.26kHz and a droop of 0.15dB at 20kHz. The

typical output from the WM8533 is 2.1Vrms – when a 10kΩ load is placed at the output of this

recommended filter the amplitude across this load is 1.99Vrms.

RELEVANT APPLICATION NOTES

The following application notes, available from www.wolfsonmicro.com, may provide additional

guidance for use of the WM8533.

DEVICE PERFORMANCE:

WAN0129 – Decoupling and Layout Methodology for Wolfson DACs, ADCs and CODECs

WAN0144 – Using Wolfson Audio DACs and CODECs with Noisy Supplies

WTN0302 - WM8524 Recommended Power Sequence and Timing (for hardware mode)

GENERAL:

WAN0108 – Moisture Sensitivity Classification and Plastic IC Packaging

WAN0109 – ESD Damage in Integrated Circuits: Causes and Prevention

WAN0158 – Lead-Free Solder Profiles for Lead-Free Components

WAN0161 – Electronic End-Product Design for ESD

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WM8533

Production Data

PACKAGE DIMENSIONS

B: 20 BALL W-CSP PACKAGE 1.842 X 1.772 X 0.451mm BODY, 0.35 mm BALL PITCH

DM107.A

6

A

D

A

2

DETAIL 1

5

4

3

2

1

A2

A1

CORNER

A

4

B

C

5

e

E1

E

D

aaa

B

2 X

B

M

ddd Z A B

aaa

A

e

DETAIL 2

TOP VIEW

D1

BOTTOM VIEW

f1

SOLDER BALL

f2

bbb

Z

h

1

Z

ccc

A1

Z

DETAIL 1

DETAIL 2

Dimensions (mm)

Symbols

A

NOM

0.451

0.172

0.279

1.842

MIN

MAX

0.481

0.198

0.292

1.867

NOTE

0.421

0.146

A1

A2

0.266

1.817

D

D1

1.400 BSC

1.772

1.747

E

E1

e

1.797

1.050 BSC

0.350 BSC

0.221

5

f1

0.2085

0.3485

0.175

0.361

f2

h

0.205

0.235

aaa

bbb

ccc

0.025

0.060

0.030

0.015

ddd

NOTES:

1. PRIMARY DATUM -Z- AND SEATING PLANE ARE DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS.

2. THIS DIMENSION INCLUDES STAND-OFF HEIGHT ‘A1’.

3. A1 CORNER IS IDENTIFIED BY INK/LASER MARK ON TOP PACKAGE.

4. BILATERAL TOLERANCE ZONE IS APPLIED TO EACH SIDE OF THE PACKAGE BODY.

5. ‘e’ REPRESENTS THE BASIC SOLDER BALL GRID PITCH.

6. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE.

7. FOLLOWS JEDEC DESIGN GUIDE MO-211-C.

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Production Data

WM8533

IMPORTANT NOTICE

Wolfson Microelectronics plc (“Wolfson”) products and services are sold subject to Wolfson’s terms and conditions of sale,

delivery and payment supplied at the time of order acknowledgement.

Wolfson warrants performance of its products to the specifications in effect at the date of shipment. Wolfson reserves the

right to make changes to its products and specifications or to discontinue any product or service without notice. Customers

should therefore obtain the latest version of relevant information from Wolfson to verify that the information is current.

Testing and other quality control techniques are utilised to the extent Wolfson deems necessary to support its warranty.

Specific testing of all parameters of each device is not necessarily performed unless required by law or regulation.

In order to minimise risks associated with customer applications, the customer must use adequate design and operating

safeguards to minimise inherent or procedural hazards. Wolfson is not liable for applications assistance or customer

product design. The customer is solely responsible for its selection and use of Wolfson products. Wolfson is not liable for

such selection or use nor for use of any circuitry other than circuitry entirely embodied in a Wolfson product.

Wolfson’s products are not intended for use in life support systems, appliances, nuclear systems or systems where

malfunction can reasonably be expected to result in personal injury, death or severe property or environmental damage.

Any use of products by the customer for such purposes is at the customer’s own risk.

Wolfson does not grant any licence (express or implied) under any patent right, copyright, mask work right or other

intellectual property right of Wolfson covering or relating to any combination, machine, or process in which its products or

services might be or are used. Any provision or publication of any third party’s products or services does not constitute

Wolfson’s approval, licence, warranty or endorsement thereof. Any third party trade marks contained in this document

belong to the respective third party owner.

Reproduction of information from Wolfson datasheets is permissible only if reproduction is without alteration and is

accompanied by all associated copyright, proprietary and other notices (including this notice) and conditions. Wolfson is

not liable for any unauthorised alteration of such information or for any reliance placed thereon.

Any representations made, warranties given, and/or liabilities accepted by any person which differ from those contained in

this datasheet or in Wolfson’s standard terms and conditions of sale, delivery and payment are made, given and/or

accepted at that person’s own risk. Wolfson is not liable for any such representations, warranties or liabilities or for any

reliance placed thereon by any person.

ADDRESS

Wolfson Microelectronics plc

Westfield House

26 Westfield Road

Edinburgh

EH11 2QB

Tel :: +44 (0)131 272 7000

Fax :: +44 (0)131 272 7001

Email :: sales@wolfsonmicro.com

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型号:	WM8524GEDT/R
生命周期：	Transferred
Reach Compliance Code：	unknown
风险等级：	5.59
Base Number Matches：	1

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