欢迎访问ic37.com |
会员登录 免费注册
发布采购
所在地: 型号: 精确
  • 批量询价
  •  
  • 供应商
  • 型号
  • 数量
  • 厂商
  • 封装
  • 批号
  • 交易说明
  • 询价
  •  
  • 北京元坤伟业科技有限公司

         该会员已使用本站17年以上

  • WM8740SEDS/RV
  • 数量-
  • 厂家-
  • 封装-
  • 批号-
  • -
  • QQ:857273081QQ:857273081 复制
    QQ:1594462451QQ:1594462451 复制
  • 010-62104931、62106431、62104891、62104791 QQ:857273081QQ:1594462451
更多
  • WM8740SEDS/RV图
  • 深圳市拓亿芯电子有限公司

     该会员已使用本站12年以上
  • WM8740SEDS/RV 现货库存
  • 数量21000 
  • 厂家WOLFSON 
  • 封装SSOP28 
  • 批号23+ 
  • 代理原装现货,价格优势
  • QQ:1774550803QQ:1774550803 复制
    QQ:2924695115QQ:2924695115 复制
  • 0755-82777855 QQ:1774550803QQ:2924695115
  • WM8740SEDS/RV图
  • 深圳市欧昇科技有限公司

     该会员已使用本站2年以上
  • WM8740SEDS/RV 现货库存
  • 数量2724 
  • 厂家WOLFSON 
  • 封装SSOP28 
  • 批号18+19+ 
  • 原装原包诺德讯只做原装货
  • QQ:2885514619QQ:2885514619 复制
  • 0755-89345486 QQ:2885514619
  • WM8740SEDS/RV图
  • 集好芯城

     该会员已使用本站13年以上
  • WM8740SEDS/RV
  • 数量16830 
  • 厂家WOLFSON 
  • 封装SSOP28 
  • 批号最新批次 
  • 原装原厂 现货现卖
  • QQ:3008092965QQ:3008092965 复制
    QQ:3008092965QQ:3008092965 复制
  • 0755-83239307 QQ:3008092965QQ:3008092965
  • WM8740SEDS/RV图
  • 深圳市宏诺德电子科技有限公司

     该会员已使用本站8年以上
  • WM8740SEDS/RV
  • 数量68000 
  • 厂家WLF 
  • 封装SSOP28 
  • 批号22+ 
  • 全新进口原厂原装,优势现货库存,有需要联系电话:18818596997 QQ:84556259
  • QQ:84556259QQ:84556259 复制
    QQ:783839662QQ:783839662 复制
  • 0755- QQ:84556259QQ:783839662
  • WM8740SEDS/RV图
  • 深圳市华斯顿电子科技有限公司

     该会员已使用本站16年以上
  • WM8740SEDS/RV
  • 数量28535 
  • 厂家WOLFSON 
  • 封装SSOP28 
  • 批号2023+ 
  • 绝对原装正品现货,全新深圳原装进口现货
  • QQ:364510898QQ:364510898 复制
    QQ:515102657QQ:515102657 复制
  • 0755-83777708“进口原装正品专供” QQ:364510898QQ:515102657
  • WM8740SEDS/RV图
  • 深圳市集创讯科技有限公司

     该会员已使用本站5年以上
  • WM8740SEDS/RV
  • 数量9500 
  • 厂家WOLFSON 
  • 封装SSOP28 
  • 批号24+ 
  • 原装进口正品现货,假一罚十价格优势
  • QQ:2885393494QQ:2885393494 复制
    QQ:2885393495QQ:2885393495 复制
  • 0755-83244680 QQ:2885393494QQ:2885393495
  • WM8740SEDS/RV图
  • 深圳市华芯盛世科技有限公司

     该会员已使用本站13年以上
  • WM8740SEDS/RV
  • 数量865000 
  • 厂家WOLFSON 
  • 封装原厂封装 
  • 批号最新批号 
  • 一级代理,原装特价现货!
  • QQ:2881475757QQ:2881475757 复制
  • 0755-83225692 QQ:2881475757
  • WM8740SEDS/RV图
  • 深圳市芯福林电子有限公司

     该会员已使用本站15年以上
  • WM8740SEDS/RV
  • 数量13880 
  • 厂家Cirrus Logic Inc. 
  • 封装28SSOP 
  • 批号21+ 
  • 公司只售原装 支持实单
  • QQ:2881495751QQ:2881495751 复制
  • 0755-88917743 QQ:2881495751
  • WM8740SEDS/RV图
  • 深圳市得捷芯城科技有限公司

     该会员已使用本站11年以上
  • WM8740SEDS/RV
  • 数量6513 
  • 厂家WOLFSON 
  • 封装NA/ 
  • 批号23+ 
  • 原厂直销,现货供应,账期支持!
  • QQ:3007977934QQ:3007977934 复制
    QQ:3007947087QQ:3007947087 复制
  • 0755-82546830 QQ:3007977934QQ:3007947087
  • WM8740SEDS/RV图
  • 深圳市惊羽科技有限公司

     该会员已使用本站11年以上
  • WM8740SEDS/RV
  • 数量6328 
  • 厂家CIRRUS 
  • 封装TSSOP-28 
  • 批号▉▉:2年内 
  • ▉▉¥63.4元一有问必回一有长期订货一备货HK仓库
  • QQ:43871025QQ:43871025 复制
  • 131-4700-5145---Q-微-恭-候---有-问-秒-回 QQ:43871025
  • WM8740SEDS/RV图
  • 深圳市金嘉锐电子有限公司

     该会员已使用本站14年以上
  • WM8740SEDS/RV
  • 数量28620 
  • 厂家Cirrus 
  • 封装28-SSOP 
  • 批号24+ 
  • 【原装优势★★★绝对有货】
  • QQ:2643490444QQ:2643490444 复制
  • 0755-22929859 QQ:2643490444
  • WM8740SEDS/RV图
  • 深圳市中杰盛科技有限公司

     该会员已使用本站14年以上
  • WM8740SEDS/RV
  • 数量12000 
  • 厂家Wolfson 
  • 封装原厂原装 
  • 批号24+ 
  • 【原装优势★★★绝对有货】
  • QQ:409801605QQ:409801605 复制
  • 0755-22968359 QQ:409801605
  • WM8740SEDS/RV图
  • 深圳市能元时代电子有限公司

     该会员已使用本站10年以上
  • WM8740SEDS/RV
  • 数量10000 
  • 厂家WOLFSON 
  • 封装SSOP28 
  • 批号24+ 
  • 只做原装进口现货假一赔十!公司原装现货!
  • QQ:2885637848QQ:2885637848 复制
    QQ:2885658492QQ:2885658492 复制
  • 0755-84502810 QQ:2885637848QQ:2885658492
  • WM8740SEDS/RV图
  • 深圳市凯信扬科技有限公司

     该会员已使用本站7年以上
  • WM8740SEDS/RV
  • 数量6654 
  • 厂家WOLFSON 
  • 封装SSOP28 
  • 批号20+ 
  • 现货库存,欢迎来询,低价出售
  • QQ:872328909QQ:872328909 复制
  • 0755-82518059 QQ:872328909
  • WM8740SEDS/RV图
  • 深圳市宏世佳电子科技有限公司

     该会员已使用本站13年以上
  • WM8740SEDS/RV
  • 数量3685 
  • 厂家WOLFSON 
  • 封装SSOP-28 
  • 批号2023+ 
  • 全新原厂原装产品、公司现货销售
  • QQ:2881894392QQ:2881894392 复制
    QQ:2881894393QQ:2881894393 复制
  • 0755- QQ:2881894392QQ:2881894393
  • WM8740SEDS/RV图
  • 昂富(深圳)电子科技有限公司

     该会员已使用本站4年以上
  • WM8740SEDS/RV
  • 数量32222 
  • 厂家WOLFSON/欧胜 
  • 封装SSOP28 
  • 批号23+ 
  • 一站式BOM配单,短缺料找现货,怕受骗,就找昂富电子.
  • QQ:GTY82dX7
  • 0755-23611557【陈妙华 QQ:GTY82dX7
  • WM8740SEDS/RV图
  • 深圳市亿智腾科技有限公司

     该会员已使用本站8年以上
  • WM8740SEDS/RV
  • 数量16680 
  • 厂家WOLFSON 
  • 封装SSOP28 
  • 批号16+ 
  • 假一赔十★全新原装现货★★特价供应★工厂客户可放款
  • QQ:799387964QQ:799387964 复制
    QQ:2777237833QQ:2777237833 复制
  • 0755-82566711 QQ:799387964QQ:2777237833
  • WM8740SEDS/RV图
  • 深圳市昌和盛利电子有限公司

     该会员已使用本站11年以上
  • WM8740SEDS/RV
  • 数量12568 
  • 厂家WOLFSON 
  • 封装SSOP28 
  • 批号▊ NEW ▊ 
  • ▊▊【100%全新原装正品】★长期供应,量大可订!价格优惠!
  • QQ:1551106297QQ:1551106297 复制
    QQ:3059638860QQ:3059638860 复制
  • 0755-23125986 QQ:1551106297QQ:3059638860
  • WM8740SEDS/RV图
  • 深圳市特拉特科技有限公司

     该会员已使用本站2年以上
  • WM8740SEDS/RV
  • 数量15000 
  • 厂家WOLFSON 
  • 封装SSOP 
  • 批号22+ 
  • 一级代理,公司优势产品,可开增值票
  • QQ:709809857QQ:709809857 复制
  • 0755-82531732 QQ:709809857
  • WM8740SEDS/RV图
  • 万三科技(深圳)有限公司

     该会员已使用本站2年以上
  • WM8740SEDS/RV
  • 数量6500000 
  • 厂家CIRRUS 
  • 封装原厂原装 
  • 批号22+ 
  • 万三科技 秉承原装 实单可议
  • QQ:3008962483QQ:3008962483 复制
  • 0755-23763516 QQ:3008962483
  • WM8740SEDS/RV图
  • 深圳市英信达电子有限公司

     该会员已使用本站14年以上
  • WM8740SEDS/RV
  • 数量8774 
  • 厂家WOLFSON 
  • 封装SSOP28 
  • 批号2016+ 
  • 全新原装现货
  • QQ:429657504QQ:429657504 复制
    QQ:147087677QQ:147087677 复制
  • 755-82539350 QQ:429657504QQ:147087677
  • WM8740SEDS/RV图
  • 深圳市科雨电子有限公司

     该会员已使用本站9年以上
  • WM8740SEDS/RV
  • 数量932 
  • 厂家CIRRUS 
  • 封装SSOP-28 
  • 批号24+ 
  • ★体验愉快问购元件!!就找我吧!单价:85元
  • QQ:97877805QQ:97877805 复制
  • 171-4729-0036(微信同号) QQ:97877805

产品型号WM8740SEDS/RV的概述

WM8740SEDS/RV概述 WM8740是一款高性能的立体声数模转换器(DAC),由Wolfson Microelectronics公司(现为Cirrus Logic的一部分)生产。该芯片以其卓越的音质和出色的动态范围,在高保真音频设备中得到了广泛应用。WM8740能够支持多种数据格式,包括I2S和左对齐格式,提供24位精度和192kHz的采样率,使其适合用于CD播放机、音频接收器和其他高端音频设备。 芯片详细参数 基本特性 - 采样率:最大192kHz - 分辨率:24位 - 动态范围:高达112dB - 总谐波失真+噪声(THD+N):-100dB(0.001%) - 工作电压:1.8V至5V - 功耗:50mW(典型值) 数字接口 - 支持I2S接口和右对齐接口 - 数据输入类型:PCM格式 模拟性能 - 输出电压范围:2.0V(使用外部放大器) - 通过比率转换能处理...

产品型号WM8740SEDS/RV的Datasheet PDF文件预览

WM8740  
w
24-bit, High Performance 192kHz Stereo DAC  
DESCRIPTION  
FEATURES  
120dB SNR (‘A’ weighted mono @48kHz), THD+N: -104dB  
@ FS  
117dB SNR (‘A’ weighted stereo @48kHz), THD+N: -104dB  
@ FS  
Sampling frequency: 8kHz to 192kHz  
Selectable digital filter roll-off  
Optional interface to industry standard external filters  
Differential mono mode needing no glue logic  
Input data word: 16 to 24-bit  
The WM8740 is a very high performance stereo DAC  
designed for audio applications such as CD, DVD, home  
theatre systems, set top boxes and digital TV. The WM8740  
supports data input word lengths from 16 to 24-bits and  
sampling rates up to 192kHz. The WM8740 consists of a  
serial interface port, digital interpolation filter, multi-bit sigma  
delta modulator and stereo DAC in a small 28-pin SSOP  
package. The WM8740 also includes a digitally controllable  
mute and attenuator function on each channel.  
Hardware or SPI compatible serial port control modes:  
The internal digital filter has two selectable roll-off  
characteristics. A sharp or slow roll-off can be selected  
dependent on application requirements. Additionally, the  
internal digital filter can be by-passed and the WM8740  
used with an external digital filter.  
-
-
Hardware mode: mute, de-emphasis, audio format  
control  
Serial mode: mute, de-emphasis, attenuation (256  
steps), phase reversal  
Fully differential voltage outputs  
The WM8740 supports two connection schemes for audio  
DAC control. The SPI-compatible serial control port  
provides access to a wide range of features including on-  
chip mute, attenuation and phase reversal. A hardware  
controllable interface is also available.  
APPLICATIONS  
CD, DVD audio  
Home theatre systems  
Professional audio systems  
BLOCK DIAGRAM  
WOLFSON MICROELECTRONICS plc  
Prouction Dta, April 2010, Rev 4.4  
To receive regular email updates, sign up at http://www.wolfsonmicro.com/enews  
Copyright ©2010 Wolfson Microelectronics plc  
WM8740  
Production Data  
TABLE OF CONTENTS  
DESCRIPTION .......................................................................................................1  
FEATURES.............................................................................................................1  
APPLICATIONS .....................................................................................................1  
BLOCK DIAGRAM .................................................................................................1  
TABLE OF CONTENTS .........................................................................................2  
PIN CONFIGURATION...........................................................................................3  
ORDERING INFORMATION ..................................................................................3  
PIN DESCRIPTION ................................................................................................4  
ABSOLUTE MAXIMUM RATINGS.........................................................................5  
RECOMMENDED OPERATING CONDITIONS .....................................................6  
ELECTRICAL CHARACTERISTICS ......................................................................6  
INTERNAL POWER ON RESET CIRCUIT ............................................................9  
DEVICE DESCRIPTION.......................................................................................12  
SYSTEM CLOCK ........................................................................................................ 12  
AUDIO DATA INTERFACE ......................................................................................... 12  
NORMAL SAMPLE RATE ........................................................................................... 13  
8 X FS INPUT SAMPLE RATE.................................................................................... 14  
MODES OF OPERATION ........................................................................................... 14  
HARDWARE CONTROL MODES ............................................................................... 14  
SOFTWARE CONTROL INTERFACE......................................................................... 15  
REGISTER MAP ......................................................................................................... 16  
MUTE MODES ............................................................................................................ 20  
FILTER RESPONSES................................................................................................. 21  
APPLICATIONS INFORMATION .........................................................................24  
RECOMMENDED EXTERNAL COMPONENTS.......................................................... 24  
RECOMMENDED EXTERNAL COMPONENTS VALUES........................................... 24  
SUGGESTED DIFFERENTIAL OUTPUT FILTER CIRCUIT........................................ 25  
RECOMMENDED DUAL DIFFERENTIAL HARDWARE SETUP................................. 25  
PACKAGE DIMENSIONS ....................................................................................26  
ADDRESS: .................................................................................................................. 27  
PD, Rev 4.4, April 2010  
w
2
WM8740  
Production Data  
PIN CONFIGURATION  
ML/I2S  
LRCIN  
DIN  
1
2
3
4
5
6
7
8
9
10  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
MC/DM1  
MD/DM0  
MUTEB  
MODE  
BCKIN  
MODE8X  
SCLK  
DIFFHW  
DGND  
CSBIWO  
RSTB  
DVDD  
ZERO  
AVDDR  
AGNDR  
VMIDR  
AVDDL  
AGNDL  
VMIDL  
11  
12  
13  
14  
VOUTLP  
VOUTLN  
AVDD  
VOUTRP  
VOUTRN  
AGND  
ORDERING INFORMATION  
TEMPERATURE  
MOISTURE  
SENSITIVITY LEVEL  
PEAK SOLDERING  
TEMPERATURE  
DEVICE  
RANGE  
PACKAGE  
WM8740SEDS/V  
WM8740SEDS/RV  
-40° to +85°C  
-40° to +85°C  
28-pin SSOP  
28-pin SSOP  
MSL2  
MSL2  
260°C  
260°C  
Note:  
Reel Quantity: 2,000  
PD, Rev 4.4, April 2010  
3
w
WM8740  
Production Data  
PIN DESCRIPTION  
PIN  
1
NAME  
LRCIN  
DIN  
TYPE  
Digital input  
Digital input  
Digital input  
Digital input  
Digital input  
Digital input  
Supply  
DESCRIPTION  
Sample rate clock input.  
2
Audio data serial input (except in 8XMODE when it is DINL).  
Audio data bit clock input .  
3
BCKIN  
MODE8X  
SCLK  
4
Internal pull-down, active high, 8 x fs mode.  
System clock input.  
5
6
DIFFHW  
DGND  
DVDD  
Internal pull-down, active high, differential mono mode.  
Digital ground supply.  
7
8
Supply  
Digital positive supply.  
9
AVDDR  
AGNDR  
VMIDR  
Supply  
Analogue positive supply.  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
Supply  
Analogue ground supply.  
Analogue output  
Mid rail right channel.  
VOUTRP Analogue output  
VOUTRN Analogue output  
Right channel DAC output positive.  
Right channel DAC output negative.  
Analogue ground supply.  
AGND  
AVDD  
Supply  
Supply  
Analogue positive supply.  
VOUTLN Analogue output  
VOUTLP Analogue output  
Left channel DAC output negative.  
Left channel DAC output positive.  
Mid rail left channel.  
VMIDL  
AGNDL  
AVDDL  
ZERO  
Analogue output  
Supply  
Analogue ground supply.  
Supply  
Analogue positive supply.  
Digital output  
Digital input  
Infinite zero detect – active low. Open drain type output with active pull-down.  
Reset input – active low. Internal pull-up.  
RSTB  
PD, Rev 4.4, April 2010  
w
4
WM8740  
Production Data  
PIN  
NAME  
TYPE  
DESCRIPTION  
Hardware Mode  
Normal Mode  
Software  
Mode  
Differential Mode  
8X Mode  
Wordlength:  
Wordlength:  
Wordlength:  
Low for 20-bit data.  
High for 24-bit data.  
Low for  
serial  
interface  
operation.  
23  
CSBIWO  
Digital input  
Low for 16-bit data.  
High for 20-bit  
(normal) or 24-bit  
I2S data.  
Low for 16-bit data.  
High for 20-bit  
(normal) or 24-bit  
I2S data.  
Internal pull-down  
24  
25  
MODE  
Digital input  
Low for hardware  
mode.  
Low for left  
mono mode.  
DINR  
High for  
software  
mode.  
Internal pull-up  
High for right  
mono mode  
MUTEB  
Digital input  
Low to soft mute.  
Low to soft mute.  
Low to soft mute.  
Low to  
soft mute.  
Internal pull-up  
High for normal  
operation.  
High for normal  
operation.  
High for normal  
operation.  
High for  
normal  
operation.  
26  
27  
28  
MD/DM0  
MC/DM1  
ML/I2S  
Digital input  
De-emphasis mode  
select bit 0.  
Low for no  
de-emphasis.  
LRP – LRCLK  
polarity select.  
Control serial  
interface  
data signal.  
Internal pull-up  
High for 44.1kHz  
de-emphasis.  
Digital input  
De-emphasis mode  
select bit 1.  
Low for normal filter  
operation.  
Unused.  
Control serial  
interface  
clock signal.  
Internal pull-up  
Leave unconnected.  
High for filter slow  
roll-off.  
Digital input  
Audio serial format:  
Low – right justified.  
High – I2S.  
Audio serial format:  
Low – right justified.  
High – I2S.  
Input data format:  
Low – right justified.  
High – left justified.  
Control serial  
interface  
load signal.  
Internal pull-up  
Note: Digital input pins have Schmitt trigger input buffers.  
ABSOLUTE MAXIMUM RATINGS  
Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at  
or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical  
Characteristics at the test conditions specified  
ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible  
to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage  
of this device.  
Wolfson tests its package types according to IPC/JEDEC J-STD-020B for Moisture Sensitivity to determine acceptable storage  
conditions prior to surface mount assembly. These levels are:  
MSL1 = unlimited floor life at <30°C / 85% Relative Humidity. Not normally stored in moisture barrier bag.  
MSL2 = out of bag storage for 1 year at <30°C / 60% Relative Humidity. Supplied in moisture barrier bag.  
MSL3 = out of bag storage for 168 hours at <30°C / 60% Relative Humidity. Supplied in moisture barrier bag.  
CONDITION  
MIN  
-0.3V  
MAX  
+7.0V  
Supply voltage  
Input  
GND -0.3V  
VDD + 0.3V  
Operating temperature range, TA  
Storage temperature prior to soldering  
Storage temperature after soldering  
°
°
-40 C  
+85 C  
30°C max / 85% RH max  
-65°C  
+150°C  
Note: It is strongly recommended that AVDD, AVDDL and AVDDR are tied together. AGND, AGNDL and AGND right  
must also be tied together.  
PD, Rev 4.4, April 2010  
w
5
WM8740  
Production Data  
RECOMMENDED OPERATING CONDITIONS  
PARAMETER  
SYMBOL  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
Digital supply range  
Analogue supply range  
Ground  
DVDD  
AVDD  
-10%  
-10%  
3.3 to 5  
+10%  
+10%  
V
V
3.3 to 5  
AGND, DGND  
0
V
Difference DGND to AGND  
Analogue supply current  
Digital supply current  
Analogue supply current  
Digital supply current  
-0.3  
0
+0.3  
V
AVDD = 5V  
DVDD = 5V  
AVDD = 3.3V  
DVDD = 3.3V  
13  
19  
12  
12  
mA  
mA  
mA  
mA  
Note:  
DVDD must be equal to, or less than the AVDD supply (i.e. DVDD = AVDD = +5V; DVDD = AVDD = +3.3V; DVDD = +3.3V  
AVDD = +5V).  
ELECTRICAL CHARACTERISTICS  
Test Conditions  
AVDD, DVDD = 5V, AGND, DGND = 0V, TA = +25oC, fs = 48kHz, SCKI = 256fs unless otherwise stated.  
PARAMETER  
DAC Circuit Specifications  
SNR  
SYMBOL  
TEST CONDITIONS  
MIN  
110  
-95  
TYP  
MAX  
UNIT  
Mono fs @ 48kHz  
Stereo fs @ 48kHz  
Stereo fs @ 96kHz  
Mono 0dB  
120  
117  
116  
-104  
-104  
117  
dB  
dB  
dB  
dB  
dB  
dB  
(See Note 1)  
THD (full-scale)  
(See Note 2)  
Stereo 0dB  
THD+N (Dynamic range)  
(See Note 2)  
-60dB  
Filter Characteristics (Sharp Roll-off)  
Passband  
0.0012 dB  
-3dB  
0.4535fs  
-82  
dB  
Stopband  
0.491fs  
30/fs  
Passband ripple  
0.0012  
dB  
dB  
s
Stopband attenuation  
Delay time  
f > 0.5465fs  
Filter Characteristics (Slow Roll-off)  
Passband  
0.001dB  
-3dB  
0.274fs  
0.459fs  
Stopband  
Passband ripple  
0.001  
dB  
dB  
s
Stopband attenuation  
Delay time  
f > 0.732fs  
-82  
9/fs  
Internal Analogue Filter  
Bandwidth  
-3dB  
195  
kHz  
dB  
Passband edge response  
Digital Logic Levels  
20kHz  
-0.043  
Input LOW level  
Input HIGH level  
Output LOW level  
Output HIGH level  
VIL  
VIH  
0.8  
2.0  
V
V
VOL  
VOH  
IOL = 2mA  
IOH = 2mA  
DGND + 0.3V  
DVDD - 0.3V  
PD, Rev 4.4, April 2010  
6
w
WM8740  
Production Data  
Test Conditions  
AVDD, DVDD = 5V, AGND, DGND = 0V, TA = +25oC, fs = 48kHz, SCKI = 256fs unless otherwise stated.  
PARAMETER  
SYMBOL  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
Analogue Output Levels  
Output level differential  
Into 10kΩ, full scale 0dB,  
2
1.32  
1
VRMS  
VRMS  
kΩ  
(5V supply)  
Into 10kΩ, full scale 0dB,  
(3.3V supply)  
Minimum resistance load  
To midrail or AC coupled  
(5V supply)  
To midrail or AC coupled  
(3.3V supply)  
600  
Ω
Maximum capacitance load  
Output DC level  
5V or 3.3V  
100  
pF  
V
AVDD/2  
Reference Levels  
Potential divider resistance  
10  
kΩ  
AVDD to VMIDL/VMIDR and  
VMIDL/VMIDR to AGND  
Voltage at VMIDL/VMIDR  
AVDD/2  
Notes: 1.  
Ratio of output level with 1kHz full scale input, to the output level with all zeros into the digital input, measured ‘A’  
weighted over a 20Hz to 20kHz bandwidth.  
2.  
All performance measurements done with 20kHz low pass filter. Failure to use such a filter will result in higher  
THD+N and lower SNR and Dynamic Range readings than are found in the Electrical Characteristics. The low  
pass filter removes out of band noise; although it is not audible it may affect dynamic specification values.  
LRCIN  
tBCH  
tBCL  
tLB  
BCKIN  
DIN  
tBCY  
tBL  
tDS  
tDH  
Figure 1 Audio Data Input Timing  
Test Conditions  
AVDD, DVDD = 5V, AGND, DGND = 0V, TA = +25oC, fs = 48kHz, SCKI = 256fs unless otherwise stated.  
PARAMETER  
SYMBOL  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
Audio Data Input Timing Information  
BCKIN pulse cycle time  
BCKIN pulse width high  
BCKIN pulse width low  
tBCY  
tBCH  
tBCL  
tBL  
100  
40  
ns  
ns  
ns  
ns  
40  
BCKIN rising edge to  
LRCIN edge  
20  
LRCIN rising edge to  
BCKIN rising edge  
tLB  
20  
ns  
DIN setup time  
DIN hold time  
tDS  
tDH  
20  
20  
ns  
ns  
PD, Rev 4.4, April 2010  
7
w
WM8740  
Production Data  
tSCKIL  
SCKI  
tSCKIH  
tSCKY  
Figure 2 System Clock Timing Requirements  
Test Conditions  
AVDD, DVDD = 5V, AGND, DGND = 0V, TA = +25oC, fs = 48kHz, SCKI = 256fs unless otherwise stated.  
PARAMETER  
SYMBOL  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
System Clock Timing Information  
System clock pulse width high  
System clock pulse width low  
System clock cycle time  
tSCKIH  
tSCKIL  
tSCKY  
10  
10  
27  
ns  
ns  
ns  
tMLL  
tMHH  
ML/I2S  
tMCY  
tMCH tMCL  
tMLD  
tMLS  
MC/DM1  
MD/DM0  
tMDS  
tMDH  
LSB  
Figure 3 Program Register Input Timing – SPI Compatible Serial Control Mode  
Test Conditions  
AVDD, DVDD = 5V, AGND, DGND = 0V, TA = +25oC, fs = 48kHz, SCKI = 256fs unless otherwise stated.  
PARAMETER  
SYMBOL  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
Program Register Input Information  
MC/DM1 pulse cycle time  
MC/DM1 pulse width low  
MD/DM0 pulse width high  
MD/DM0 set-up time  
tMCY  
tMCL  
tMCH  
tMDS  
tMDH  
tMLL  
tMHH  
tMLS  
tMLD  
80  
32  
32  
10  
10  
10  
10  
10  
10  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
MC/DM1 hold time  
ML/I2S pulse width low  
ML/I2S pulse width high  
ML/I2S set-up time  
ML/I2S delay from MC  
PD, Rev 4.4, April 2010  
8
w
WM8740  
Production Data  
INTERNAL POWER ON RESET CIRCUIT  
Power On Reset  
Circuit  
10K  
10K  
Figure 4 Internal Power On Reset Circuit Schematic  
The WM8740 includes an internal Power On Reset Circuit which is used reset the digital logic into a  
default state after power up.  
Figure 4 shows a schematic of the internal POR circuit. The POR circuit is powered from AVDD. The  
circuit monitors DVDD and VMIDL and asserts PORB low if DVDD or VMIDL are below the minimum  
threshold Vpor_off  
.
On power up, the POR circuit requires AVDD to be present to operate. PORB is asserted low until  
AVDD and DVDD and VMIDL are established. When AVDD, DVDD, and VMIDL have been  
established, PORB is released high, all registers are in their default state and writes to the digital  
interface may take place.  
On power down, PORB is asserted low whenever DVDD or VMIDLL drop below the minimum  
threshold Vpor_off  
.
If AVDD is removed at any time, the internal Power On Reset circuit is powered down and PORB will  
follow AVDD.  
In most applications the time required for the device to release PORB high will be determined by the  
charge time of the VMIDLL node.  
Figure 5 Typical Power Up Sequence where DVDD is Powered before AVDD  
PD, Rev 4.4, April 2010  
9
w
WM8740  
Production Data  
Figure 6 Typical Power Up Sequence where AVDD is Powered before DVDD  
Figure 7 Typical Power Up Sequence where AVDD is Powered and VMIDLL has Charged before DVDD  
Typical POR Operation (typical values, not tested)  
SYMBOL  
Vpora  
TYP  
0.35  
0.8  
UNIT  
V
V
V
V
V
Vpord  
Vporr  
0.85  
2.6  
Vpora_off  
Vpord_off  
0.8  
PD, Rev 4.4, April 2010  
10  
w
WM8740  
Production Data  
In a real application the designer is unlikely to have control of the relative power up sequence of  
AVDD and DVDD. Using the POR circuit to monitor VMIDLL ensures a reasonable delay between  
applying power to the device and Device Ready.  
Figure 5 and Figure 6 show typical power up scenarios in a real system. Both AVDD and DVDD must  
be established and VMIDL must have reached the threshold Vporr before the device is ready and can  
be written to. Any writes to the device before Device Ready will be ignored.  
Figure 5 shows DVDD powering up before AVDD. Figure 6 shows AVDD powering up before DVDD.  
In both cases, the time from applying power to Device Ready is dominated by the charge time of  
VMIDLL. In the case where AVDD is powered long before DVDD, thus allowing VMIDL to charge  
above Vporr, the PORB will not release until DVDD passes the Vpord threshold. This situation is  
shown in Figure 7.  
PD, Rev 4.4, April 2010  
11  
w
WM8740  
Production Data  
DEVICE DESCRIPTION  
The WM8740 is a high performance 128fs oversampling rate stereo DAC employing a novel 64 level  
sigma delta DAC design which provides optimised signal-to-noise performance and clock jitter  
tolerance. It is ideally suited to high quality audio applications such as CD, DVD-audio, home theatre  
receivers and professional mixing consoles. The WM8740 supports sample rates from 8ks/s to  
192ks/s.  
The control functions of the WM8740 are either pin selected (hardware mode) or programmed via the  
serial interface (software mode). Control functions that are available include: data input word length  
and format selection (16-24 bits: I2S, left justified or right justified): de-emphasis sample rate  
selection (48kHz, 44.1kHz and 32kHz); differential output modes; a software or hardware mute and  
independently digitally controllable attenuation on both channels.  
The digital filtering may be bypassed entirely by selecting MODE8X. Data is then input directly to the  
DAC, bypassing the digital filters. Left and right channels are input separately, using the MODE pin  
as the right channel input. This mode allows the use of alternative digital filters, such as the Pacific  
Microsonics PMD100 HDCD filter.  
In addition to the normal stereo operating mode the WM8740 may also be used in dual differential  
mode with either the left or right channel (selectable) being output dual differentially. Two WM8740s  
can then be used in parallel to implement a stereo channel, each supporting a single channel  
differentially. Note that this mode uses 2 pairs of differential outputs for each channel – the benefit is  
SNR improved by 3dB. This mode is available in both software and hardware modes and may also  
be used in conjunction with MODE8X.  
SYSTEM CLOCK  
Sample rates from 8ks/s up to 96ks/s are available, and automatically selected, with a system clock  
of 256fs or 384fs. In addition a system clock of 128fs or 192fs may be used, with sample rates up to  
192ks/s. With a 128fs or 192fs system clock 64x oversampling mode operation is automatically  
selected and the first stage of the digital filter is bypassed.  
WM8740 has an asynchronous monitor circuit, which in the event of removal of the master system  
clock, resets the digital filters and analogue circuits, muting the output. Re-application of the system  
clock re-starts the filters from an intitialised state. Control registers are not reset under this condition.  
The WM8740 is tolerant of asynchronous bit clock jitter. The internal signal processing  
resynchronises to the external LRCIN once the phase difference between bit clock and the system  
clock exceeds half an LRCIN period. During this re-synch period the interpolating filters will either  
miss or repeat an audio sample, minimising the audible effects of the operation. Table 1 shows the  
typical system clock frequency inputs for the WM8740.  
SAMPLING  
RATE  
SYSTEM CLOCK FREQUENCY (MHZ)  
128fs  
192fs  
256fs  
384fs  
512fs  
768fs  
(LRCIN)  
32kHz  
4.096  
5.6448  
6.114  
6.144  
8.467  
8.192  
11.2896  
12.288  
24.576  
12.288  
16.9340  
18.432  
36.864  
16.384  
22.5792  
24.576  
24.576  
33.8688  
36.864  
44.1kHz  
48kHz  
9.216  
96kHz  
12.288  
24.576  
18.432  
36.864  
Unavailable Unavailable  
192kHz  
Unavailable Unavailable Unavailable Unavailable  
Table 1 System Clock Frequencies Versus Sampling Rate  
AUDIO DATA INTERFACE  
Data may be input at a rate corresponding to the system clock having a rate of 256fs or 384fs, in  
which case an oversampling ratio of 128x is selected. Alternatively a rate of 128fs or 192fs may be  
used, in which case the first filter stage is bypassed and an oversampling ratio of 64x results. Finally,  
in MODE8X, data may be input at 8x the normal rate, in which case separate input pins are used to  
input the two stereo channels of data (unless DIFFHW mode and MODE8X are both selected, in  
which case only a mono channel is converted differentially). In MODE8X all filter stages are by-  
passed, prior to the sigma delta modulator, MODE8X is not supported at 192kHz sampling rate. Data  
is input MSB first in all modes.  
PD, Rev 4.4, April 2010  
12  
w
WM8740  
Production Data  
NORMAL SAMPLE RATE  
In normal mode, the data is input serially on one pin for both left and right channels.  
Data can be “right justified” meaning that the last 16, 20 or 24 bits (depending on chosen PCM word  
length) that were clocked in prior to the transition on LRCIN are valid.  
Alternatively data can be “left justified” (20 and 24-bit PCM data only), where the bits are clocked in  
as the first 20 or 24 bits after a transition on LRCIN.  
For the three I2S modes supported (16-bit, 20-bit and 24-bit PCM data), data is clocked “left justified”  
except with one additional preceding clock cycle.  
1/fs  
LEFT  
RIGHT  
LRCIN (PIN 1)  
BCKIN (PIN 3)  
16-BIT RIGHT  
JUSTIFIED  
DIN (PIN 2)  
B2 B1 B0  
B2 B1 B0  
B2 B1 B0  
B0  
B15  
B2 B1 B0  
B2 B1 B0  
B2 B1 B0  
B15  
B2 B1 B0  
B2 B1 B0  
B2 B1 B0  
20-BIT RIGHT  
JUSTIFIED  
DIN (PIN 2)  
B19 B18 B17  
B19 B18 B17  
24-BIT RIGHT  
JUSTIFIED  
DIN (PIN 2)  
B23 B22 B21 B20 B19  
B23 B22 B21 B20 B19  
24-BIT LEFT  
JUSTIFIED  
DIN (PIN 2)  
B23 B22 B21  
B4 B3 B2 B1 B0  
B23 B22 B21  
B4 B3 B2 B1 B0  
20-BIT LEFT  
JUSTIFIED  
DIN (PIN 2)  
B0  
B19 B18 B17  
B0  
B19 B18 B17  
B0  
LEFT  
RIGHT  
LRCIN (PIN 1)  
BCKIN (PIN 3)  
16-BIT I2S  
DIN (PIN 2)  
B15  
B23  
B19  
B2 B1 B0  
B15  
B23  
B19  
B2 B1 B0  
B15  
B23  
B19  
24-BIT I2S  
DIN (PIN 2)  
B6 B5 B4 B3 B2 B1 B0  
B6 B5 B4 B3 B2 B1 B0  
20-BIT I2S  
DIN (PIN 2)  
B2 B1 B0  
B2 B1 B0  
Figure 8 Audio Data Input Format  
PD, Rev 4.4, April 2010  
13  
w
WM8740  
Production Data  
8 X FS INPUT SAMPLE RATE  
Due to the higher speed of the interface in 8 x fs mode, audio data is input on two pins. The MODE  
pin (pin 24) is used as the second input for the right channel data and left data is input on DIN (pin2).  
In this mode, software control of the device is not available. The data can be input in two formats, left  
or right justified, selectable by ML/I2S and two word lengths (20 or 24 bit), selectable by CSBIWO. In  
both modes the data is always clocked in MSB first.  
For left justified data the word start is marked by the falling edge of LRCIN. The data is clocked in on  
the next 20/24 BCKIN rising edges. This format is compatible with devices such as the PMD100.  
For right justified the data is justified to the rising edge of LRCIN and the data is clocked in on the  
preceding 20/24 BCKIN rising edges before the LRCIN rising edge. This format is compatible with  
devices such as the DF1704 or SM5842.  
In both modes the polarity of LRCIN can be switched using MD/DM0.  
Differential hardware mode can be used in conjunction with 8fs mode by setting the DIFFHW  
pin high. In differential 8fs mode the data is input on DIN and output differentially. MODE is  
unused and must be tied low.  
1/8fs  
LRCIN (PIN 1)  
BCKIN (PIN 3)  
LEFT AUDIO  
B23  
B23  
B22  
B22  
B21  
B21  
B20  
B20  
B19  
B19  
B2  
B2  
B1  
B1  
B0  
B0  
B23  
B23  
B22  
B22  
B21  
B21  
B20  
B20  
DATA DIN  
(PIN 2)  
RIGHT AUDIO  
DATA MODE  
(PIN 24)  
1/8fs  
LRCIN (PIN 1)  
BCKIN (PIN 3)  
LEFT AUDIO  
DATA DIN  
(PIN 2)  
B23  
B22  
B21  
B20  
B20  
B19  
B19  
B2  
B2  
B1  
B1  
B0  
B0  
RIGHT AUDIO  
DATA MODE  
(PIN 24)  
B23  
B22  
B21  
Figure 9 Audio Data Input Format (8 x fs Operation)  
MODES OF OPERATION  
Control of the various modes of operation is either by software control over the serial interface, or  
by hard-wired pin control. Selection of software or hardware mode is via MODE pin. The following  
functions may be controlled either via the serial control interface or by hard wiring of the  
appropriate pins.  
HARDWARE CONTROL MODES  
When the MODE pin is held ‘low’ the following hardware modes of operation are available. In  
Hardware differential mode or 8X mode some of these modes/control words are altered or  
unavailable.  
PD, Rev 4.4, April 2010  
14  
w
WM8740  
Production Data  
DE-EMPHASIS CONTROL  
MDDM1  
MCDMO  
DE-EMPHASIS  
PIN 27  
PIN 26  
L
L
L
H
L
Off  
48kHz  
44.1kHz  
32kHz  
H
H
H
Table 2 De-Emphasis Control  
AUDIO INPUT FORMAT  
ML/I2S  
PIN 28  
L
CSBIWO  
PIN 23  
L
DATA FORMAT  
16 bit normal right  
justified  
L
H
20 bit normal right  
justified  
H
H
L
16 bit I2S  
24 bit I2S  
H
Table 3 Audio Input Format  
SOFT MUTE  
MUTEB  
PIN 25  
L
FUNCTION  
Mute On (no output)  
Mute Off (normal operation)  
H
Table 4 Soft Mute  
A logic low on the MUTEB pin will cause the attenuation to ramp to infinite attenuation at a rate of  
128/fs seconds per 0.5dB step. Setting MUTEB high will cause the attenuation to ramp back to its  
previous value.  
SOFTWARE CONTROL INTERFACE  
The WM8740 can be controlled using a 3-wire serial interface. MD/DM0 (pin 26) is used for the  
program data, MC/DM1 (pin 22) is used to clock in the program data and ML/I2S (pin 28) is use to  
latch in the program data. The 3-wire interface protocol is shown in Figure 6. CSB/IWO (pin 23) must  
be low when writing.  
ML/I2S (PIN 28)  
MC/DM1 (PIN 27)  
MD/DM0 (PIN 26)  
B15 B14 B13  
B2  
B1  
B0  
Figure 10 Three-Wire Serial Interface  
PD, Rev 4.4, April 2010  
15  
w
WM8740  
Production Data  
REGISTER MAP  
WM8740 controls the special functions using 4 program registers, which are 16-bits long. These  
registers are all loaded through input pin MD/DM0. After the 16 data bits are clocked in, ML/I2S is  
used to latch in the data to the appropriate register. Table 5 shows the complete mapping of the 4  
registers. Note that in hardware differential mode and 8X modes, software control is not available.  
The hardware differential mode (Diff[1:0]) clock loss detector disable (CDD) can only be accessed by  
writing to M2[8:5] with the pattern 1111. Register M4 is then accessible by setting A[2:0] to 110.  
B15  
B14  
B13  
B12  
B11  
B10  
B9  
B8  
B7  
AL7  
AR7  
-
B6  
AL6  
AR6  
-
B5  
AL5  
AR5  
-
B4  
AL4  
AR4  
IW1  
B3  
AL3  
AR3  
B2  
AL2  
AR2  
B1  
AL1  
AR1  
B0  
AL0  
AR0  
M0  
M1  
M2  
M3  
M4  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
A2 (0) A1(0) A0(0) LDL  
A2(0) A1(0) A0(1) LDR  
A2(0) A1(1) A0(0)  
A2(0) A1(1) A0(1) IZD  
A2(1) A1(1) A0(0)  
-
IW0 OPE DEM MUT  
SF1  
-
SF0  
-
REV SR0 ATC LRP  
I2S  
-
CDD DIFF1 DIFF0  
-
-
-
-
Table 5 Mapping of Program Registers  
REGISTER  
BITS  
NAME  
AL[7:0]  
LDL  
DEFAULT  
DESCRIPTION  
0
[7:0]  
FF  
0
Attenuation data for left channel.  
Attenuation data load control for left channel.  
Attenuation data for right channel.  
Attenuation data load control for right channel.  
Left and right DACs soft mute control.  
De-emphasis control.  
8
[7:0]  
8
1
2
AR[7:0]  
LDR  
FF  
0
0
MUT  
DEM  
OPE  
0
1
0
2
0
Left and right DACs operation control.  
Input audio data bit select.  
[4:3]  
0
IW[1:0]  
I2S  
0
3
0
Audio data format select.  
1
LRP  
0
Polarity of LRCIN select.  
2
ATC  
0
Attenuator control.  
3
SR0  
0
Digital filter slow roll-off select.  
Output phase reverse.  
4
REV  
0
[7:6]  
8
SF[1:0]  
IZD  
0
Sampling rate select.  
0
Infinite zero detection circuit control.  
Differential output mode.  
4
[5:4]  
6
DIFF  
CDD  
0
0
Clock loss detector disable.  
Table 6 Register Bit Descriptions  
DAC OUTPUT ATTENUATION  
The level of attenuation for eight bit code X, is given by:  
0.5 (X - 255) dB, 1 X 255  
- dB (mute),  
X = 0  
Bit 8 in register 0 (LDL) is used to control the loading of attenuation data in B[7:0]. When LDL is set  
to 0, attenuation data will be loaded into AL[7:0], but it will not affect the filter attenuation. LDR in  
register 1 has the same function for right channel attenuation. Only when LDL or LDR is set to '1' will  
the filter attenuation be updated. This permits left and right channel attenuation to be updated  
simultaneously.  
Attenuation level is controlled by AL[7:0] (left channel) or AR[7:0] (right channel). Attenuation levels  
are given in Table 7.  
PD, Rev 4.4, April 2010  
16  
w
WM8740  
Production Data  
X[7:0]  
ATTENUATION LEVEL  
00(hex)  
- dB (mute)  
01(hex)  
-127.0dB  
:
:
:
:
FD(hex)  
FE(hex)  
-1.0dB  
-0.5dB  
0.0dB  
FF(hex)  
Table 7 Attenuation Control Level  
Bit 2 in Reg3 is used to control the attenuator (ATC). When ATC is “high”, the attenuation data  
loaded in program register 0 is used for both the left and the right channels. When ATC is low, the  
attenuation data for each register is applied separately to left and right channels.  
SOFT MUTE  
MUT  
(REG2, B0)  
L
Soft Mute off (normal operation)  
Soft Mute on (no output)  
H
Table 8 Soft Mute  
Setting MUT causes the attenuation to ramp from the current value down to 00. The values held in  
the attenuation registers are unchanged. When MUT is reset the attenuation will ramp back up to the  
previous value. The ramp rate is 128/fs s/0.5dB step.  
DIGITAL DE-EMPHASIS  
DEM  
(REG2, B1)  
L
De-emphasis off  
De-emphasis on  
H
Table 9 Digital De-Emphasis  
DAC OPERATION ENABLE  
OPE  
(REG2,B2)  
L
Normal operation  
H
DAC output forced to bipolar zero,  
irrespective of input data.  
Table 10 DAC Operation Enable  
AUDIO DATA INPUT FORMAT  
I2S  
IW1  
IW0  
AUDIO INTERFACE  
(REG3, B0)  
(REG2, B4)  
(REG2, B3)  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
16-bit standard right justified  
20-bit standard right justified  
24-bit standard right justified  
24-bit left justified (MSB first)  
16-bit I2S  
24-bit I2S  
20-bit I2S  
20-bit left justified (MSB first)  
Table 11 Audio Data Input Format  
PD, Rev 4.4, April 2010  
17  
w
WM8740  
Production Data  
POLARITY OF LR INPUT CLOCK  
The left channel data for a particular sample instant is always input first, then the right channel data.  
LRP  
(REG3, B1)  
L
LR High – left channel  
LR Low – right channel  
LR Low – left channel  
LR High – right channel  
H
Table 12 Polarity of LR Input Clock  
INDIVIDUAL OR COMMON ATTENUTATION CONTROL  
ATC  
(REG3, B2)  
L
Individual control  
H
Common control from Reg0  
Table 13 Individual or Common Attenuation Control  
DIGITAL FILTER ROLL-OFF SELECTION  
SRO  
(REG3, B3)  
L
Sharp  
Slow  
H
Table 14 Digital Filter Roll-Off Selection  
ANALOGUE OUTPUT POLARITY REVERSAL  
REV  
(REG3, B4)  
L
Normal  
H
Inverted  
Table 15 Analogue Output Polarity Reversal  
DE-EMPHASIS SAMPLE RATE  
SF1  
SF0  
SAMPLE RATE  
(REG3, B7)  
(REG3, B6)  
0
0
1
1
0
1
0
1
No de-emphasis  
48kHz  
44.1kHz  
32kHz  
Table 16 De-Emphasis Sample Rate  
INFINITE ZERO DETECT  
IZD  
(REG3, B8)  
L
Zero detect mute off  
Zero detect mute on  
H
Table 17 Infinite Zero Detect  
PD, Rev 4.4, April 2010  
18  
w
WM8740  
Production Data  
SOFTWARE DIFFERENTIAL MONO MODE  
To control the WM8740 in software differential mode register M4 must be written to. A ‘key’ register  
write must be made to register M2 to allow access to register M4 which is ‘locked’ as default. Bits B5  
to B8 of register M2 must be set to ‘1’ (0x01e0).  
With register M4 ‘unlocked’, bits B4 and B5 may be used to set the required differential output mode;  
normal stereo, reversed stereo, mono left or mono right, as shown in Table 18.  
DIFF[1:0]  
B[5:4])  
00  
DIFFERENTIAL OUTPUT MODE  
Stereo  
10  
Stereo reverse.  
01  
Mono left – differential outputs.  
VOUTLP (17) is left channel.  
VOUTLN (16) is left channel inverted.  
VOUTRP (12) is left channel inverted.  
VOUTRN (13) is left channel.  
Mono right – differential outputs.  
VOUTLP (17) is right channel inverted.  
VOUTLN (16) is right channel.  
VOUTRP (12) is right channel.  
VOUTRN (13) is right channel inverted.  
11  
Table 18 Differential Output Modes  
Using these controls a pair of WM8740 devices may be used to build a dual differential stereo  
implementation with higher performance and differential output.  
Note: DIFFHW mode pin may be used to achieve the same result by hardware means.  
CLOCK LOSS DETECTOR DISABLE  
CDD (REG4, B6)  
L
Clock loss detector on  
Clock loss detector off  
R
Table 19 Clock Loss Detector Disable  
When the system clock is inactive for approximately 100μs, the clock loss detector circuit detects the  
loss of clock and the analogue circuitry is forced into a mute condition and the digital filters reset.  
Setting the CDD bit disables this behaviour.  
PD, Rev 4.4, April 2010  
19  
w
WM8740  
Production Data  
MUTE MODES  
The device has various mute modes.  
DIGITAL FILTER  
ANALOGUE  
ANRES  
ANMUTE  
Reg bit OPE = ‘1’  
MUTEB pin  
Unaffected  
Asserted  
Gain ramped to zero  
Asserted when  
gain = 0  
On release volume ramps  
to previous value  
AUTOMUTE  
Automute has no effect on digital  
filters  
Asserted after  
1024 zero input  
samples if IZD = 1  
(detect 1024 zero  
input samples)  
Reg bit MUT  
As MUTEB pin  
As MUTEB pin  
Asserted  
Gain = 00  
(left and right)  
Gain = -dB  
RAM initialise  
Gain initialised to 0dB  
Asserted  
Asserted  
Loss of system  
clock  
Not running (no clock). On clock  
restart, filters initialised, RAM  
initialised. Registers unchanged  
Asserted  
Asserted  
No LRCLK or invalid  
SCLK/LRCLK ratio  
Filters initialised, RAM initialised.  
Registers unchanged  
Asserted  
RB  
Reset – gain initialised to 0dB  
Reset  
Asserted  
Asserted  
Asserted  
Asserted  
Power-on reset  
Table 20 Mute Modes  
ANRES is the reset to the switched capacitor filter.  
1. ANMUTE is an analogue muting signal gating the analogue signal at the output (after  
the SC filter)  
2. AUTOMUTE is asserted when both the IZD register bit is asserted and the input audio  
data has been zero on both left and right channels for 1024 input samples. The first  
non-zero sample de-asserts.  
3. Applying a logic low to MUTEB or setting MUT in Reg2 causes the gain registers to  
ramp to zero. When a logic high is applied, the gain ramps slowly back up to the value  
held in the appropriate attenuation register (AL or AR). The ramp rate = 128/fs s/0.5dB  
step.  
If SOFTMUTE is set or  
MUTEB=0 then GAINL and  
GAINR are overridden to 00  
GAINL[0:7]  
Signal  
Processing  
GAINR[0:7]  
SOFTMUTE  
MUTEB  
gain ramps between  
previous and new gain  
setting  
Automute:  
Detect 1024  
zero input  
samples  
IZD  
OPE  
FREQ_INVALID  
INIT  
ANMUTE  
ZERO  
Figure 11 Mute Modes  
PD, Rev 4.4, April 2010  
20  
w
WM8740  
Production Data  
FILTER RESPONSES  
Figure 12 Digital Filter Response (Sharp Roll-off Mode)  
Figure 13 Digital Filter Response (Sharp Roll-off Mode)  
Figure 14 Digital Filter Response (Slow Roll-off Mode)  
Figure 15 Digital Filter Response (Slow Roll-off Mode)  
0
-20  
-40  
-60  
-80  
-100  
-120  
0
0.2  
0.4  
0.6  
0.8  
1
1.2  
1.4  
1.6  
1.8  
2
Frequency (Fs)  
Figure 16 Digital Filter Response 128fs Mode (192kHz  
Sample Rate) Normal Mode – Solid, Slow Mode  
– Dashed  
PD, Rev 4.4, April 2010  
21  
w
WM8740  
Production Data  
1
0.8  
0.6  
0.4  
0.2  
0
1
0.8  
0.6  
0.4  
0.2  
0
-0.2  
-0.2  
-0.4  
-0.4  
0
10  
20  
30  
40  
50  
60  
0
10  
20  
30  
40  
50  
60  
Time (input samples)  
Time (input samples)  
Figure 17 Impulse Response (Normal Roll-off,  
no De-emphasis)  
Figure 18 Impulse Response (Slow Roll-off,  
no De-emphasis)  
0.0  
-1.0  
-2.0  
-3.0  
-4.0  
-5.0  
-6.0  
-7.0  
-8.0  
-9.0  
-10.0  
0.0  
-1.0  
-2.0  
-3.0  
-4.0  
-5.0  
-6.0  
-7.0  
-8.0  
-9.0  
-10.0  
0
2000  
4000  
6000  
8000  
10000  
12000  
14000  
16000  
0
5000  
10000  
15000  
20000  
Frequency (Fs)  
Frequency (Fs)  
Figure 19 De-emphasis Frequency Response (fs=32kHz)  
Figure 20 De-emphasis Frequency Response (fs=44.1kHz)  
0.0  
-1.0  
-2.0  
-3.0  
-4.0  
-5.0  
-6.0  
-7.0  
-8.0  
-9.0  
-10.0  
0.4  
0.3  
0.2  
0.1  
0.0  
-0.1  
-0.2  
-0.3  
-0.4  
0
2000  
4000  
6000  
8000  
10000 12000 14000 16000 18000 20000  
0
2000  
4000  
6000  
8000  
10000  
12000  
14000  
16000  
Frequency (Fs)  
Frequency (Fs)  
Figure 21 De-emphasis Frequency Response (fs=48kHz)  
Figure 22 De-emphasis Frequency Response Error  
(fs=32kHz)  
PD, Rev 4.4, April 2010  
22  
w
WM8740  
Production Data  
0.4  
0.4  
0.3  
0.3  
0.2  
0.2  
0.1  
0.1  
0.0  
0.0  
-0.1  
-0.2  
-0.3  
-0.4  
-0.1  
-0.2  
-0.3  
-0.4  
0
2000  
4000  
6000  
8000  
10000 12000 14000 16000 18000 20000  
0
2000  
4000  
6000  
8000  
10000 12000 14000 16000 18000 20000  
Frequency (Fs)  
Frequency (Fs)  
Figure 23 De-emphasis Frequency Response Error  
(fs=44.1kHz)  
Figure 24 De-emphasis Frequency Response Error  
(fs=48kHz)  
PD, Rev 4.4, April 2010  
23  
w
WM8740  
Production Data  
APPLICATIONS INFORMATION  
RECOMMENDED EXTERNAL COMPONENTS  
DVDD  
AVDD  
8
15  
9
DVDD  
AVDD  
AVDDR  
AVDDL  
+
C1  
C2  
7
20  
DGND  
+
C3  
C4  
C5  
C6  
DGND  
14  
10  
19  
16  
17  
AGND  
AGNDR  
AGNDL  
AGND  
28  
27  
26  
23  
22  
-
ML/I2S  
MC/DM1  
MD/DM0  
CSB/IWO  
RSTB  
VOUTLN  
VOUTLP  
LEFT OUTPUT DATA  
+
Software I/F or  
Hardware Control  
13  
12  
-
VOUTRN  
VOUTRP  
RIGHT OUTPUT DATA  
+
4
6
MODE8X  
WM8740  
AVDD  
DIFFHW  
MODE  
R1  
24  
25  
21  
ZERO  
11  
18  
MUTEB  
VMIDR  
VMIDL  
+
1
1
1
2
C
C
+
1
2
3
1
0
LRCIN  
DIN  
C9  
C
Audio Serial Data I/F  
System Clock Input  
BCKIN  
AGND  
R2  
R2  
5
SCLK  
Notes: 1. AGND and DGND should be connected as close to the WM8740 as possible.  
to  
C
,
1
and C should be positioned as close to the WM8740 as possible.  
1
2. C2  
5 C 9  
3. Capacitor type used can have a big effect on device performance. It is  
recommended that capacitors with very low ESR are used and that ceramics are  
either NPO or COG type material to achieve best performance from the WM8740.  
Figure 25 External Components Diagram  
RECOMMENDED EXTERNAL COMPONENTS VALUES  
COMPONENT  
REFERENCE  
SUGGESTED  
VALUE  
DESCRIPTION  
C1 and C6  
C2 to C5  
C7 and C8  
C9 and C11  
C10 and C12  
R1  
10μF  
0.1μF  
10μF  
0.1μF  
10μF  
10kΩ  
51Ω  
De-coupling for DVDD and AVDD.  
De-coupling for DVDD and AVDD.  
Output AC coupling caps to remove VMID DC level from outputs.  
Reference de-coupling capacitors for VMIDR and VMIDL.  
Resistor to AVDD for open drain output operation.  
Source termination resistors.  
R2  
Table 21 External Components Description  
PD, Rev 4.4, April 2010  
24  
w
WM8740  
Production Data  
SUGGESTED DIFFERENTIAL OUTPUT FILTER CIRCUIT  
Figure 26 Suggested Differential Output Filter Circuit  
RECOMMENDED DUAL DIFFERENTIAL HARDWARE SETUP  
Figure 27 Recommended Dual Differential Hardware Setup  
PD, Rev 4.4, April 2010  
25  
w
WM8740  
Production Data  
PACKAGE DIMENSIONS  
DS: 28 PIN SSOP (10.2 x 5.3 x 1.75 mm)  
DM007.E  
b
e
28  
15  
E1  
E
GAUGE  
PLANE  
Θ
14  
1
D
0.25  
L
c
A1  
L1  
A A2  
-C-  
0.10 C  
SEATING PLANE  
Dimensions  
(mm)  
NOM  
-----  
Symbols  
MIN  
-----  
0.05  
1.65  
0.22  
0.09  
9.90  
MAX  
A
A1  
A2  
b
c
D
e
E
E1  
L
2.0  
0.25  
1.85  
0.38  
0.25  
10.50  
-----  
1.75  
0.30  
-----  
10.20  
0.65 BSC  
7.80  
7.40  
5.00  
0.55  
8.20  
5.60  
0.95  
5.30  
0.75  
L1  
θ
1.25 REF  
0o  
4o  
8o  
JEDEC.95, MO-150  
REF:  
NOTES:  
A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS.  
B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE.  
C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.20MM.  
D. MEETS JEDEC.95 MO-150, VARIATION = AH. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS.  
PD, Rev 4.4, April 2010  
26  
w
WM8740  
Production Data  
IMPORTANT NOTICE  
Wolfson Microelectronics plc (“Wolfson”) products and services are sold subject to Wolfson’s terms and conditions of sale,  
delivery and payment supplied at the time of order acknowledgement.  
Wolfson warrants performance of its products to the specifications in effect at the date of shipment. Wolfson reserves the  
right to make changes to its products and specifications or to discontinue any product or service without notice. Customers  
should therefore obtain the latest version of relevant information from Wolfson to verify that the information is current.  
Testing and other quality control techniques are utilised to the extent Wolfson deems necessary to support its warranty.  
Specific testing of all parameters of each device is not necessarily performed unless required by law or regulation.  
In order to minimise risks associated with customer applications, the customer must use adequate design and operating  
safeguards to minimise inherent or procedural hazards. Wolfson is not liable for applications assistance or customer  
product design. The customer is solely responsible for its selection and use of Wolfson products. Wolfson is not liable for  
such selection or use nor for use of any circuitry other than circuitry entirely embodied in a Wolfson product.  
Wolfson’s products are not intended for use in life support systems, appliances, nuclear systems or systems where  
malfunction can reasonably be expected to result in personal injury, death or severe property or environmental damage.  
Any use of products by the customer for such purposes is at the customer’s own risk.  
Wolfson does not grant any licence (express or implied) under any patent right, copyright, mask work right or other  
intellectual property right of Wolfson covering or relating to any combination, machine, or process in which its products or  
services might be or are used. Any provision or publication of any third party’s products or services does not constitute  
Wolfson’s approval, licence, warranty or endorsement thereof. Any third party trade marks contained in this document  
belong to the respective third party owner.  
Reproduction of information from Wolfson datasheets is permissible only if reproduction is without alteration and is  
accompanied by all associated copyright, proprietary and other notices (including this notice) and conditions. Wolfson is  
not liable for any unauthorised alteration of such information or for any reliance placed thereon.  
Any representations made, warranties given, and/or liabilities accepted by any person which differ from those contained in  
this datasheet or in Wolfson’s standard terms and conditions of sale, delivery and payment are made, given and/or  
accepted at that person’s own risk. Wolfson is not liable for any such representations, warranties or liabilities or for any  
reliance placed thereon by any person.  
ADDRESS:  
Wolfson Microelectronics plc  
26 Westfield Road  
Edinburgh  
EH11 2QB  
United Kingdom  
Tel :: +44 (0)131 272 7000  
Fax :: +44 (0)131 272 7001  
Email :: sales@wolfsonmicro.com  
PD, Rev 4.4, April 2010  
27  
w
配单直通车
WM8740SEDS/RV产品参数
型号:WM8740SEDS/RV
是否Rohs认证: 符合
生命周期:Active
包装说明:SSOP, SSOP28,.3
Reach Compliance Code:compliant
HTS代码:8542.39.00.01
风险等级:5.78
转换器类型:D/A CONVERTER
输入位码:BINARY
输入格式:SERIAL
JESD-30 代码:R-PDSO-G28
长度:10.2 mm
位数:24
功能数量:1
端子数量:28
最高工作温度:85 °C
最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY
封装代码:SSOP
封装等效代码:SSOP28,.3
封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, SHRINK PITCH
电源:5 V
认证状态:Not Qualified
座面最大高度:2 mm
子类别:Other Converters
标称供电电压:3.3 V
表面贴装:YES
技术:CMOS
温度等级:INDUSTRIAL
端子形式:GULL WING
端子节距:0.65 mm
端子位置:DUAL
宽度:5.3 mm
Base Number Matches:1
  •  
  • 供货商
  • 型号 *
  • 数量*
  • 厂商
  • 封装
  • 批号
  • 交易说明
  • 询价
批量询价选中的记录已选中0条,每次最多15条。
 复制成功!