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WM8759

w

24-bit 192kHz Stereo DAC with Headphone Buffer

DESCRIPTION

FEATURES

•

Stereo DAC with headphone driver

The WM8759 is a high performance stereo DAC with an

integrated headphone driver. It is designed for audio

applications such as portable DVD, MP3 players or

consumer equipment with line output and headphone output

connections.

50mW power into 16R load on 3.3V supply

Audio Performance

-

100dB SNR (‘A’ weighted @ 48kHz)

-88dB THD line level

-

The WM8759 supports data input word lengths from 16 to

24-bits and sampling rates up to 192kHz. The WM8759

consists of a serial interface port, digital interpolation filters,

multi-bit sigma delta modulators and stereo DAC in a 14-pin

SOIC package.

-72dB THD headphone

•

DAC Sampling Frequency: 8kHz – 192kHz

Pin Selectable Audio Data Interface Format

-

I²S, 16-bit Right Justified or DSP

•

2.7V - 5.5V Supply Operation, Split Analog-digital supplies

14-pin SOIC Package

The hardware control interface is used for the selection of

audio data interface format, enable and de-emphasis. The

WM8759 supports I²S, right Justified or DSP interfaces.

Typical power consumption 20mW on 2.7V supply

Operating on split analog digital supplies the WM8759

allows very lower power consumption from the digital

section, whilst supporting large output powers from the

analog headphone driver.

APPLICATIONS

•

Portable music Players

Home music players

Digital TV

BLOCK DIAGRAM

Advanced Information, September 2004, Rev 3.0

WOLFSON MICROELECTRONICS plc

Copyright 2004 Wolfson Microelectronics plc

www.wolfsonmicro.com

WM8759

Advanced Information

TABLE OF CONTENTS

DESCRIPTION ............................................................................................................1

FEATURES..................................................................................................................1

APPLICATIONS ..........................................................................................................1

BLOCK DIAGRAM ......................................................................................................1

TABLE OF CONTENTS ..............................................................................................2

PIN CONFIGURATION................................................................................................3

ORDERING INFORMATION .......................................................................................3

PIN DESCRIPTION .....................................................................................................4

ABSOLUTE MAXIMUM RATINGS..............................................................................5

DC ELECTRICAL CHARACTERISTICS .....................................................................6

ELECTRICAL CHARACTERISTICS ...........................................................................6

MASTER CLOCK TIMING.................................................................................................. 8

DIGITAL AUDIO INTERFACE............................................................................................ 8

DEVICE DESCRIPTION..............................................................................................9

GENERAL INTRODUCTION.............................................................................................. 9

DAC CIRCUIT DESCRIPTION ........................................................................................... 9

CLOCKING SCHEMES .....................................................................................................10

DIGITAL AUDIO INTERFACE...........................................................................................10

AUDIO DATA SAMPLING RATES.....................................................................................12

HARDWARE CONTROL MODES .....................................................................................13

DIGITAL FILTER CHARACTERISTICS.............................................................................14

DAC FILTER RESPONSES...............................................................................................14

DIGITAL DE-EMPHASIS CHARACTERISTICS........................................................15

APPLICATIONS INFORMATION ..............................................................................16

RECOMMENDED EXTERNAL COMPONENTS .......................................................16

POWER UP/DOWN SEQUENCE......................................................................................16

PCB LAYOUT RECOMMENDATIONS..............................................................................17

PACKAGE DRAWING...............................................................................................18

IMPORTANT NOTICE...............................................................................................19

ADDRESS: ........................................................................................................................19

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WM8759

PIN CONFIGURATION

ORDERING INFORMATION

TEMPERATURE

MOISTURE SENSITIVITY

LEVEL

PEAK SOLDERING

TEMPERATURE

DEVICE

RANGE

PACKAGE

240°C

WM8759ED/V

-25 to +85^oC

14-pin SOIC

(tape and reel)

14-pin SOIC

(lead free)

MSL2

240°C

WM8759ED/RV

-25 to +85^oC

MSL2

260°C

WM8759GED/V

WM8759GED/RV

-25 to +85^oC

MSL2

14-pin SOIC

(lead free,

tape and reel)

Note:

Reel quantity = 3,000

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Advanced Information

PIN DESCRIPTION

1

NAME

LRCIN

TYPE

Digital input

DESCRIPTION

Sample rate clock input

Serial audio data input

Bit clock input

2

DIN

Digital input

Analogue output

Supply

3

BCKIN

ENABLE

CAP

4

Enable input – 0 = powered down, 1 = enabled

Analogue internal reference

5

6

HPOUTR

AGND

AVDD

Right channel DAC output

7

Ground reference for analog circuits and substrate connection

Positive supply for analog circuits

Left channel DAC output

8

Supply

9

HPOUTL

DGND

DVDD

Analogue output

Digital Supply

Digital input

10

11

12

Digital ground supply

Digital positive supply

DEEMPH

De-emphasis select, Internal pull down

High = de-emphasis ON

Low = de-emphasis OFF

13

14

FORMAT

MCLK

Digital input

Data input format select, Internal pull up

Low = 16-bit right justified or DSP ‘late’

High = 16-24-bit I²S or DSP ‘early’

Master clock input

Note:

1. Digital input pins have Schmitt trigger input buffers.

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WM8759

ABSOLUTE MAXIMUM RATINGS

Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at

or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical

Characteristics at the test conditions specified.

ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible

to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage

of this device.

Wolfson tests its package types according to IPC/JEDEC J-STD-020B for Moisture Sensitivity to determine acceptable storage

conditions prior to surface mount assembly. These levels are:

MSL1 = unlimited floor life at <30°C / 85% Relative Humidity. Not normally stored in moisture barrier bag.

MSL2 = out of bag storage for 1 year at <30°C / 60% Relative Humidity. Supplied in moisture barrier bag.

MSL3 = out of bag storage for 168 hours at <30°C / 60% Relative Humidity. Supplied in moisture barrier bag.

The Moisture Sensitivity Level for each package type is specified in Ordering Information.

CONDITION

MIN

-0.3V

MAX

+7V

Supply voltage

Voltage range digital inputs

Master Clock Frequency

Operating temperature range, T_A

Storage temperature prior to soldering

Storage temperature after soldering

GND -0.3V

VDD +0.3V

50MHz

+85°C

-25°C

30°C max / 85% RH max

-65°C

+150°C

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Advanced Information

DC ELECTRICAL CHARACTERISTICS

PARAMETER

Supply range

Ground

SYMBOL

AVDD, DVDD

AGND, DGND

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V

2.7

5.5

0

V

Analog supply current

AVDD = 5V

AVDD = 3.3V

DVDD = 5V

12

mA

Digital supply current

8

4

mA

DVDD = 3.3V

AVDD=DVDD=5V

Power down current (note 4)

0.01

ELECTRICAL CHARACTERISTICS

Test Conditions

AVDD = 5V, DVDD = 3.3V, GND = 0V, T_A= +25^oC, fs = 48kHz, MCLK = 256fs unless otherwise stated.

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

0.8

UNIT

Digital Logic Levels (TTL Levels)

Input LOW level

V_IL

V_IH

V

Input HIGH level

2.0

Output LOW

V_OL

V_OH

I

_OL= 2mA

DGND + 0.3V

Output HIGH

I

_OH= 2mA

DVDD – 0.3V

Analogue Reference Levels

Reference voltage (CAP)

Potential divider resistance

AVDD/2

50k

V

R_CAP

AVDD to CAP and CAP

to GND

Ω

DAC Output (Load = 10kΩ. 50pF)

0dBFs Full scale output voltage

At DAC outputs

1.1 x

AVDD/5

100

Vrms

dB

SNR (Note 5,6,7)

A-weighted,

@ fs = 48kHz

A-weighted

@ fs = 96kHz

A-weighted

@ fs = 192kHz

A-weighted,

@ fs = 48kHz

VDD = 3.3V

A-weighted

94

97

95

dB

SNR (Note 5,6,7)

95

dB

@ fs = 96kHz

VDD = 3.3V

SNR (Note 5,6,7)

Non ‘A’ weighted @ fs

= 48kHz

97

dB

THD+N (Note 7)

10k load

16R load

1kHz, 0dBFs

-88

-72

93

dB

THD+N driving headphone

DAC channel separation

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WM8759

Test Conditions

AVDD = 5V, DVDD = 3.3V, GND = 0V, T_A= +25^oC, fs = 48kHz, MCLK = 256fs unless otherwise stated.

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Analogue Output Levels

Output level

Load = 10kΩ, 0dBFS

1.1

Vrms

Load = 10kΩ, 0dBFS,

0.72

(AVDD = 3.3V)

Gain mismatch

channel-to-channel

1

16

%FSR

Minimum resistance load

To midrail or a.c.

coupled

To midrail or a.c.

coupled

Ω

(AVDD = 3.3V)

Output d.c. level

AVDD/2

V

Notes:

1. Ratio of output level with 1kHz full scale input, to the output level with all zeros into the digital input, measured ‘A’ weighted

over a 20Hz to 20kHz bandwidth.

2. All performance measurements done with 20kHz low pass filter, and where noted an A-weight filter. Failure to use such a

filter will result in higher THD+N and lower SNR and Dynamic Range readings than are found in the Electrical

Characteristics. The low pass filter removes out of band noise; although it is not audible it may affect dynamic specification

values.

3. CAP pin decoupled with 10uF and 0.1uF capacitors (smaller values may result in reduced performance).

4. Power down occurs 1.5µs after MCLK is stopped.

5. Signal-to-noise ratio (dB) - SNR is a measure of the difference in level between the full scale output and the output with no

signal applied. (No Auto-zero or Automute function is employed in achieving these results).

6. Dynamic range (dB) - DNR is a measure of the difference between the highest and lowest portions of a signal. Normally a

THD+N measurement at 60dB below full scale. The measured signal is then corrected by adding the 60dB to it. (e.g.

THD+N @ -60dB= -32dB, DR= 92dB).

7. THD+N (dB) - THD+N is a ratio, of the rms values, of (Noise + Distortion)/Signal.

8. Stop band attenuation (dB) - Is the degree to which the frequency spectrum is attenuated (outside audio band).

9. Channel Separation (dB) - Also known as Cross-Talk. This is a measure of the amount one channel is isolated from the

other. Normally measured by sending a full scale signal down one channel and measuring the other.

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Advanced Information

MASTER CLOCK TIMING

t_MCLKL

MCLK

t_MCLKH

t_MCLKY

Figure 1 Master Clock Timing Requirements

Test Conditions

VDD = 5V, GND = 0V, T_A= +25^oC, fs = 48kHz, MCLK = 256fs unless otherwise stated.

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNIT

System Clock Timing Information

MCLK Master clock pulse width high

MCLK Master clock pulse width low

MCLK Master clock cycle time

MCLK Duty cycle

t_MCLKH

t_MCLKL

t_MCLKY

8

ns

20

40:60

1.5

60:40

12

Time from MCLK stopping to power

down.

µs

DIGITAL AUDIO INTERFACE

t_BCH

t_BCL

BCKIN

LRCIN

DIN

t_BCY

t_LRSU

t_DS

t_LRH

t_DH

Figure 2 Digital Audio Data Timing

Test Conditions

VDD = 5V, GND = 0V, T_A= +25^oC, fs = 48kHz, MCLK = 256fs unless otherwise stated.

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Audio Data Input Timing Information

BCKIN cycle time

t_BCY

t_BCH

t_BCL

40

16

8

ns

BCKIN pulse width high

BCKIN pulse width low

LRCIN set-up time to

BCKIN rising edge

t_LRSU

LRCIN hold time from

BCKIN rising edge

t_LRH

t_DS

8

ns

DIN set-up time to BCKIN

rising edge

DIN hold time from BCKIN

rising edge

t_DH

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WM8759

DEVICE DESCRIPTION

GENERAL INTRODUCTION

The WM8759 is a high performance DAC with integrated headphone output buffer, designed for

digital consumer audio applications. The range of features make it ideally suited for use in

portable DVD players, MP3 players and other consumer audio equipment.

The WM8759 is a complete 2-channel stereo audio digital-to-analogue converter, including digital

interpolation filter, multi-bit sigma delta with dither, and switched capacitor multi-bit stereo DAC

and output smoothing filters. It is fully compatible and an ideal partner for a range of industry

standard microprocessors, controllers and DSPs. A novel multi bit sigma-delta DAC design is

used, utilising a 128x oversampling rate, to optimise signal to noise performance and offer

increased clock jitter tolerance. (In ‘high-rate’ operation, the oversampling ratio is 64x for system

clocks of 128fs or 192fs)

Control of the internal functionality of the device is provided by hardware control (pin

programmed).

Operation using master clocks of 256fs, 384fs, 512fs or 768fs is provided, selection between

clock rates being automatically controlled. Sample rates (fs) from less than 8kHz to 96kHz are

allowed, provided the appropriate system clock is input. Support is also provided for up to 192kHz

using a master clock of 128fs or 192fs.

The audio data interface supports 16-bit right justified or 16-24-bit I²S (Philips left justified, one bit

delayed) interface formats. A DSP interface is also supported, enhancing the interface options for

the user.

Split analog and digital 2.7-5.5V supply may be used, the output amplitude scaling with absolute

analog supply level. Low supply voltage operation and low current consumption combined with the

low pin count small package make the WM8759 attractive for many consumer applications. A

power down mode is provided, allowing power consumption to be minimised.

The device is packaged in a small 14-pin SOIC.

DAC CIRCUIT DESCRIPTION

The WM8759 DAC is designed to allow playback of 24-bit PCM audio or similar data with high

resolution and low noise and distortion. Sample rates up to 192kHz may be used, with much lower

sample rates being acceptable provided that the ratio of sample rate (LRCIN) to master clock

(MCLK) is maintained at one of the required rates.

The two DACs on the WM8759 are implemented using sigma-delta oversampled conversion

techniques. These require that the PCM samples are digitally filtered and interpolated to generate

a set of samples at a much higher rate than the up to 192kHz input rate. This sample stream is

then digitally modulated to generate a digital pulse stream that is then converted to analogue

signals in a switched capacitor DAC.

The advantage of this technique is that the DAC is linearised using noise shaping techniques,

allowing the 24-bit resolution to be met using non-critical analogue components. A further

advantage is that the high sample rate at the DAC output means that smoothing filters on the

output of the DAC need only have fairly crude characteristics in order to remove the characteristic

steps, or images on the output of the DAC. To prevent the generation of unwanted tones dithering

is used in the digital modulator along with a higher order modulator.

The multi-bit switched capacitor technique used in the DAC reduces sensitivity to clock jitter, and

dramatically reduces out of band noise compared to switched current or single bit techniques

used in other implementations.

The voltage on the CAP pin is used as the reference for the DACs. Therefore the amplitude of the

signals at the DAC outputs will scale with the amplitude of the voltage at the CAP pin. An external

reference could be used to drive into the CAP pin if desired, with a value typically of about midrail

ideal for optimum performance.

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WM8759

Advanced Information

The outputs of the 2 DACs are buffered out of the device by buffer amplifiers capable of driving

loads of either line level or headphone level impedance. The advanced multi-bit DAC used in

WM8759 produces far less out of band noise than single bit traditional sigma delta DACs, and so

in most applications where line level output is required, no post DAC filter is required. Typically an

AC coupling capacitor and a DC setting resistor to ground are the only components required on

the output of the chip.

CLOCKING SCHEMES

In a typical digital audio system there is only one central clock source producing a reference clock

to which all audio data processing is synchronised. This clock is often referred to as the audio

system’s Master Clock. The external master clock can be applied directly through the MCLK input

pin with no configuration necessary for sample rate selection.

Note that on the WM8759, MCLK is used to derive clocks for the DAC path. The DAC path

consists of DAC sampling clock, DAC digital filter clock and DAC digital audio interface timing. In

a system where there are a number of possible sources for the reference clock it is recommended

that the clock source with the lowest jitter be used to optimise the performance of the DAC.

The device can be powered down by stopping MCLK. In this state the power consumption is

substantially reduced.

DIGITAL AUDIO INTERFACE

Audio data is applied to the internal DAC filters via the Digital Audio Interface. Three interface

formats are supported:

•

Right Justified mode

I²S mode

DSP mode

All formats send the MSB first. The data format is selected with the FORMAT pin. When

FORMAT is LOW, right justified data format is selected and word lengths of 16-bits may be used.

When the FORMAT pin is HIGH, I²S format is selected and word length of any value up to 24-bits

may be used. (If a word length shorter than 24-bits is used, the unused bits should be padded

with zeros). If LRCIN is 4 BCKINs or less duration, the DSP compatible format is selected. Early

and Late clock formats are supported, selected by the state of the FORMAT pin.

‘Packed’ mode (i.e. only 32 or 48 clocks per LRCIN period) operation is also supported in both I²S

(16-24 bits) and right justified formats, (16 bit). If a ‘packed’ format of 16-bit word length is applied

(16 BCKINS per LRCIN half period), the device auto-detects this mode and switches to 16-bit

data length.

I²S MODE

The WM8759 supports word lengths of 16-24 bits in I²S mode.

In I²S mode, the digital audio interface receives data on the DIN input. Audio Data is time

multiplexed with LRCIN indicating whether the left or right channel is present. LRCIN is also used

as a timing reference to indicate the beginning or end of the data words.

In I²S modes, the minimum number of BCKINs per LRCIN period is 2 times the selected word

length. LRCIN must be high for a minimum of word length BCKINs and low for a minimum of word

length BCKINs. Any mark to space ratio on LRCIN is acceptable provided the above requirements

are met. In I²S mode, the MSB is sampled on the second rising edge of BCKIN following a LRCIN

transition. LRCIN is low during the left samples and high during the right samples.

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WM8759

1/fs

LEFT CHANNEL

RIGHT CHANNEL

LRCIN

BCKIN

1 BCKIN

DIN

1

2

3

n

1

2

3

n

n-2 n-1

LSB

MSB

Figure 3 I²S Mode Timing Diagram

RIGHT JUSTIFIED MODE

The WM8759 supports word lengths of 16-bits in right justified mode.

In right justified mode, the digital audio interface receives data on the DIN input. Audio Data is

time multiplexed with LRCIN indicating whether the left or right channel is present. LRCIN is also

used as a timing reference to indicate the beginning or end of the data words.

In right justified mode, the minimum number of BCKINs per LRCIN period is 2 times the selected

word length. LRCIN must be high for a minimum of word length BCKINs and low for a minimum of

word length BCKINs. Any mark to space ratio on LRCIN is acceptable provided the above

requirements are met.

In right justified mode, the LSB is sampled on the rising edge of BCKIN preceding a LRCIN

transition. LRCIN is high during the left samples and low during the right samples.

1/fs

LEFT CHANNEL

RIGHT CHANNEL

LRCIN

BCKIN

DIN

1

2

3

1

2

3

14 15

16

MSB

LSB

MSB

LSB

Figure 4 Right Justified Mode Timing Diagram

DSP MODE

A DSP compatible, time division multiplexed format is also supported by the WM8759. This

format is of the type where a ‘synch’ pulse is followed by two data words (left and right) of

predetermined word length. (16-bits). The ‘synch’ pulse replaces the normal duration LRCIN, and

DSP mode is auto-detected by the shorter than normal duration of the LRCIN. If LRCIN is of 4

BCKIN or less duration, the DSP compatible format is selected. Early and Late clock formats are

supported, selected by the state of the FORMAT pin.

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Advanced Information

1/fs

Max 4 BCKIN's

LRCIN

BCKIN

LEFT CHANNEL

RIGHT CHANNEL

NO VALID DATA

1

2

1

2

1

DIN

15

16

MSB

LSB

Input Word Length (16 bits)

Figure 5 DSP ‘Late’ Mode Timing

1 BCKIN

1/fs

max 4 BCKIN's

LRCIN

BCKIN

LEFT CHANNEL

RIGHT CHANNEL

NO VALID DATA

1

2

1

2

DIN

15

16

15

16

MSB

LSB

Input Word Length (16 bits)

Figure 6 DSP ‘Early’ Mode Timing

AUDIO DATA SAMPLING RATES

The master clock for WM8759 supports audio sampling rates from 128fs to 768fs, where fs is the

audio sampling frequency (LRCIN) typically 32kHz, 44.1kHz, 48kHz, 96kHz or 192kHz. The

master clock is used to operate the digital filters and the noise shaping circuits.

The WM8759 has a master clock detection circuit that automatically determines the relation

between the master clock frequency and the sampling rate (to within +/- 8 master clocks). If there

is a greater than 8 clocks error, the interface shuts down the DAC and mutes the output. The

master clock should be synchronised with LRCIN, although the WM8759 is tolerant of phase

differences or jitter on this clock.

SAMPLING

RATE

MASTER CLOCK FREQUENCY (MHZ) (MCLK)

128fs

192fs

256fs

384fs

512fs

768fs

(LRCIN)

32kHz

44.1kHz

48kHz

4.096

5.6448

6.144

12.288

24.576

6.144

8.467

8.192

11.2896

12.288

24.576

12.288

16.9344

18.432

36.864

16.384

22.5792

24.576

33.8688

36.864

9.216

18.432

36.864

96kHz

Unavailable Unavailable

192kHz

Unavailable Unavailable Unavailable Unavailable

Table 1 Master Clock Frequencies Versus Sampling Rate

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HARDWARE CONTROL MODES

The WM8759 is hardware programmable providing the user with options to select input audio data

format, de-emphasis and mute.

ENABLE OPERATION

Pin 4 (ENABLE) controls the operation of the chip. If ENABLE is low the device is held in a low

power state. If this pin is held high the device is powered up.

To ensure correct operation it is essential that there is a low to high transition on the ENABLE pin

after digital supplies have come on. This can be achieved by providing the ENABLE signal from

an external controller chip or by means of a simple RC network on the ENABLE pin. See

“Recommended External Components” in the “Application Information” section at the end of this

datasheet.

Note that the ENABLE pin should not be used as a mute pin or to temporarily silence the DAC

(between tracks of a CD for example). The ENABLE pin is not intended to be used as a mute

control but to allow entry into low power mode. Disabling the device via the ENABLE pin has the

effect of powering down the voltage on the CAP pin. Repeated enabling/disabling of the device

can cause audible pops at the output.

HIGH PERFORMANCE MODE

On the rising edge of ENABLE, the DEEMPH pin is sampled. If it is low the device powers up

normally. If it is high the device goes into a high performance and high power consumption state.

Once ENABLE is high, DEEMPH controls the selection of the de-emphasis filter.

INPUT AUDIO FORMAT SELECTION

FORMAT (pin 13) controls the data input format.

FORMAT

INPUT DATA MODE

16 bit right justified

16–24 bit I²S

0

1

Table 2 Input Audio Format Selection

Notes:

1. In 16-24 bit I²S mode, any data from 16-24 bits or more is supported provided that LRCIN is

high for a minimum of data width BCKINs and low for a minimum of data width BCKINs,

unless Note 2. For data widths greater than 24 bits, the LSB’s will be truncated and the

most significant 24 bits will be used by the internal processing.

2. If exactly 16 BCKIN cycles occur in both the low and high period of LRCIN the WM8759 will

assume the data is 16-bit and accept the data accordingly.

INPUT DSP FORMAT SELECTION

FORMAT

50% LRCIN DUTY CYCLE

LRCIN of 4 BCKIN or Less Duration

0

16 bit

DSP format – ‘late’ mode

(MSB-first, right justified)

1

I²S format up to 24 bit

DSP format – ‘early’ mode

(Philips serial data protocol)

Table 3 DSP Interface Formats

DE-EMPHASIS CONTROL

DEEMPH (pin 12) is an input control for selection of de-emphasis filtering to be applied.

DEEMPH

DE-EMPHASIS

0

Off

On

1

Table 4 De-emphasis Control

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DIGITAL FILTER CHARACTERISTICS

PARAMETER

Passband Edge

SYMBOL

TEST CONDITIONS

-3dB

MIN

TYP

MAX

UNIT

0.487fs

Passband Ripple

f < 0.444fs

f > 0.555fs

0.05

dB

Stopband Attenuation

-60

Table 5 Digital Filter Characteristics

DAC FILTER RESPONSES

0.2

0.15

0.1

0

-20

-40

0.05

0

-60

-0.05

-0.1

-0.15

-0.2

-80

-100

-120

0

0.5

1

1.5

2

2.5

3

0

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0.4

0.45

0.5

Frequency (Fs)

Figure 7 DAC Digital Filter Frequency Response

-44.1, 48 and 96kHz

Figure 8 DAC Digital Filter Ripple

-44.1, 48 and 96kHz

0.2

0

-20

-40

-60

-80

0

-0.2

-0.4

-0.6

-0.8

-1

0

0.2

0.4

0.6

0.8

1

0

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0.4

0.45

0.5

Frequency (Fs)

Figure 9 DAC Digital Filter Frequency Response -192kHz

Figure 10 DAC Digital Filter Ripple -192kHz

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DIGITAL DE-EMPHASIS CHARACTERISTICS

0

1

0.5

0

-2

-4

-0.5

-1

-6

-1.5

-2

-8

-2.5

-3

-10

0

2

4

6

8

10

12

14

16

0

2

4

6

8

10

12

14

16

Frequency (kHz)

Figure 11 De-Emphasis Frequency Response (32kHz)

Figure 12 De-Emphasis Error (32kHz)

0

0.4

0.3

0.2

0.1

0

-2

-4

-6

-0.1

-0.2

-0.3

-0.4

-8

-10

0

5

10

15

20

0

5

10

15

20

Frequency (kHz)

Figure 13 De-Emphasis Frequency Response (44.1kHz)

Figure 14 De-Emphasis Error (44.1kHz)

0

1

0.8

0.6

0.4

0.2

0

-2

-4

-6

-0.2

-0.4

-0.6

-0.8

-1

-8

-10

0

5

10

15

20

0

5

10

15

20

Frequency (kHz)

Figure 15 De-Emphasis Frequency Response (48kHz)

Figure 16 De-Emphasis Error (48kHz)

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WM8759

Advanced Information

APPLICATIONS INFORMATION

RECOMMENDED EXTERNAL COMPONENTS

Figure 17 External Component Diagram

In an application where ENABLE is fed directly from VDD rather than a dedicated control line,

resistor R3 and capacitor C9 are used on the ENABLE pin to introduce a short delay in the Low to

High transition of ENABLE. This will ensure the pin goes high after power supplies have had time

to settle (see “ENABLE Operation” in the “Hardware Control Modes” section of the datasheet).

However, if the ENABLE signal is being provided from an external controller chip rather than VDD

directly, R3 and C9 will not be required.

POWER UP/DOWN SEQUENCE

For click free operation, the WM8759 should be powered up and down in a specific sequence.

Power-up:

1. Power up AVDD and DVDD and wait to settle

2. Turn on clocks and data (MCLK, BCLK, LRCLK, SDATA)

3. Switch ENABLE pin from low to high

Power-down:

1. Switch Enable from high to low

2. Remove clocks and data

3. Power down AVDD and DVDD

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Advanced Information

WM8759

PCB LAYOUT RECOMMENDATIONS

Care should be taken in the layout of the PCB that the WM8759 is to be mounted to. The

following notes will help in this respect:

1. The VDD supply to the device should be as noise free as possible. This can be

accomplished to a large degree with a 10uF bulk capacitor placed locally to the device and a

0.1uF high frequency decoupling capacitor placed as close to the VDD pin as possible. It is

best to place the 0.1uF capacitor directly between the VDD and GND pins of the device on

the same layer to minimize track inductance and thus improve device decoupling

effectiveness.

2. The CAP pin should be as noise free as possible. This pin provides the decoupling for

the on chip reference circuits and thus any noise present on this pin will be directly coupled

to the device outputs. In a similar manner to the VDD decoupling described above, this pin

should be decoupled with a 10uF bulk capacitor local to the device and a 0.1uF capacitor as

close to the CAP pin as possible.

3. Separate analogue and digital track routing from each other. The device is split into

analogue (pins 5 – 9) and digital (pins 1 – 4 and pins 10 – 14) sections that allow the routing

of these signals to be easily separated. By physically separating analogue and digital

signals, crosstalk from the PCB can be minimized.

4. Use an unbroken solid GND plane. To achieve best performance from the device, it is

advisable to have either a GND plane layer on a multilayer PCB or to dedicate one side of a

2 layer PCB to be a GND plane. For double sided implementations it is best to route as

many signals as possible on the device mounted side of the board, with the opposite side

acting as a GND plane. The use of a GND plane greatly reduces any electrical emissions

from the PCB and minimizes crosstalk between signals.

An evaluation board is available for the WM8759 that demonstrates the above techniques and the

excellent performance achievable from the device. This can be ordered or the User manual

downloaded from the Wolfson web site at www.wolfsonmicro.com

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WM8759

Advanced Information

PACKAGE DRAWING

DM001.C

D: 14 PIN SOIC 3.9mm Wide Body

e

B

14

8

H

E

1

7

D

L

h x 45^o

A1

SEATING PLANE

-C-

α

C

A

0.10 (0.004)

Dimensions

(MM)

Dimensions

(Inches)

Symbols

MIN

MAX

1.75

0.25

0.51

0.25

8.75

4.00

MIN

MAX

A

A1

B

C

D

E

1.35

0.10

0.33

0.19

8.55

3.80

0.0532

0.0040

0.0130

0.0075

0.3367

0.1497

0.0688

0.0098

0.0200

0.0098

0.3444

0.1574

e

1.27 BSC

0.05 BSC

H

h

L

5.80

0.25

0.40

0^o

6.20

0.50

1.27

8^o

0.2284

0.0099

0.0160

0^o

0.2440

0.0196

0.0500

8^o

α

REF:

JEDEC.95, MS-012

NOTES:

A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS (INCHES).

B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE.

C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.25MM (0.010IN).

D. MEETS JEDEC.95 MS-012, VARIATION = AB. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS.

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Advanced Information

WM8759

IMPORTANT NOTICE

Wolfson Microelectronics plc (WM) reserve the right to make changes to their products or to discontinue any product or service

without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that

information being relied on is current. All products are sold subject to the WM terms and conditions of sale supplied at the time

of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability.

WM warrants performance of its products to the specifications applicable at the time of sale in accordance with WM’s standard

warranty. Testing and other quality control techniques are utilised to the extent WM deems necessary to support this warranty.

Specific testing of all parameters of each device is not necessarily performed, except those mandated by government

requirements.

In order to minimise risks associated with customer applications, adequate design and operating safeguards must be used by

the customer to minimise inherent or procedural hazards. Wolfson products are not authorised for use as critical components in

life support devices or systems without the express written approval of an officer of the company. Life support devices or

systems are devices or systems that are intended for surgical implant into the body, or support or sustain life, and whose failure

to perform when properly used in accordance with instructions for use provided, can be reasonably expected to result in a

significant injury to the user. A critical component is any component of a life support device or system whose failure to perform

can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.

WM assumes no liability for applications assistance or customer product design. WM does not warrant or represent that any

license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property

right of WM covering or relating to any combination, machine, or process in which such products or services might be or are

used. WM’s publication of information regarding any third party’s products or services does not constitute WM’s approval,

license, warranty or endorsement thereof.

Reproduction of information from the WM web site or datasheets is permissible only if reproduction is without alteration and is

accompanied by all associated warranties, conditions, limitations and notices. Representation or reproduction of this information

with alteration voids all warranties provided for an associated WM product or service, is an unfair and deceptive business

practice, and WM is not responsible nor liable for any such use.

Resale of WM’s products or services with statements different from or beyond the parameters stated by WM for that product or

service voids all express and any implied warranties for the associated WM product or service, is an unfair and deceptive

business practice, and WM is not responsible nor liable for any such use.

ADDRESS:

Wolfson Microelectronics plc

Westfield House

26 Westfield Road

Edinburgh

EH11 2QB

United Kingdom

Tel :: +44 (0)131 272 7000

Fax :: +44 (0)131 272 7001

Email :: sales@wolfsonmicro.com

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型号:	WM8759GED/V
是否Rohs认证：	符合
生命周期：	Obsolete
IHS 制造商：	WOLFSON MICROELECTRONICS LTD
包装说明：	,
Reach Compliance Code：	compliant
风险等级：	5.57
湿度敏感等级：	2
Base Number Matches：	1

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