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产品型号WM8782SEDS的概述

芯片WM8782SEDS的概述 WM8782SEDS是一款由英国Wolfson Microelectronics (现为Cirrus Logic的一部分) 设计的高级音频ADC（模数转换器）。该芯片专为高品质音频应用而开发，适用于专业音频设备，如数字音频工作站、音频接口、便携式音乐播放设备及其他消费电子产品。WM8782SEDS提供了高达24位的解析度和192kHz的采样率，能够满足各种对音质要求极高的应用场合。 WM8782SEDS采用了低功耗设计，能够在各种环境下高效工作。此外，芯片内部集成了数字滤波器和可编程增益放大器（PGA），使其在即使极低的信噪比环境下也能提供优越的音质。这种细致的设计使得WM8782SEDS成为音频工程师和开发者的热门选择。芯片WM8782SEDS的详细参数 WM8782SEDS的技术规范包括但不限于以下几个方面： 1. 音频性能： - 解析度：2...

产品型号WM8782SEDS的Datasheet PDF文件预览

WM8782

24-Bit, 192kHz Stereo ADC

DESCRIPTION

FEATURES

•

SNR 102dB (‘A’ weighted @ 48kHz)

THD -90dB (at –1dB)

Sampling Frequency: 8 – 192kHz

Master or Slave Clocking Mode

System Clock (MCLK): 128fs, 192fs, 256fs, 384fs, 512fs,

768fs

The WM8782 is a high performance, low cost stereo audio

ADC designed for recordable media applications.

The device offers stereo line level inputs along with two

control input pins (FORMAT, IWL) to allow operation of the

audio interface in three industry standard modes. An

internal op-amp is integrated on the front end of the chip to

•

Audio Data Interface Modes

16-24 bit I²S, 16-24 bit Left, 16-24 bit Right Justified

accommodate analogue input signals greater than 1V_rms

The device also has a high pass filter to remove residual

DC offsets.

Supply Voltages

Analogue 2.7 to 5.5V

Digital core: 2.7V to 3.6V

WM8782 offers Master or Slave mode clocking schemes.

A control input pin M/S is used to allow Slave mode

operation or Master mode operation. A stereo 24-bit multi-

bit sigma-delta ADC is used with 128x, 64x or 32x over-

sampling, according to sample rate. Digital audio output

word lengths from 16-24 bits and sampling rates from

8kHz to 192kHz are supported.

•

20-pin SSOP package

APPLICATIONS

•

Recordable DVD Players

Personal Video Recorders

STB

Studio Audio Processing Equipment

The device is a hardware controlled device and is supplied

in a 20-SSOP package.

BLOCK DIAGRAM

Product Preview, May 2004, Rev 1.0

WOLFSON MICROELECTRONICS plc

www.wolfsonmicro.com

WM8782

Product Preview

TABLE OF CONTENTS

DESCRIPTION .......................................................................................................1

FEATURES.............................................................................................................1

APPLICATIONS .....................................................................................................1

BLOCK DIAGRAM .................................................................................................1

TABLE OF CONTENTS .........................................................................................2

PIN CONFIGURATION...........................................................................................3

ORDERING INFORMATION ..................................................................................3

PIN DESCRIPTION ................................................................................................4

ABSOLUTE MAXIMUM RATINGS.........................................................................5

RECOMMENDED OPERATING CONDITIONS .....................................................5

ELECTRICAL CHARACTERISTICS ......................................................................6

TERMINOLOGY............................................................................................................. 7

SIGNAL TIMING REQUIREMENTS.......................................................................8

DEVICE DESCRIPTION.......................................................................................10

INTRODUCTION.......................................................................................................... 10

ADC ............................................................................................................................. 10

ADC DIGITAL FILTER ................................................................................................. 10

DIGITAL AUDIO INTERFACE...................................................................................... 11

POWER DOWN CONTROL......................................................................................... 13

POWER-ON RESET.................................................................................................... 14

DIGITAL FILTER CHARACTERISTICS...............................................................15

ADC FILTER RESPONSES ......................................................................................... 15

ADC HIGH PASS FILTER............................................................................................ 16

APPLICATIONS INFORMATION .........................................................................17

RECOMMENDED EXTERNAL COMPONENTS........................................................... 17

RECOMMENDED EXTERNAL COMPONENTS VALUES............................................ 17

PACKAGE DIMENSIONS ....................................................................................18

IMPORTANT NOTICE..........................................................................................19

ADDRESS:................................................................................................................... 19

PP, May 2004, Rev 1.0

Product Preview

WM8782

PIN CONFIGURATION

M/S

MCLK

DOUT

LRCLK

DGND

DVDD

BCLK

AINL

AINOPL

COM

AINR

AINOPR

AGND

IWL

FSAMPEN

FORMAT

VMID

AVDD

VREFP

VREFGND

ORDERING INFORMATION

DEVICE

TEMPERATURE

RANGE

PACKAGE

MOISTURE SENSITIVITY

LEVEL

PEAK SOLDERING

TEMPERATURE

WM8782SEDS

-25°C to +85°C

20-pin SSOP

(lead free)

MSL1

260^oC

WM8782SEDS/R

-25°C to +85°C

20-pin SSOP

(lead free, tape and reel)

MSL1

260^oC

Note:

Reel quantity = 2,000

PP, May 2004, Rev 1.0

WM8782

Product Preview

PIN DESCRIPTION

PIN NO.

NAME

MCLK

DOUT

LRCLK

DGND

DVDD

BCLK

IWL

TYPE

Digital Input

DESCRIPTION

Master Clock

Digital Output

Digital Input / Output

Supply

ADC Digital Audio Data

Audio Interface Left / Right Clock

Digital Negative Supply

Digital Positive Supply

Audio Interface Bit Clock

Word Length

Supply

Digital Input / Output

Digital Tristate Input

0 = 16 bit

1 = 20 bit

Z = 24 bit

FSAMPEN

FORMAT

Digital Tristate Input

Fast Sampling Rate Enable

0 = 48ken

1= 96ken

Z= 192ken

Audio Mode Select

0 = RJ

1 = LJ

Z = I2S

VMID

VREFGND

VREFP

AVDD

Analogue Output

Supply

Midrail Voltage Decoupling Capacitor

Negative Supply and Substrate Connection

Analogue Output

Supply

Positive Reference Voltage Decoupling Pin; 10uF external decoupling

Analogue Positive Supply

AGND

AINOPR

AINR

Supply

Analogue Negative Supply and Substrate Connection

Right Channel Internal Op-Amp Output

Right Channel Input

Analogue Output

Analogue Input

Analogue Output

Analogue Input

Digital Input

COM

Common mode high impedance input should be set to midrail.

Left Channel Internal Op-Amp Output

Left Channel Input

AINOPL

AINL

M/S

Interface Mode Select

0 = Slave mode (128fs, 192fs, 256fs, 384fs, 512fs, 768fs)

1 = Master mode (256fs, 128fs)

(fs=word clock frequency)

PP, May 2004, Rev 1.0

Product Preview

WM8782

ABSOLUTE MAXIMUM RATINGS

Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously

operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given

under Electrical Characteristics at the test conditions specified.

ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible

to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage

of this device.

Wolfson tests its package types according to IPC/JEDEC J-STD-020B for Moisture Sensitivity to determine acceptable storage

conditions prior to surface mount assembly. These levels are:

MSL1 = unlimited floor life at <30°C / 85% Relative Humidity. Not normally stored in moisture barrier bag.

MSL2 = out of bag storage for 1 year at <30°C / 60% Relative Humidity. Supplied in moisture barrier bag.

MSL3 = out of bag storage for 168 hours at <30°C / 60% Relative Humidity. Supplied in moisture barrier bag.

The Moisture Sensitivity Level for each package type is specified in Ordering Information.

CONDITION

MIN

-0.3V

MAX

+3.63V

Digital supply voltage

Analogue supply voltage

Voltage range digital inputs

Voltage range analogue inputs

-0.3V

+7V

DGND -0.3V

AGND -0.3V

-25°C

DVDD + 0.3V

AVDD +0.3V

+85°C

+Operating temperature range, T_A

Storage temperature after soldering

Notes

-65°C

+150°C

1. Analogue and digital grounds must always be within 0.3V of each other.

RECOMMENDED OPERATING CONDITIONS

PARAMETER

Digital supply range

Analogue supply range

Ground

SYMBOL

DVDD

TEST CONDITIONS

MIN

2.7

TYP

MAX

3.6

UNIT

AVDD

2.7

5.5

DGND,AGND

Notes

1. Digital supply DVDD must never be more than 0.3V greater than AVDD.

PP, May 2004, Rev 1.0

WM8782

Product Preview

ELECTRICAL CHARACTERISTICS

Test Conditions

DVDD = 3.3V, AVDD = 5.0V, T_A= +25^oC, 1kHz signal, A-weighted, fs = 48kHz, MCLK = 256fs, 24-bit audio data, Slave Mode

unless otherwise stated.

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V_rms

kΩ

ADC Performance

Full Scale Input Signal Level

(for ADC 0dB Input)

1.0

Input resistance, using

recommended external resistor

network on p17.

Input capacitance

Signal to Noise Ratio

(see Terminology note 1,2,4)

SNR

A-weighted,

@ fs = 48kHz

Unweighted,

@ fs = 48kHz

A-weighted,

102

100

@ fs = 48kHz, AVDD =

3.3V

Signal to Noise Ratio

(see Terminology note 1,2,4)

A-weighted,

@ fs = 96kHz

Unweighted,

@ fs = 96kHz

A-weighted,

@ fs = 96kHz, AVDD =

3.3V

Total Harmonic Distortion

THD

DNR

1kHz, -1dB Full Scale

@ fs = 48kHz

-90

1kHz, -1dB Full Scale

@ fs = 96kHz

1kHz, -1dB Full Scale

@ fs = 192kHz

Dynamic Range

-60dBFS

102

ADC Channel Separation

(see Terminology note 4)

1kHz Input

20kHz

0.1

Channel Level Matching

Channel Phase Deviation

Power Supply Rejection Ratio

1kHz signal

0.0001

Degree

PSRR

1kHz 100mVpp, applied

to AVDD, DVDD

20Hz to 20kHz

100mVpp

Digital Logic Levels (TTL Levels)

Input LOW level

0.8

Input HIGH level

V_IH

2.0

-1

Input leakage current – digital pad

0.2

µA

Input leakage current – digital

tristate input (Note 3)

Input capacitance

Output LOW

V_OL

V_OH

_OL=1mA

0.1 x DVDD

Output HIGH

_OH= -1mA

0.9 x DVDD

PP, May 2004, Rev 1.0

Product Preview

WM8782

Analogue Reference Levels

Midrail Reference Voltage

VMID

AVDD to VMID and

VMID to VREFN

–3%

AVDD/2

+3%

Potential Divider Resistance

Buffered Reference Voltage

VREF source current

VREF sink current

R_VMID

VREFP

I_VREF

kΩ

AVDD/2

+3%

I_VREF

Supply Current

Analogue supply current

Digital supply current

Power Down

AVDD = 5V

DVDD = 3.3V

0.5

Notes:

1. All performance measurements are done with a 20kHz low pass filter, and where noted an A-weight filter, except

where noted. Failure to use such a filter will result in higher THD+N and lower SNR and Dynamic Range readings than

are found in the Electrical Characteristics. The low pass filter removes out of band noise; although this is not audible,

it may affect dynamic specification values.

2. VMID is decoupled with 10uF and 0.1uF capacitors close to the device package. Smaller capacitors may reduce

performance.

3. This high leakage current is due to the topology of the instate pads. The pad input is connected to the midpoint of an

internal resistor string to pull input to vmid if undriven.

TERMINOLOGY

1. Signal-to-noise ratio (dB) – Ratio of output level with 1kHz full scale input, to the output level with all zeros into the

digital input, over a 20Hz to 20kHz bandwidth. (No Auto-zero or Automute function is employed in achieving these

results).

2. Dynamic range (dB) – DR is a measure of the difference between the highest and lowest portions of a signal.

Normally a THD+N measurement at 60dB below full scale. The measured signal is then corrected by adding the 60dB

to it. (e.g. THD+N @ -60dB= -32dB, DR= 92dB).

3. THD+N (dB) – THD+N is a ratio, of the rms values, of (Noise + Distortion)/Signal.

4. Channel Separation (dB) – Also known as Cross-Talk. This is a measure of the amount one channel is isolated from

the other. Normally measured by sending a full scale signal down one channel and measuring the other.

PP, May 2004, Rev 1.0

WM8782

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SIGNAL TIMING REQUIREMENTS

SYSTEM CLOCK TIMING

Figure 1 System Clock Timing Requirements

Test Conditions

DVDD = 3.3V, DGND = 0V, T_A= +25^oC, Slave Mode, fs = 48kHz, Slave Mode, MCLK = 256fs, 24-bit data, unless otherwise

stated.

PARAMETER

SYMBOL

MIN

TYP

MAX

UNIT

System Clock Timing Information

MCLK System clock pulse width high

MCLK System clock pulse width low

MCLK System clock cycle time

MCLK duty cycle

T_MCLKL

T_MCLKH

T_MCLKY

T_MCLKDS

40:60

60:40

Table 1 Master Clock Timing Requirements

AUDIO INTERFACE TIMING – MASTER MODE

Figure 2 Digital Audio Data Timing – Master Mode (see Control Interface)

Test Conditions

DVDD = 3.3V, DGND = 0V, T_A= +25^oC, Master Mode, fs = 48kHz, MCLK = 256fs, 24-bit data, unless otherwise stated.

PARAMETER

SYMBOL

MIN

TYP

MAX

UNIT

Audio Data Input Timing Information

LRCLK propagation delay from BCLK falling edge

DOUT propagation delay from BCLK falling edge

t_DL

t_DDA

Table 2 Digital Audio Data Timing - Master Mode

PP, May 2004, Rev 1.0

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WM8782

AUDIO INTERFACE TIMING – SLAVE MODE

Figure 3 Digital Audio Data Timing – Slave Mode

Test Conditions

DVDD = 3.3V, DGND = 0V, T_A= +25^oC, Slave Mode, fs = 48kHz, MCLK = 256fs, 24-bit data, unless otherwise stated.

PARAMETER

SYMBOL

MIN

TYP

MAX

UNIT

Audio Data Input Timing Information

BCLK cycle time

t_BCY

t_BCH

t_BCL

t_LRSU

t_LRH

t_DD

BCLK pulse width high

BCLK pulse width low

LRCLK set-up time to BCLK rising edge

LRCLK hold time from BCLK rising edge

DOUT propagation delay from BCLK falling edge

Table 3 Digital Audio Data Timing - Slave Mode

Note:

LRCLK should be synchronous with MCLK, although the WM8782 interface is tolerant of phase variations or jitter on these

signals.

PP, May 2004, Rev 1.0

WM8782

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DEVICE DESCRIPTION

INTRODUCTION

The WM8782 is a stereo 24-bit ADC designed for demanding recording applications such as DVD

recorders, studio mixers, PVRs, and AV amplifiers. The WM8782 consists of stereo line level inputs,

followed by a sigma-delta modulator and digital filtering.

The device offers stereo line level inputs along with two control input pins (FORMAT, IWL) to allow

operation of the audio interface in three industry standard modes (left justified, right justified or I²S) .

An internal op-amp is integrated on the front end of the chip to accommodate analogue input signals

greater than 1V_rms. The device also has a high pass filter to remove residual DC offsets.

The WM8782 offers Master or Slave mode clocking schemes. A control input pin M/S is used to allow

Slave mode or Master mode operation. The WM8782 supports master clock rates from 128fs to

768fs and digital audio output word lengths from 16-24 bits. Sampling rates from 8kHz to 192kHz are

supported, delivering high SNR operating with 128x, 64x or 32x over-sampling, according to the

sample rate.

The line inputs are biased internally through the operational amplifier to V_MID

ADC

The WM8782 uses a multi-bit over sampled sigma-delta ADC. A single channel of the ADC is

illustrated in Figure 4 Multi-Bit Oversampling Sigma Delta ADC Schematic.

ANALOG

INTEGRATOR

LIN/RIN

TO ADC DIGITAL FILTERS

MULTI

BITS

Figure 4 Multi-Bit Oversampling Sigma Delta ADC Schematic

The use of multi-bit feedback and high oversampling rates reduces the effects of jitter and high

frequency noise.

The ADC Full Scale input is 1.0V rms at AVDD = 5.0 volts. Any voltage greater than full scale will

possibly overload the ADC and cause distortion. Note that the full scale input has a linear relationship

with AVDD. The internal op-amp and appropriate resistors can be used to reduce signals greater

than 1Vrms before they reach the ADC.

The ADC filters perform true 24 bit signal processing to convert the raw multi-bit oversampled data

from the ADC to the correct sampling frequency to be output on the digital audio interface.

ADC DIGITAL FILTER

The ADC digital filters contain a digital high pass filter. The high-pass filter response detailed in

Digital Filter Characteristics. The operation of the high pass filter removes residual DC offsets that

are present on the audio signal.

PP, May 2004, Rev 1.0

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WM8782

DIGITAL AUDIO INTERFACE

The digital audio interface uses three pins:

•

DOUT: ADC data output

LRCLK: ADC data alignment clock

BCLK: Bit clock, for synchronisation

The digital audio interface takes the data from the internal ADC digital filters and places it on DOUT

and LRCLK. DOUT is the formatted digital audio data stream output from the ADC digital filters with

left and right channels multiplexed together. LRCLK is an alignment clock that controls whether Left

or Right channel data is present on the DOUT line. DOUT and LRCLK are synchronous with the

BCLK signal with each data bit transition signified by a BCLK high to low transition. DOUT is always

an output. BCLK and LRCLK maybe an inputs or outputs depending whether the device is in Master

or Slave mode. (see Master and Slave Mode Operation, below).

Three different audio data formats are supported:

•

Left justified

Right justified

I²S

MASTER AND SLAVE MODE OPERATION

The WM8782 can be configured as either a master or slave mode device. As a master device the

WM8782 generates BCLK and LRCLK and thus controls sequencing of the data transfer on DOUT.

In slave mode, the WM8782 responds with data to clocks it receives over the digital audio interface.

The mode can be selected by setting the MS input pin (see Table 4 Master/Slave selection below).

Master and slave modes are illustrated below.

Figure 5 Master Mode

Figure 6 Slave Mode

DESCRIPTION

M/S

Master/Slave Selection

0 = Slave Mode

1= Master Mode

Table 4 Master/Slave selection

AUDIO INTERFACE CONTROL

The Input Word Length and Audio Format mode can be selected by using IWL and FORMAT pins.

PIN DESCRIPTION

IWL

Word Length

0 = 16 bit

1 = 20 bit

Z = 24 bit

FORMAT

Audio Mode Select

0 = RJ

1 = LJ

Z = I2S

Table 5 Audio Data Format Control

PP, May 2004, Rev 1.0

WM8782

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AUDIO DATA FORMATS

In Left Justified mode, the MSB is available on the first rising edge of BCLK following an LRCLK

transition. The other bits up to the LSB are then transmitted in order. Depending on word length,

BCLK frequency and sample rate, there may be unused BCLK cycles before each LRCLK transition.

Figure 7 Left Justified Audio Interface (assuming n-bit word length)

In Right Justified mode, the LSB is available on the last rising edge of BCLK before an LRCLK

transition. All other bits are transmitted before (MSB first). Depending on word length, BCLK

frequency and sample rate, there may be unused BCLK cycles after each LRCLK transition.

Figure 8 Right Justified Audio Interface (assuming n-bit word length)

In I²S mode, the MSB is available on the second rising edge of BCLK following an LRCLK transition.

The other bits up to the LSB are then transmitted in order. Depending on word length, BCLK

frequency and sample rate, there may be unused BCLK cycles between the LSB of one sample and

the MSB of the next.

Figure 9 - I²S Justified Audio Interface (assuming n-bit word length)

PP, May 2004, Rev 1.0

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WM8782

MASTER CLOCK AND AUDIO SAMPLE RATES

In a typical digital audio system there is only one central clock source producing a reference clock to

which all audio data processing is synchronised. This clock is often referred to as the audio system’s

Master Clock (MCLK). The external master system clock can be applied directly through the MCLK

input pin. In a system where there are a number of possible sources for the reference clock it is

recommended that the clock source with the lowest jitter be used to optimise the performance of the

ADC.

The master clock is used to operate the digital filters and the noise shaping circuits. The WM8782

supports master clocks of 128fs, 192fs, 256fs, 384fs, 512fs and 768fs, where fs is the audio

sampling frequency (LRCLK). In Slave Mode, the WM8782 automatically detects the audio sample

rate. In Master Mode, LRCLK is generated for rate 256fs, unless the user changes this to 128fs

using the FSAMPEN pin = z (see Table 7 below). BCLK is also generated in Master Mode.

BCLK=MCLK/4 for 256fs, and BCLK=MCLK/2 for 128fs.

Table 6 shows the common MCLK frequencies for different sample rates.

SAMPLING RATE

(LRCLK)

Master Clock Frequency (MHz)

128fs

192fs

256fs

384fs

512fs

768fs

8kHz

16kHz

32kHz

44.1kHz

48kHz

96kHz

192kHz

1.024

2.048

1.536

3.072

6.144

8.467

9.216

18.432

36.864

2.048

4.096

8.192

3.072

6.144

4.096

8.192

6.144

12.288

24.576

4.096

12.288

16.384

5.6448

6.144

11.2896 16.9340 22.5792 33.8688

12.288

24.576

18.432

36.864

24.576

36.864

12.288

24.576

Table 6 Master Clock Frequency Selection

In Slave mode, the WM8782 has a master detection circuit that automatically determines the

relationship between the master clock frequency and the sampling rate (to within +/- 32 system

clocks). If there is a greater than 32 clocks error the interface sets itself to the highest rate available

(768fs). There must be a fixed number of MCLKS per LRCLK, although the WM8782 is tolerant of

phase variations or jitter on these clocks.

The WM8782 can operate at sample rates from 8kHz to 192kHz. The WM8782 uses a sigma-delta

modulator that operates at a fixed frequency of 6.144MHz (128 x LRCLK oversampling @ 48kHz

sampling rate). For correct operation of the device and optimal performance, the user must set the

appropriate ADC modulator sampling rate enable. In both Master and Slave Modes, it is

recommended that for 96kHz the user sets FSAMPEN to 1, and for 192kHz set FSAMPEN to z. For

Master Mode 192kHz, FSAMPEN set to z is a requirement.

DESCRIPTION

M/S

Master/Slave Selection

0 = Slave Mode (128fs, 192fs,

256fs, 384fs, 512fs, 768fs)

1= Master Mode (256fs, 128fs

when FSAMPEN=z)

FSAMPEN

Fast sampling rate enable

0 = 48ken (128x OSR)

1= 96ken (64x OSR)

z= 192ken (32x OSR)

Table 7 Master/Slave and sampling rate enable selection

POWER DOWN CONTROL

The WM8782 can be powered down by stopping MCLK. Power down mode using MCLK is entered

after 65536/fs clocks. On power-up, the WM8782 applies the power-on reset sequence described

below.

When MCLK is stopped DOUT is forced to zero.

PP, May 2004, Rev 1.0

WM8782

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POWER-ON RESET

The WM8782 has an internal power-on reset circuit. The reset sequence is entered at power-on or

power-up. Until the internal reset is removed, DOUT is forced to zero.

Figure 10 Power-on Reset Diagram

Figure 11 Power-on Reset Timing

PP, May 2004, Rev 1.0

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WM8782

DIGITAL FILTER CHARACTERISTICS

The WM8782 digital filter characteristics scale with sample rate.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

ADC Sample Rate (Single Rate – 48Hz typically)

Passband

+/- 0.01dB

-6dB

0.4535fs

+/- 0.01

0.4892fs

Passband Ripple

Stopband

0.5465fs

-65

Stopband Attenuation

Group Delay

f > 0.5465fs

ADC Sample Rate (Dual Rate – 96kHz typically)

Passband

+/- 0.01dB

0.4535fs

+/- 0.01

-6dB

0.4892fs

Passband Ripple

Stopband

0.5465fs

-65

Stopband Attenuation

Group Delay

f > 0.5465fs

Table 8 Digital Filter Characteristics

ADC FILTER RESPONSES

0.02

-20

-40

-60

-80

0.015

0.01

0.005

-0.005

-0.01

-0.015

-0.02

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0.4

0.45

0.5

1.5

2.5

Frequency (Fs)

Figure 12 Digital Filter Frequency Response

Figure 13 ADC Digital Filter Ripple

PP, May 2004, Rev 1.0

WM8782

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ADC HIGH PASS FILTER

The WM8782 has a digital highpass filter to remove DC offsets. The filter response is characterised by the following

polynomial.

1 - z^-1

H(z) =

1 - 0.9995z^-1

-5

-10

-15

0.0005

0.001

Frequency (Fs)

0.0015

0.002

Figure 14 ADC Highpass Filter Response

PP, May 2004, Rev 1.0

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WM8782

APPLICATIONS INFORMATION

RECOMMENDED EXTERNAL COMPONENTS

Figure 15 External Components Diagram

RECOMMENDED EXTERNAL COMPONENTS VALUES

COMPONENT

REFERENCE

SUGGESTED

VALUE

DESCRIPTION

C1 and C8

C2 and C7

C5 and C6

10µF

0.1µF

10µF

10kΩ

5kΩ

De-coupling for DVDD and AVDD

Analogue input AC coupling caps

Current limiting resistors

R2 and R5

R3 and R6

Internal op-amp input resistor

Internal op-amp feedback resistor

Common mode resistor

3.3kΩ

0.1µF

10µF

0.1µF

10µF

Reference de-coupling capacitors for VMID pin

Reference de-coupling capacitors for VREFP pin

C10

Table 9 External Components Description

PP, May 2004, Rev 1.0

WM8782

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PACKAGE DIMENSIONS

DS: 20 PIN SSOP (7.2 x 5.3 x 1.75 mm)

DM0015.B

GAUGE

PLANE

0.25

A A2

-C-

0.10 C

SEATING PLANE

Dimensions

(mm)

NOM

-----

Symbols

MIN

-----

MAX

2.0

-----

1.85

0.38

0.25

7.50

A₁

A₂

E₁

0.05

1.65

0.22

0.09

6.90

-----

1.75

0.30

-----

7.20

0.65 BSC

7.80

7.40

5.00

0.55

8.20

5.60

0.95

5.30

0.75

L₁

0.125 REF

0^o

4^o

8^o

JEDEC.95, MO 150

REF:

NOTES:

A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS.

B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE.

C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.20MM.

D. MEETS JEDEC.95 MO-150, VARIATION = AE. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS.

PP, May 2004, Rev 1.0

Product Preview

WM8782

IMPORTANT NOTICE

Wolfson Microelectronics plc (WM) reserve the right to make changes to their products or to discontinue any product or

service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing

orders, that information being relied on is current. All products are sold subject to the WM terms and conditions of sale

supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation

of liability.

WM warrants performance of its products to the specifications applicable at the time of sale in accordance with WM’s

standard warranty. Testing and other quality control techniques are utilised to the extent WM deems necessary to support

this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by

government requirements.

In order to minimise risks associated with customer applications, adequate design and operating safeguards must be used

by the customer to minimise inherent or procedural hazards. Wolfson products are not authorised for use as critical

components in life support devices or systems without the express written approval of an officer of the company. Life

support devices or systems are devices or systems that are intended for surgical implant into the body, or support or

sustain life, and whose failure to perform when properly used in accordance with instructions for use provided, can be

reasonably expected to result in a significant injury to the user. A critical component is any component of a life support

device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or

system, or to affect its safety or effectiveness.

WM assumes no liability for applications assistance or customer product design. WM does not warrant or represent that

any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual

property right of WM covering or relating to any combination, machine, or process in which such products or services might

be or are used. WM’s publication of information regarding any third party’s products or services does not constitute WM’s

approval, license, warranty or endorsement thereof.

Reproduction of information from the WM web site or datasheets is permissible only if reproduction is without alteration and

is accompanied by all associated warranties, conditions, limitations and notices. Representation or reproduction of this

information with alteration voids all warranties provided for an associated WM product or service, is an unfair and deceptive

business practice, and WM is not responsible nor liable for any such use.

Resale of WM’s products or services with statements different from or beyond the parametersstated by WM for that

product or service voids all express and any implied warranties for the associated WM product or service, is an unfair and

deceptive business practice, and WM is not responsible nor liable for any such use.

ADDRESS:

Wolfson Microelectronics plc

Westfield House

26 Westfield Road

Edinburgh

EH11 2QB

United Kingdom

Tel :: +44 (0)131 272 2000

Fax :: +44 (0)131 272 7001

Email :: sales@wolfsonmicro.com

PP, May 2004, Rev 1.0

WM8782SEDS相关文章

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WM8782SEDS产品参数

型号:	WM8782SEDS
是否Rohs认证：	符合
生命周期：	Transferred
IHS 制造商：	WOLFSON MICROELECTRONICS LTD
Reach Compliance Code：	unknown
风险等级：	5.57
Is Samacsys：	N
转换器类型：	D/A CONVERTER
输入位码：	BINARY
JESD-30 代码：	R-PDSO-G20
湿度敏感等级：	1
位数：	24
功能数量：	2
端子数量：	20
最高工作温度：	85 °C
最低工作温度：	-25 °C
封装主体材料：	PLASTIC/EPOXY
封装代码：	SSOP
封装等效代码：	SSOP20,.3
封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, SHRINK PITCH
电源：	3/3.3,3/5 V
认证状态：	Not Qualified
子类别：	Other Converters
表面贴装：	YES
技术：	CMOS
温度等级：	OTHER
端子形式：	GULL WING
端子节距：	0.635 mm
端子位置：	DUAL
Base Number Matches：	1

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