WS1403-TR1原理图各脚功能电路原理芯片引脚定义引脚图及功能-中国IC网-芯三七

WS1403

CDMA PCS 3x3 Power Ampliﬁer Module

(1850-1910 MHz)

Data Sheet

Description

Features

The WS1403 is a CDMA Personal Communication Service

(PCS) Power Ampliﬁer (PA), designed for handsets

operating in the 1850~1910 MHz bandwidth.

• Excellent linearity

• Low quiescent current

• High eﬃciency

Digital mode control of CoolPAM reduces current

consumption, which enables extended talk time of

mobile devices.

PAE at 28 dBm: 39.8%

PAE at 17 dBm: 22.3%

• 8-pin surface mounting package

The WS1403 meets stringent CDMA linearity

requirements to and beyond 28 dBm output power. The

3mmx3mm form factor 8-pin surface mount package

is self contained, incorporating 50 ohm input and output

matching networks.

3 mm x 3 mm x 1.0 mm

• Internal 50 ohm matching networks for both RF input

and output

• RoHS compliant

Applications

• Digital CDMA PCS

• Wireless Local loop

Order Information

Part Number

WS1403-TR1

WS1403-BLK

No. of Devices

1,000

Container

7”Tape and Reel

BULK

100

Functional Block Diagram

Vref (1)

Vcont (2)

MMIC

BIAS CIRCUIT & CONTROL LOGIC

INTER

RF

INPUT

(3)

RF

OUTPUT

(6)

INPUT

MATCH

OUTPUT

MATCH

DA

STAGE

PA

MATCH

MODULE

Vcc1 (4)

Vcc2 (5)

[1]

Table 1. Absolute Maximum Ratings

Parameter

Symbol

Min.

–

Nominal

–

Max.

10.0

5.0

Unit

dBm

V

RF Input Power

DC Supply Voltage

Reference Voltage

Control Voltage

Storage Temperature

Vcc

0

3.4

Vref

0

2.85

–

3.3

V

Vcont

Tstg

0

3.3

V

-55

+125

°C

Table 2. Recommended Operating Condition

Parameter

Symbol

Vcc

Min.

3.2

Nominal

3.4

Max.

4.2

Unit

V

DC Supply Voltage

DC Reference Voltage

Vref

2.75

2.85

2.95

V

Mode Control Voltage

– High Power Mode

– Low Power Mode

Vcont

0

2.0

0

2.85

0.5

3.0

V

Operating Frequency

Ambient Temperature

Fo

Ta

1850

-30

1910

85

MHz

°C

25

Table 3. Power Range Truth Table

[2]

Power Mode

Symbol

Vref

2.85

0

Vcont

Low

High

-

Range

High Power Mode

Low Power Mode

Shut Down Mode

PR2

PR1

–

~ 28 dBm

~ 17 dBm

–

Notes:

1. No damage assuming only one parameter is set at limit at a time with all other parameters set at or below nominal value.

2. High (2.0 – 3.0 V), Low (0.0 V – 0.5 V).

2

Table 4. Electrical Characteristics for CDMA Mode (Vcc = 3.4 V, Vref = 2.85 V, T = 25°C, Zin/Zout = 50 ohm)

Characteristics

Symbol

F

Condition

Min.

1850

24

Typ.

–

Max.

Unit

Operating Frequency Range

1910 MHz

Gain_hi

Gain_low

PAE_hi

PAE_ low

Icc_hi

High Power Mode, Pout = 28 dBm

Low Power Mode, Pout = 17 dBm

High Power Mode, Pout = 28 dBm

Low Power Mode, Pout = 17 dBm

High Power Mode, Pout = 28 dBm

Low Power Mode, Pout = 17 dBm

High Power Mode

28

dB

%

Gain

14

18

35.6

16.1

39.8

22.3

465

65

Power Added Eﬃciency

Total Supply Current

Quiescent Current

%

520

90

125

22

7

mA

µA

Icc_ low

Iq_hi

91

Iq_ low

Iref_hi

Iref_low

Icont

Low Power Mode

12

High Power Mode, Pout = 28 dBm

Low Power Mode, Pout = 17 dBm

Vref = 0 V

2

Reference Current

Control Current

3.3

0.19

0.2

8

1

Total Current in Power-Down

Mode

Ipd

5

Adjacent

Channel

Power

1.25 MHz oﬀset ACPR1_hi

1.98 MHz oﬀset ACPR2_hi

High Power Mode, Pout = 28 dBm

-52

-59

-54

-65

-40

-64

1.4:1

-47

dBc

-56

1.25 MHz oﬀset ACPR1_ low Low Power Mode, Pout = 17 dBm

1.98 MHz oﬀset ACPR2_ low

-47

Ratio

-56

Harmonic

Suppression

Second

Third

2f0

High Power Mode, Pout = 28 dBm

-33

3f0

-45

Input VSWR

VSWR

S

2.0:1

-60

Stability (Spurious Output)

Noise Power in Rx Band

Ruggedness

VSWR 6:1, All Phase

dBc

RxBN

-137

-133

10:1

dBm/Hz

VSWR

No Damage

Pout <28 dBm, Pin <10 dBm, All Phase

High Power Mode

3

Characteristics Data (Vcc = 3.4 V, Vref = 2.85 V, T = 25°C, Zin/Zout = 50 ohm)

500

450

400

350

300

250

200

150

100

50

35

30

25

20

15

10

1850 MHz

1880 MHz

1910 MHz

1850 MHz

1880 MHz

1910 MHz

0

5

10

15

20

25

30

0

5

10

15

20

25

30

Pout (dBm)

Figure 1. Total current vs. output power

Figure 2. Gain vs. output power

45

40

35

30

25

20

15

10

5

-40

-45

-50

-55

-60

-65

-70

-75

1850 MHz

1880 MHz

1910 MHz

1850 MHz

1880 MHz

1910 MHz

0

5

10

15

20

25

30

0

5

10

15

20

25

30

Pout (dBm)

Figure 3. Power added eﬃciency vs. output power

Figure 4. Adjacent channel power ratio 1 vs. output power

-50

-55

-60

-65

-70

-75

-80

-85

1850 MHz

1880 MHz

1910 MHz

0

5

10

15

20

25

30

Pout (dBm)

Figure 5. Adjacent channel power ratio 2 vs. output power

4

Evaluation Board Description

Vref

1 Vref

GND 8

GND 7

C3

100pF

R1

0 ohm

Vcont

RF In

2 Vcont

3 RF In

C4

100pF

RF Out

Vcc2

RF Out 6

Vcc2 5

Vcc1

4 Vcc1

C2

150pF

C6

2.2µF

C5

2.2µF

C1

100pF

Figure 6. Evaluation board schematic

3

4

1403

PYYWW

AAAAA

Figure 7. Evaluation board assembly diagram

5

Package Dimensions and Pin Descriptions

0.60

PIN 1 MARK

1

2

3

4

8

7

6

5

3

0.1

3

0.1

1.0 0.1

TOP VIEW

SIDE VIEW

0.7

1.40

PIN DESCRIPTIONS

0.15 x 45

PIN #

NAME

Vref

DESCRIPTION

Reference Voltage

Control Voltage

RF Input

1

2

3

4

5

6

7

8

Vcont

RF In

Vcc1

1.20

1.40

2.80

Supply Voltage

RF Output

Vcc2

RF Out

GND

3.0

Ground

0.40

GND

Ground

0.80

0.40

R 0.10

0.40

X-RAY BOTTOM VIEW

Figure 8. Package dimensional drawing and pin descriptions (all dimensions are in millimeters)

PIN 1 MARK

Manufacturing Part Number

Lot Number

1403

PYYWW

AAAAA

P

Manufacturing Info

YY

WW

AAAAA

Manufacturing Year

Work Week

Assembly Lot

Figure 9. Marking speciﬁcations

6

Peripheral Circuit in Handset

+2.85 V

C8

MSM

PA_ON

PA_RO

C1

C2

WS1403

Output Matching Circuit

C6

Vref

GND

RF OUT

Vcc2

Vcont

RF In

RF Out

TX

FILTER

RF IN

Vcc1

Duplexer

C7

L1

C3

C4

C5

V_BATT

Figure 10. Peripheral circuit

Notes:

•

Recommended voltage for Vref is 2.85 V.

Place C1 near to Vref pin.

Place C3 and C4 close to pin 4 (Vcc1) and pin 5 (Vcc2). These capacitors can aﬀect the RF performance.

Use 50 W transmission line between PAM and Duplexer and make it as short as possible to reduce conduction loss.

π-type circuit topology is good to use for matching circuit between PA and Duplexer.

Calibration

Oﬀset Value (Diﬀerence between Rising Point and Falling

Point)

Calibration procedure is shown in Figure 11. Two

calibration tables, high mode and low mode respectively,

are required for Cool PAM, which is due to gain diﬀerence

in each mode. For continuous output power at the mode

change points, the input power should be adjusted

according to gain step during the mode change.

Oﬀset value, which is the diﬀerence between the rising

point (output power where PA mode changes from low

mode to high mode) and falling point (output power

where PA mode changes from high mode to low mode),

should be adopted to prevent system oscillation. 3 to 5

dB is recommended for hysteresis.

TX_AGC

GAIN

Low Mode

High Mode

Max. PWR

High Mode

Low Mode

Pout

Falling Rising

Pout

Min. PWR

Falling

Rising

Figure 11. Calibration procedure

Figure 12. Setting of oﬀset between rising and falling power

7

5.00

4.50

4.00

3.50

3.00

2.50

2.00

1.50

1.00

0.50

0

700

600

500

CDG Urban

CDG Suburban

400

300

200

100

0

-50

-40

-30

-20

-10

0

10

20

30

PA Out (dBm)

Conventional PAM

Digitally Controlled PAM

Cool PAM

Figure 13. CDMA power distribution function

Average Current & Talk Time

Stencil Design Guidelines

Probability Distribution Function implies that what is

A properly designed solder screen or stencil is required

important for longer talk time is the eﬃciency of low to ensure optimum amount of solder paste is deposited

or medium power range rather than the eﬃciency at

full power. WS1403 idle current is 12 mA and operating

current at 17 dBm is 65 mA at nominal condition. This PA

with low current consumption prolongs talk time by no

less than 30 minutes compared to other PAs.

onto the PCB pads.

The recommended stencil layout is shown in Figure 16.

Reducing the stencil opening can potentially generate

more voids. On the other hand, stencil openings larger

than 100% will lead to excessive solder paste smear or

bridging across the I/O pads or conductive paddle to

adjacent I/O pads. Considering the fact that solder paste

thickness will directly aﬀect the quality of the solder

joint, a good choice is to use laser cut stencil composed

of 0.100 mm (4 mils) or 0.127 mm (5 mils) thick stainless

steel which is capable of producing the required ﬁne

stencil outline.

Average current = ∫(PDF x Current)dp

PCB Design Guidelines

The recommended WS1403 PCB land pattern is shown

in Figure 14 and Figure 15. The substrate is coated with

solder mask between the I/O and conductive paddle to

protect the gold pads from short circuit that is caused by

solder bleeding/bridging.

∅ 0.3 mm ON

0.5 mm PITCH

0.6

0.5

0.55

0.7

0.6

0.4

0.5

0.8

0.4

0.8

1.325

1.05

0.1

0.8

0.5

1.4

1.1

0.25

Figure 14. Metallization

Figure 15. Solder mask opening

Figure 16. Solder paste stencil aperture

8

Tape and Reel Information

P10 (3)

P2 (1)

P0

D0

T

Y

F

A

F (1)

W

B0

Y

SECTION Y - Y

P1 (2)

D1

X

A0

R 0.5

0.1

K0

SECTION X - X

R 1.0

DETAIL A

DIMENSIONS

NOTATION

MILLIMETERS

3.40 0.10

1.35 0.10

1.55 0.05

1.60 0.10

4.00 0.10

8.00 0.10

2.00 0.05

40.00 0.20

1.75 0.10

5.50 0.05

12.00 0.30

0.30 0.05

A0

B0

K0

D0

D1

P0

P1

P2

P10

E

F

W

T

Figure 17. Tape and reel format – 3 mm x 3 mm

9

Reel Drawing

BACK VIEW

FRONT VIEW

Figure 18. Plastic reel format (all dimensions are in millimeters)

10

Avago Technologies follows JEDEC Standard J-STD 020B.

Each component and package type is classiﬁed for

moisture sensitivity by soaking a known dry package at

various temperatures and relative humidity, and times.

After soak, the components are subjected to three

consecutive simulated reﬂows.

Handling and Storage

ESD (Electrostatic Discharge)

Electrostatic discharge occurs naturally in the

environment. With the increase in voltage potential, the

outlet of neutralization or discharge will be sought. If the

acquired discharge route is through a semiconductor

device, destructive damage will result.

The out of bag exposure time maximum limits are

determined by the classiﬁcation test describe below

which corresponds to a MSL classiﬁcation level 6 to 1

according to the JEDEC standard IPC/JEDEC J-STD-020B

and J-STD-033.

ESD countermeasure methods should be developed and

used to control potential ESD damage during handling

in a factory environment at each manufacturing site.

WS1403 is MSL3. Thus, according to the J-STD-033 p.11

the maximum Manufacturers Exposure Time (MET) for

this part is 168 hours. After this time period, the part

would need to be removed from the reel, de-taped and

then re-baked. MSL classiﬁcation reﬂow temperature

for the WS1403 is targeted at 260°C +0/-5°C. Figure

19 and Table 7 show typical SMT proﬁle for maximum

temperature of 260 +0/-5°C.

MSL (Moisture Sensitivity Level)

Plastic encapsulated surface mount package is

sensitive to damage induced by absorbed moisture and

temperature.

Table 5. ESD Classiﬁcation

Pin #

Name

Vref

Description

HBM

CDM

Classiﬁcation

Class 2

1

2

3

4

5

6

7

8

Reference Voltage

Control Voltage

RF Input

2000 V

200 V

Vcont

RF In

Vcc1

Vcc2

RF Out

GND

2000 V

200 V

Supply Voltage

RF Output

Ground

Note:

1. Module products should be considered extremely ESD sensitive.

Table 6. Moisture Classiﬁcation Level and Floor Life

MSL Level

Floor Life (Out of Bag) at Factory Ambient = < 30°C/60% RH or As Stated

1

Unlimited at = < 30°C/85% RH

2

1 year

2a

3

4 weeks

168 hours

72 hours

48 hours

24 hours

4

5

5a

6

Mandatory bake before use. After bake, must be reﬂowed within the time limit speciﬁed on the label.

Note:

1. The MSL Level is marked on the MSL Label on each shipping bag.

11

tp

T

P

CRITICAL ZONE

T TO T

RAMP UP

L

P

T

L

t

L

Ts

max

min

ts

PREHEAT

RAMP DOWN

25

t 25°C TO PEAK

TIME

Figure 19. Typical SMT reﬂow proﬁle for maximum temperature = 260 +0/-5°C

Table 7. Typical SMT Reﬂow Proﬁle for Maximum Temperature = 260 +0/-5°C

Proﬁle Feature

Sn-Pb Solder

Pb-Free Solder

Average Ramp-Up Rate (TL to TP)

3°C/sec max

3°C /sec max

Preheat

- Temperature Min (Tsmin)

- Temperature Max (Tsmax)

- Time (Min to Max) (ts)

100°C

150°C

60-120 sec

150°C

200°C

60-180 sec

Tsmax to TL

- Ramp-Up Rate

3°C /sec max

Time Maintained Above:

- Temperature (TL)

- Time (TL)

183°C

60-150 sec

217°C

60-150 sec

Peak Temperature (Tp)

240 +0/-5°C

10-30 sec

260 +0/-5°C

20-40 sec

Time Within 5°C of Actual Peak Temperature (tp)

Ramp-Down Rate

6°C/sec max

6 min max.

6°C/sec max

8 min max.

Time 25°C to Peak Temperature

12

Storage Condition

Baking of Populated Boards

Packages described in this document must be stored Some SMD packages and board materials are not able

in sealed moisture barrier, antistatic bags. Shelf life in a to withstand long duration bakes at 125°C. Examples of

sealed moisture barrier bag is 12 months at <40°C and this are some FR-4 materials, which cannot withstand a

90% relative humidity (RH) J-STD-033 p.7.

24 hr bake at 125°C. Batteries and electrolytic capacitors

are also temperature sensitive. With component and

board temperature restrictions in mind, choose a

bake temperature from Table 4-1 in J-STD 033; then

determine the appropriate bake duration based on the

component to be removed. For additional considerations

see IPC-7711 and IPC-7721.

Out-of-Bag Time Duration

After unpacking, the device must be soldered to the PCB

within 168 hours as listed in the J-STD-020B p.11 with

factory conditions <30°C and 60% RH.

Baking

Derating Due to Factory Environmental Conditions

It is not necessary to re-bake the part if both conditions

(storage conditions and out-of bag conditions) have

been satisﬁed. Baking must be done if at least one of

the conditions above have not been satisﬁed. The baking

conditions are 125°C for 12 hours J-STD-033 p.8.

Factory ﬂoor life exposures for SMD packages removed

from the dry bags will be a function of the ambient

environmental conditions. A safe, yet conservative,

handling approach is to expose the SMD packages only

up to the maximum time limits for each moisture

sensitivity level as shown in Table 7. This approach,

however, does not work if the factory humidity or

temperature is greater than the testing conditions of

30°C/60% RH. A solution for addressing this problem

is to derate the exposure times based on the knowledge

of moisture diﬀusion in the component package

materials ref. JESD22-A120). Recommended equivalent

total ﬂoor life exposures can be estimated for a range

of humidities and temperatures based on the nominal

plastic thickness for each device.

CAUTION

Tape and reel materials typically cannot be baked at the

temperature described above. If out-of-bag exposure

time is exceeded, parts must be baked for a longer time

at low temperatures, or the parts must be de-reeled, de-

taped, re-baked and then put back on tape and reel. (See

moisture sensitive warning label on each shipping bag

for information of baking).

Board Rework

Table 8 lists equivalent derated ﬂoor lives for humidities

ranging from 20-90% RH for three temperature, 20°C,

25°C, and 30°C.

Component Removal, Rework and Remount

If a component is to be removed from the board, it is

recommended that localized heating be used and the

maximum body temperatures of any surface mount

component on the board not exceed 200°C. This

method will minimize moisture related component

damage. If any component temperature exceeds 200°C,

the board must be baked dry per 4-2 prior to rework

and/or component removal. Component temperatures

shall be measured at the top center of the package body.

Any SMD packages that have not exceeded their ﬂoor

life can be exposed to a maximum body temperature as

high as their speciﬁed maximum reﬂow temperature.

This table is applicable to SMDs molded with novolac,

biphenyl or multifunctional epoxy mold compounds.

The following assumptions were used in calculating

Table 8:

1. Activation Energy for diﬀusion = 0.35eV (smallest

known value).

2. For ≤60% RH, use Diﬀusivity = 0.121exp ( -0.35eV/kT)

mm2/s

(this used smallest known Diﬀusivity @ 30°C).

3. For >60% RH, use Diﬀusivity = 1.320exp ( -0.35eV/kT)

mm2/s

Removal for Failure Analysis

(this used largest known Diﬀusivity @ 30°C).

Not following the above requirements may cause

moisture/reﬂow damage that could hinder or

completely prevent the determination of the original

failure mechanism.

13

Table 8. Recommended Equivalent Total Floor Life (days) @ 20°C, 25°C and 30°C for ICs with Novolac, Biphenyl and Multifunc-

tional Epoxies (Reﬂow at same temperature at which the component was classiﬁed)

Maximum Percent Relative Humidity

Package Type and Body

Thickness

Moisture Sensitivity Level

5%

∞

10% 20%

30%

60

78

103

9

40%

41

53

69

8

50%

33

42

57

7

60%

28

36

47

7

70%

10

14

19

5

80%

7

90%

6

∞

5

∞

10

13

17

4

30°C

25°C

Level 2a

10

13

4

8

10 20°C

4

5

7

2

3

4

1

2

3

1

2

3

4

2

3

4

1

2

3

1

2

30°C

25°C

20°C

30°C

25°C

20°C

30°C

25°C

20°C

30°C

25°C

20°C

30°C

25°C

20°C

30°C

25°C

20°C

30°C

25°C

20°C

30°C

25°C

20°C

Body Thickness

≥3.1 mm

Level 3

Level 4

Level 5

Level 5a

Level 2a

Level 3

Level 4

Level 5

Level 5a

11

14

4

10

13

4

9

7

6

12

3

12

3

10

3

8

including

2

PQFPs >84 pin,

PLCCs (square)

All MQFPs

6

5

4

3

8

7

6

5

4

3

2

1

or

5

4

3

2

All BGAs ≥1 mm

7

6

5

4

3

2

1

3

2

1

5

4

3

2

∞

7

∞

19

25

32

5

∞

12

15

19

4

86

148

∞

9

39

51

69

8

28

27

49

7

4

3

6

4

8

5

3

2

Body 2.1 mm

12

15

4

10

13

3

9

5

3

≤ Thickness

12

3

7

5

<3.1 mm including

PLCCs (rectangular)

18-32 pin

2

9

7

5

4

3

2

11

4

9

7

6

5

4

3

SOICs (wide body)

SOICs ≥20 pins,

PQFPs ≤80 pins

3

2

1

5

4

3

2

1

6

5

4

3

2

1

0.5

1

0.5 30°C

2

1

25°C

20°C

30°C

25°C

20°C

30°C

25°C

20°C

30°C

25°C

20°C

30°C

25°C

20°C

3

2

∞

10

13

18

∞

13

18

26

3

∞

9

∞

5

∞

11

14

20

4

28

∞

7

1

Level 2a

Level 3

2

1

2

1

Body Thickness

<2.1 mm

10

13

3

2

1

2

including

1

SOICs <18 pin

Level 4

Level 5

Level 5a

12

17

5

7

5

4

2

1

9

7

6

2

All TQFPs, TSOPs or

All BGAs <1 mm body

thickness

3

2

1

6

4

3

2

1

8

6

5

4

2

1

0.5 30°C

5

3

2

1

25°C

20°C

6

4

3

2

14

For product information and a complete list of distributors, please go to our website: www.avagotech.com

Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries.

AV02-0291EN - August 26, 2008

型号:	WS1403-TR1
是否Rohs认证：	符合
生命周期：	Obsolete
IHS 制造商：	BROADCOM LTD
包装说明：	SOLCC8,.12,32
Reach Compliance Code：	compliant
ECCN代码：	5A991.G
HTS代码：	8542.33.00.01
风险等级：	5.7
Base Number Matches：	1

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