X22C12PI各脚功能电路原理芯片引脚定义引脚图及功能IC贸易商-中国IC网-芯三七

X22C12

1K Bit

X22C12

256 x 4

Nonvolatile Static RAM

FEATURES

DESCRIPTION

• High Performance CMOS

The X22C12 is a 256 x 4 CMOS NOVRAM featuring a

high-speed static RAM overlaid bit-for-bit with a non-

volatile E²PROM. The NOVRAM design allows data to

be easily transferred from RAM to E²PROM (STORE)

and from E²PROM to RAM (RECALL). The STORE

operation is completed within 5ms or less and the

RECALL is completed within 1µs.

—150ns RAM Access Time

• High Reliability

—Store Cycles: 1,000,000

—Data Retention: 100 Years

• Low Power Consumption

—Active: 40mA Max.

—Standby: 100µA Max.

XicorNOVRAMsaredesignedforunlimitedwriteopera-

tions to the RAM, either RECALLs from E²PROM or

writes from the host. The X22C12 will reliably endure

1,000,000 STORE cycles. Inherent data retention is

greater than 100 years.

• Infinite Array Recall, RAM Read and Write Cycles

• Nonvolatile Store Inhibit: V_CC= 3.5V Typical

• Fully TTL and CMOS Compatible

• JEDEC Standard 18-Pin 300-mil DIP

• 100% Compatible with X2212

—With Timing Enhancements

FUNCTIONAL DIAGRAM

PIN CONFIGURATION

PLASTIC DIP

CERDIP

2

NONVOLATILE E PROM

MEMORY ARRAY

A

1

2

3

4

5

6

7

8

9

18

17

16

15

14

13

12

11

10

V

A

7

4

3

2

1

0

CC

6

STORE

A

0

A

ARRAY

RECALL

1

5

ROW

SELECT

STATIC RAM

MEMORY ARRAY

A

I/O

I/0

2

3

4

3

2

X22C12

CS

1

V

CC

V

WE

STORE

RECALL

CONTROL

LOGIC

SS

STORE

V

SS

RECALL

COLUMN

I/O CIRCUITS

3817 FHD F02

I/O

1

COLUMN SELECT

INPUT

DATA

I/O

2

SOIC

CONTROL

I/O

3

1

2

3

4

5

6

7

8

9

10

20

19

18

17

16

15

14

13

12

11

V

A7

A

4

A

3

A

2

A

1

A

0

CC

A

6

A

5

I/O

4

A

5

7

6

I/O

4

X22C12

NC

I/O

3

I/O

2

I/O

1

CS

V

SS

WE

STORE

WE

RECALL

3817 FHD F01

3815 FHD F10.1

3817-2.4 7/30/96 T0/C0/D1 SH

Characteristics subject to change without notice

1

X22C12

RECALL

PIN DESCRIPTIONS AND DEVICE OPERATION

Addresses (A₀–A₇)

The RECALL input, when LOW, will initiate the transfer

of the entire contents of the E²PROM array to the RAM

array. The transfer of data will be completed in 1µs or

less.

The address inputs select a 4-bit memory location

during a read or write operation.

Chip Select (CS)

An array recall has priority over RAM read/write opera-

tions and will terminate both operations when RECALL

is asserted. RECALL LOW will also inhibit the STORE

input.

The Chip Select input must be LOW to enable read or

write operations with the RAM array. CS HIGH will place

the I/O pins in the high impedance state.

Write Enable (WE)

Automatic Recall

The Write Enable input controls the I/O buffers, deter-

mining whether a RAM read or write operation is en-

abled. When CS is LOW and WE is HIGH, the I/O pins

will output data from the selected RAM address loca-

tions. When both CS and WE are LOW, data presented

at the I/O pins will be written to the selected address

location.

Upon power-up the X22C12 will automatically recall

data from the E²PROM array into the RAM array.

Write Protection

The X22C12 has three write protect features that are

employed to protect the contents of the nonvolatile

memory.

Data In/Data Out (I/O₁–I/O₄)

• V_CCSense—All functions are inhibited when V_CCis

<3.5V typical.

Data is written to or read from the X22C12 through the

I/O pins. The I/O pins are placed in the high impedance

state when either CS is HIGH or during either a store or

recall operation.

• Write Inhibit—Holding either STORE HIGH or

RECALL LOW during power-up or power-down will

prevent an inadvertent store operation and E²PROM

data integrity will be maintained.

STORE

• Noise Protection—A STORE pulse of typically less

than 20ns will not initiate a store cycle.

TheSTORE input, whenLOW, willinitiatethetransferof

the entire contents of the RAM array to the E²PROM

array. The WE and RECALL inputs are inhibited during

the store cycle. The store operation is completed in 5ms

or less.

PIN NAMES

Symbol

A –A

Description

Address Inputs

Data Inputs/Outputs

Write Enable

Chip Select

Recall

0

7

A store operation has priority over RAM read/write

operations. If STORE is asserted during a read opera-

tion, the read will be discontinued. If STORE is asserted

during a RAM write operation, the write will be immedi-

ately terminated and the store performed. The data at

theRAMaddressthatwasbeingwrittenwillbeunknown

in both the RAM and E²PROM arrays.

I/O –I/O

1

4

WE

CS

RECALL

STORE

Store

V

CC

V

SS

+5V

Ground

NC

No Connect

3817 PGM T01

2

X22C12

ABSOLUTE MAXIMUM RATINGS

COMMENT

Temperature under Bias .................. –65°C to +135°C

Storage Temperature ....................... –65°C to +150°C

Voltage on any Pin with

Stresses above those listed under “Absolute Maximum

Ratings” may cause permanent damage to the device.

This is a stress rating only and the functional operation of

the device at these or any other conditions above those

indicatedintheoperationalsectionsofthisspecificationis

not implied. Exposure to absolute maximum rating condi-

tions for extended periods may affect device reliability.

Respect to V

....................................... –1V to +7V

SS

D.C. Output Current ............................................ 5mA

Lead Temperature

(Soldering, 10 seconds).............................. 300°C

RECOMMENDED OPERATING CONDITIONS

Supply Voltage

Limits

Temperature

Min.

Max.

X22C12

5V ±10%

Commercial

Industrial

Military

0°C

+70°C

+85°C

+125°C

3817 PGM T13

–40°C

–55°C

3817 PGM T12.1

D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions, unless otherwise specified.)

Limits

Symbol

Parameter

Min.

Max.

Units

Test Conditions

CS = V , I/Os = Open, All Others =

l

V

CC

Supply Current,

40

mA

CC

IL

RAM Read/Write

V , Addresses = 0.4V/2.4V Levels @

IH

f = 8MHz

I

V

Standby Current

2

mA

Store or Recall Functions Not Active,

SB1

SB2

CC

(TTL Inputs)

I/Os = Open, All Other Inputs = V

IH

V

CC

Standby Current

100

µA

Store or Recall functions Not Active,

I/Os = Open, All Other Inputs =

(CMOS Inputs)

V

–0.3V

CC

I

Input Leakage Current

Output Leakage Current

Input LOW Voltage

10

µA

V

= V to V

SS CC

LI

IN

= V to V

CC

LO

OUT

SS

(2)

V

–1

2

0.8

lL

(2)

Input HIGH Voltage

Output LOW Voltage

Output HIGH Voltage

V

+ 1

CC

V

IH

0.4

V

I = 4.2mA

OL

OH

2.4

V

I

= –2mA

OH

3817 PGM T02.3

CAPACITANCE T_A= +25°C, f = 1MHz, V_CC= 5V

Symbol

Parameter

Max.

Units

Test Conditions

(1)

C

Input/Output Capacitance

Input Capacitance

8

6

pF

V

= 0V

I/O

(1)

= 0V

IN

3815 PGM T03.1

Notes: (1) This parameter is periodically sampled and not 100% tested.

(2) V min. and V max. are for reference only and are not tested.

IL IH

3

X22C12

MODE SELECTION

CE

WE

RECALL

STORE

I/O

Mode

(3)

H

L

X

H

L

H

L

H

L

Output High Z

Output Data

Not Selected

Read RAM

L

Input Data High

Input Data Low

Output High Z

Write “1” RAM

Write “0” RAM

Array Recall

L

X

H

X

H

X

H

X

L

Array Recall

(4)

H

Nonvolatile Store

L

Nonvolatile Store

3817 PGM T05.1

ENDURANCE AND DATA RETENTION

Parameter

Min.

Units

Endurance

100,000

1,000,000

100

Data Changes Per Bit

Store Cycles

Years

Store Cycles

Data Retention

3817 PGM T06

POWER-UP TIMING

Symbol

Parameter

Max.

Units

(5)

t

Power-up to Read Operation

100

5

µs

PUR

(5)

t

Power-up to Write or Store Operation

ms

PUW

3817 PGM T07

EQUIVALENT A.C. LOAD CIRCUIT

A.C. CONDITIONS OF TEST

Input Pulse Levels

0V to 3V

10ns

5V

Input Rise and

Fall Times

919Ω

Input and Output

Timing Levels

1.5V

OUTPUT

3817 PGM T04.1

497Ω

100pF

3815 FHD F09.1

Notes: (3) Chip is deselected but may be automatically completing a store cycle.

(4) STORE = LOW is required only to initiate the store cycle, after which the store cycle will be automatically completed

(e.g. STORE = X).

(5) t

and t

are the delays required from the time V

is stable until the specified operation can be initiated. These

PUR

PUW

parameters are periodically sampled and not 100% tested.

CC

4

X22C12

A.C. CHARACTERISTICS (Over the recommended operating conditions, unless otherwise specified.)

Read Cycle Limits

Symbol

Parameter

Read Cycle Time

Min.

Max.

Units

t

150

ns

RC

AA

CO

OH

Access Time

150

Chip Select to Output Valid

Output Hold from Address Change

Chip Select to Output in Low Z

Chip Deselect to Output in High Z

0

(6)

LZ

(6)

50

HZ

3817 PGM T08

Read Cycle

t

RC

ADDRESS

t

A

t

HZ

OH

t

CO

CS

t

LZ

DATA I/O

DATA VALID

3817 FHD F03

Note: (6) t min. and t min. are periodically sampled and not 100% tested.

LZ HZ

5

X22C12

Write Cycle Limits

Symbol

Parameter

Write Cycle Time

Min.

Max.

Units

t

150

90

0

ns

WC

CW

AS

Chip Select to End of Write

Address Setup Time

Write Pulse Width

90

0

WP

WR

DW

DH

Write Recovery Time

Data Valid to End of Write

Data Hold Time

40

0

Write Enable to Output in High Z

Output Active from End of Write

50

WZ

OW

0

ns

3817 PGM T09.1

Write Cycle

t

WC

ADDRESS

t

CW

CS

WE

t

AS

WP

WR

t

DW

DH

DATA IN

DATA VALID

t

WZ

OW

DATA OUT

3817 FHD F04

Early Write Cycle

t

WC

t

ADDRESS

CS

t

CW

WR

t

AS

t

WP

WE

t

DW

DH

DATA VALID

DATA IN

HIGH Z

DATA OUT

3817 FHD F05

6

X22C12

Recall Cycle Limits

Symbol

Parameter

Min.

Max.

Units

t

Array Recall Time

Recall Pulse Width

1

µs

ns

RCC

RCP

RCZ

(7)

90

0

Recall to Output in High Z

50

Output Active from End of Recall

Recalled Data Access Time from End of Recall

ORC

ARC

120

ns

3817 PGM T10

Recall Cycle

ADDRESS

t

RCC

t

RCP

RECALL

CS

t

RCZ

ORC

DATA I/O

t

ARC

3817 FHD F06

Note: (7) RECALL rise time must be less than 1µs.

7

X22C12

Store Cycle Limits

Symbol

Parameter

Internal Store Time

Min.

Max.

Units

t

5

ms

ns

STC

STP

STZ

OST

Store Pulse Width

90

0

Store to Output in High Z

Output Active from End of Store

50

ns

3817 PGM T11

Store Cycle Limits

t

STC

t

STP

STORE

t

STZ

OST

HI Z

DATA I/O

3817 FHD F07

SYMBOL TABLE

WAVEFORM

INPUTS

OUTPUTS

Must be

steady

Will be

steady

May change

from LOW

to HIGH

Will change

from LOW

to HIGH

May change

from HIGH

to LOW

Will change

from HIGH

to LOW

Don’t Care:

Changes

Allowed

Changing:

State Not

Known

N/A

Center Line

is High

Impedance

8

X22C12

18-LEAD PLASTIC DUAL IN-LINE PACKAGE TYPE P

0.915 (23.24)

0.894 (22.71)

0.270 (6.86)

0.250 (6.35)

PIN 1 INDEX

PIN 1

0.060 (1.52)

0.050 (1.27)

0.800 (20.32)

REF.

0.165 (4.19)

0.130 (3.30)

SEATING

PLANE

0.025 (0.51)

0.005 (0.13)

0.140 (3.56)

0.120 (3.05)

0.110 (2.79)

0.090 (2.29)

0.070 (1.78)

0.050 (1.27)

0.020 (0.51)

0.016 (0.41)

0.325 (8.26)

0.300 (7.62)

0°

15°

TYP. 0.010 (0.25)

NOTE:

1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)

2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH

3926 FHD F02

9

X22C12

18-LEAD HERMETIC DUAL IN-LINE PACKAGE TYPE D

0.960 (24.38)

––

0.310 (7.87)

0.220 (5.59)

PIN 1

0.005 (0.13) MIN.

0.800 (20.32)

REF.

0.098 (2.49)

––

SEATING

PLANE

0.200 (5.08)

––

0.070 (1.78)

0.015 (0.38)

0.200 (5.08)

0.150 (3.81) MIN.

0.125 (3.18)

0.110 (2.79)

0.090 (2.29)

0.065 (1.65)

0.023 (0.58)

0.014 (0.36)

0.038 (0.97)

TYP. 0.100 (2.54)

TYP. 0.060 (1.52)

TYP. 0.018 (0.46)

0.320 (8.13)

0.290 (7.37)

TYP. 0.311 (7.90)

0°

0.015 (0.38)

0.008 (0.20)

15°

NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)

3926 FHD F06

10

X22C12

20-LEAD PLASTIC SMALL OUTLINE GULL WING PACKAGE TYPE S

0.290 (7.37)

0.299 (7.60)

0.393 (10.00)

0.420 (10.65)

PIN 1 INDEX

PIN 1

0.014 (0.35)

0.020 (0.50)

0.496 (12.60)

0.508 (12.90)

(4X) 7°

0.092 (2.35)

0.105 (2.65)

0.003 (0.10)

0.012 (0.30)

0.050 (1.27)

0.050" Typical

0.010 (0.25)

0.020 (0.50)

X 45°

0.050"

Typical

0° – 8°

0.420"

0.007 (0.18)

0.011 (0.28)

0.015 (0.40)

0.050 (1.27)

0.030" Typical

20 Places

FOOTPRINT

NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)

3926 FHD F23

11

X22C12

ORDERING INFORMATION

X22C12

X

Store Cycles

Device

Blank = 1,000,000

Temperature Range

Blank = Commercial = 0°C to +70°C

I = Industrial = –40°C to +85°C

M = Military = –55°C to +125°C

MB = MIL-STD-883

Package

P = 18-Lead Plastic DIP

D = 18-Lead Cerdip

S = 20-Lead Plastic SOIC (300 mil)

LIMITED WARRANTY

Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty,

express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement.

Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and

prices at any time and without notice.

Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, licenses are

implied.

U.S. PATENTS

Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,404,475;

4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829, 482; 4,874, 967; 4,883, 976. Foreign patents and

additional patents pending.

LIFE RELATED POLICY

In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error

detection and correction, redundancy and back-up features to prevent such an occurence.

Xicor’s products are not authorized for use in critical components in life support devices or systems.

1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose

failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant

injury to the user.

2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life

support device or system, or to affect its safety or effectiveness.

12

型号:	X22C12PI
是否Rohs认证：	不符合
生命周期：	Obsolete
包装说明：	0.300 INCH, PLASTIC, DIP-18
Reach Compliance Code：	unknown
风险等级：	5.83
Is Samacsys：	N
最长访问时间：	150 ns
其他特性：	EEPROM SOFTWARE STORE/RECALL; RETENTION/ENDURANCE - 100 YEARS/100000 CYCLES
JESD-30 代码：	R-PDIP-T18
JESD-609代码：	e0
长度：	22.975 mm
内存密度：	1024 bit
内存集成电路类型：	NON-VOLATILE SRAM
内存宽度：	4
功能数量：	1
端口数量：	1
端子数量：	18
字数：	256 words
字数代码：	256
工作模式：	ASYNCHRONOUS
最高工作温度：	85 °C
最低工作温度：	-40 °C
组织：	256X4
输出特性：	3-STATE
可输出：	NO
封装主体材料：	PLASTIC/EPOXY
封装代码：	DIP
封装等效代码：	DIP18,.3
封装形状：	RECTANGULAR
封装形式：	IN-LINE
并行/串行：	PARALLEL
峰值回流温度（摄氏度）：	NOT SPECIFIED
认证状态：	Not Qualified
座面最大高度：	4.7 mm
子类别：	SRAMs
最大供电电压 (Vsup)：	5.5 V
最小供电电压 (Vsup)：	4.5 V
标称供电电压 (Vsup)：	5 V
表面贴装：	NO
技术：	CMOS
温度等级：	INDUSTRIAL
端子面层：	Tin/Lead (Sn/Pb)
端子形式：	THROUGH-HOLE
端子节距：	2.54 mm
端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	7.62 mm
Base Number Matches：	1

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