X5649P芯片引脚定义引脚图及功能IC贸易商引脚图技术参数-中国IC网-芯三七

X5648, X5649

®

(Replaces X25648, X25649)

Data Sheet

March 17, 2005

FN8136.0

DESCRIPTION

CPU Supervisor with 64Kbit SPI EEPROM

These devices combine three popular functions, Power-

on Reset Control, Supply Voltage Supervision, and Block

Lock Protect Serial EEPROM Memory in one package.

This combination lowers system cost, reduces board

space requirements, and increases reliability.

FEATURES

• Low V detection and reset assertion

CC

—Five standard reset threshold voltages

—Re-program low V reset threshold voltage

CC

using special programming sequence

Applying power to the device activates the power-on

reset circuit which holds RESET/RESET active for a

period of time. This allows the power supply and oscilla-

tor to stabilize before the processor can execute code.

—Reset signal valid to V = 1V

CC

• Long battery life with low power consumption

—<50µA max standby current, watchdog on

—<1µA max standby current, watchdog off

—<400µA max active current during read

• 64Kbits of EEPROM

The device’s low V

detection circuitry protects the

CC

user’s system from low voltage conditions by holding

RESET/RESET active when V falls below a minimum

• Built-in inadvertent write protection

—Power-up/power-down protection circuitry

—Protect 0, 1/4, 1/2 or all of EEPROM array with

CC

V

trip point. RESET/RESET remains asserted until

returns to proper operating level and stabilizes. Five

CC

™

Block Lock protection

industry standard V

thresholds are available,

TRIP

—In circuit programmable ROM mode

• 2MHz SPI interface modes (0,0 & 1,1)

• Minimize EEPROM programming time

—32-byte page write mode

however, Intersil’s unique circuits allow the threshold to

be reprogrammed to meet custom requirements or to

fine-tune the threshold in applications requiring higher

precision.

—Self-timed write cycle

—5ms write cycle time (typical)

• 2.7V to 5.5V and 4.5V to 5.5V power supply

operation

• Available packages

—14-lead SOIC, 8-lead PDIP

BLOCK DIAGRAM

WP

Protect Logic

SI

Data

Register

Status

Register

SO

Command

Decode &

Control

SCK

CS

16Kbits

Logic

32Kbits

Reset

Timebase

RESET/RESET

Power-on and

Low Voltage

Reset

V

+

-

CC

X5648 = RESET

X5649 = RESET

Generation

V

TRIP

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-352-6832 | Intersil (and design) is a registered trademark of Intersil Americas Inc.

1

All other trademarks mentioned are the property of their respective owners.

X5648, X5649

PIN CONFIGURATION

14-Lead SOIC

8-Lead PDIP

X5648/49

1

NC

14

13

12

CS

2

3

4

5

V_CC

V

1

8

CS

SO

WP

CC

V_CC

2

3

7

6

RESET/RESET

X5648/49

SO

WP

V_SS

RESET/RESET

11

10

9

SCK

SI

SCK

SI

V

SS

4

5

6

7

NC

8

NC

PIN DESCRIPTION

(PDIP)

(SOIC)

Name

Function

1

2, 3

CS

Chip Select Input. CS HIGH, deselects the device and the SO output pin is at

a high impedance state. Unless a nonvolatile write cycle is underway, the device

will be in the standby power mode. CS LOW enables the device, placing it in the

active power mode. Prior to the start of any operation after power-up, a HIGH to

LOW transition on CS is required.

2

5

4

9

SO

SI

Serial Output. SO is a push/pull serial data output pin. A read cycle shifts data out

on this pin. The falling edge of the serial clock (SCK) clocks the data out.

Serial Input. SI is a serial data input pin. Input all opcodes, byte addresses, and

memory data on this pin. The rising edge of the serial clock (SCK) latches the input

data. Send all opcodes (Table 1), addresses and data MSB first.

6

3

10

5

SCK

WP

Serial Clock. The serial clock controls the serial bus timing for data input and out-

put. The rising edge of SCK latches in the opcode, address, or data bits present on

the SI pin. The falling edge of SCK changes the data output on the SO pin.

Write Protect. The WP pin works in conjunction with a nonvolatile WPEN bit to

“lock” the setting of the watchdog timer control and the memory write protect bits.

4

8

7

6

V_SS

V_CC

Ground

12, 13

11

Supply Voltage

RESET/ Reset Output. RESET/RESET is an active LOW/HIGH, open drain output which

RESET

goes active whenever V_CCfalls below the minimum V_CCsense level. It will re-

main active until V_CCrises above the minimum V_CCsense level for 200ms. RE-

SET/RESET goes active if the watchdog timer is enabled and CS remains either

HIGH or LOW longer than the selectable watchdog time out period. A falling

edge of CS will reset the watchdog timer. RESET/RESET goes active on power-

up at about 1V and remains active for 200ms after the power supply stabilizes.

1, 7, 8, 14

NC

No internal connections

FN8136.0

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March 17, 2005

X5648, X5649

PRINCIPLES OF OPERATION

Power-on Reset

Figure 1. Set V

Voltage

TRIP

CS

Application of power to the X5648/X5649 activates a

power-on reset circuit. This circuit goes active at about

1V and pulls the RESET/RESET pin active. This signal

prevents the system microprocessor from starting to

operate with insufficient voltage or prior to stabilization

V_P

SCK

V_P

of the oscillator. When V

exceeds the device V

CC

TRIP

SI

value for 200ms (nominal) the circuit releases

RESET/RESET, allowing the processor to begin exe-

cuting code.

Resetting the V

Voltage

TRIP

This procedure sets the V

level. For example, if the current V

to a “native” voltage

TRIP

Low Voltage Monitoring

is 4.4V and the

TRIP

During operation, the X5648/X5649 monitors the V

CC

V

is reset, the new V

is something less than

TRIP

level and asserts RESET/RESET if supply voltage

falls below preset minimum The

1.7V. This procedure must be used to set the voltage

to a lower value.

a

V

.

TRIP

RESET/RESET signal prevents the microprocessor

from operating in a power fail or brownout condition.

The RESET/RESET signal remains active until the

voltage drops below 1V. It also remains active until

To reset the V

voltage, apply a voltage between 2.7

TRIP

and 5.5V to the V

pin. Tie the CS pin, the WP pin,

CC

and the SCK pin HIGH. RESET/RESET and SO pins

are left unconnected. Then apply the programming volt-

V

returns and exceeds V

for 200ms.

CC

TRIP

age V to the SI pin ONLY and pulse CS LOW then

P

HIGH. Remove V and the sequence is complete.

V

Threshold Reset Procedure

P

CC

The X5648/X5649 has a standard V

threshold

CC

Figure 2. Reset V

Voltage

TRIP

(V

) voltage. This value will not change over normal

TRIP

operating and storage conditions. However, in applica-

tions where the standard V is not exactly right, or

TRIP

CS

for higher precision in the

V

value, the

TRIP

X5648/X5649 threshold may be adjusted.

V_CC

SCK

Setting the V

Voltage

TRIP

V_P

This procedure sets the V

value. For example, if the current V

to a higher voltage

TRIP

SI

is 4.4V and

TRIP

the new V

is 4.6V, this procedure directly makes

TRIP

the change. If the new setting is lower than the current

setting, then it is necessary to reset the trip point

before setting the new value.

To set the new V

voltage, apply the desired V

TRIP

threshold to the Vcc pin and tie the CS pin and the WP

pin HIGH. RESET/RESET and SO pins are left uncon-

nected. Then apply the programming voltage V to

P

both SCK and SI and pulse CS LOW then HIGH.

Remove V and the sequence is complete.

P

FN8136.0

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March 17, 2005

X5648, X5649

Figure 3. V

Programming Sequence Flow Chart

TRIP

V_TRIPProgramming

Execute

Reset V_TRIP

Sequence

Set V_CC= V_CCApplied =

Desired V_TRIP

Execute

Set V_TRIP

Sequence

New V_CCApplied =

Old V_CCApplied - Error

Old V_CCApplied + Error

Execute

Reset V_TRIP

Sequence

Apply 5V to V_CC

Decrement V_CC

(V_CC= V_CC- 10mV)

NO

RESET pin

goes active?

YES

Error ≥ Emax

Error > Emax

Measured V_TRIP

Desired V_TRIP

-

Error < Emax

DONE

Emax = Maximum Desired Error

FN8136.0

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March 17, 2005

X5648, X5649

Figure 4. Sample V

Reset Circuit

TRIP

V_P

4.7K

NC

4.7K

RESET

1

2

3

4

8

7

6

5

NC

X5648/49

V_TRIP

Adj.

+

Program

Reset V_TRIP

Test V_TRIP

Set V_TRIP

10K

SPI SERIAL MEMORY

Write Enable Latch

The device contains a write enable latch. This latch

must be SET before a write operation is initiated. The

WREN instruction will set the latch and the WRDI

instruction will reset the latch (Figure 3). This latch is

automatically reset upon a power-up condition and

after the completion of a valid write cycle.

The memory portion of the device is a CMOS serial

EEPROM array with Intersil’s block lock protection. The

array is internally organized as x 8. The device features

a Serial Peripheral Interface (SPI) and software proto-

col allowing operation on a simple four-wire bus.

™

The device utilizes Intersil’s proprietary Direct Write

cell, providing a minimum endurance of 100,000

cycles and a minimum data retention of 100 years.

Status Register

The RDSR instruction provides access to the status

register. The status register may be read at any time,

even during a write cycle. The status register is for-

matted as follows:

The device is designed to interface directly with the

synchronous Serial Peripheral Interface (SPI) of many

popular micro controller families. It contains an 8-bit

instruction register that is accessed via the SI input,

with data being clocked in on the rising edge of SCK.

CS must be LOW during the entire operation.

7

6

5

4

3

2

1

0

WPEN FLB

0

BL1 BL0 WEL WIP

All instructions (Table 1), addresses and data are trans-

ferred MSB first. Data input on the SI line is latched on

the first rising edge of SCK after CS goes LOW. Data is

output on the SO line by the falling edge of SCK. SCK is

static, allowing the user to stop the clock and then start

it again to resume operations where left off.

The Write-In-Progress (WIP) bit is a volatile, read only

bit and indicates whether the device is busy with an

internal nonvolatile write operation. The WIP bit is read

using the RDSR instruction. When set to a “1”, a non-

volatile write operation is in progress. When set to a

“0”, no write is in progress.

Table 1. Instruction Set

Instruction Name Instruction Format*

Operation

WREN

SFLB

0000 0110

0000 0000

0000 0100

0000 0101

0000 0001

0000 0011

0000 0010

Set the write enable latch (enable write operations)

Set flag bit

WRDI/RFLB

RSDR

Reset the write enable latch/reset flag bit

Read status register

WRSR

Write status register (watchdog, block lock, WPEN & flag bits)

Read data from memory array beginning at selected address

Write data to memory array beginning at selected address

READ

WRITE

Note: *Instructions are shown MSB in left most position. Instructions are transferred MSB first.

FN8136.0

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March 17, 2005

X5648, X5649

Table 2. Block Protect Matrix

WREN CMD Status Register Device Pin

Block

Status Register

WPEN, BL0, BL1

WD0, WD1

WEL

WPEN

WP#

Protected Block

Protected

Unprotected Block

Protected

0

1

X

1

0

X

0

X

1

Protected

Writable

Protected

Writable

Protected

Writable

Protected

Writable

The Write Enable Latch (WEL) bit indicates the sta-

tus of the write enable latch. When WEL = 1, the

latch is set HIGH and when WEL = 0 the latch is reset

LOW. The WEL bit is a volatile, read only bit. It can

be set by the WREN instruction and can be reset by

the WRDS instruction.

Setting the WP pin LOW while WPEN is a “1” while an

internal write cycle to the status register is in progress

will not stop this write operation, but the operation dis-

ables subsequent write attempts to the status register.

When WP is HIGH, all functions, including nonvolatile

writes to the status register operate normally. Setting

the WPEN bit in the status register to “0” blocks the

WP pin function, allowing writes to the status register

when WP is HIGH or LOW. Setting the WPEN bit to

“1” while the WP pin is LOW activates the programma-

ble ROM mode, thus requiring a change in the WP pin

prior to subsequent status register changes. This

allows manufacturing to install the device in a system

with WP pin grounded and still be able to program the

status register. Manufacturing can then load configura-

tion data, manufacturing time and other parameters

into the EEPROM, then set the portion of memory to

be protected by setting the block lock bits, and finally

set the “OTP mode” by setting the WPEN bit. Data

changes now require a hardware change.

The block lock bits, BL0 and BL1, set the level of block

lock protection. These nonvolatile bits are pro-

grammed using the WRSR instruction and allow the

user to protect one quarter, one half, all or none of the

EEPROM array. Any portion of the array that is block

lock protected can be read but not written. It will

remain protected until the BL bits are altered to disable

block lock protection of that portion of memory.

Status

Register Bits

Array Addresses Protected

X5648/X5649

None

BL1

BL0

0

1

0

1

0

1

$1800-$1FFF

$1000-$1FFF

Read Sequence

$0000-$1FFF

When reading from the EEPROM memory array, CS is

first pulled low to select the device. The 8-bit READ

instruction is transmitted to the device, followed by the

16-bit address. After the READ opcode and address

are sent, the data stored in the memory at the selected

address is shifted out on the SO line. The data stored

in memory at the next address can be read sequen-

tially by continuing to provide clock pulses. The

address is automatically incremented to the next

higher address after each byte of data is shifted out.

When the highest address is reached, the address

counter rolls over to address $0000 allowing the read

cycle to be continued indefinitely. The read operation

is terminated by taking CS high. Refer to the read

EEPROM array sequence (Figure 1).

The FLAG bit shows the status of a volatile latch that

can be set and reset by the system using the SFLB

and RFLB instructions. The flag bit is automatically

reset upon power-up.

The nonvolatile WPEN bit is programmed using the

WRSR instruction. This bit works in conjunction with the

WP pin to provide an in-circuit programmable ROM func-

tion (Table 2). WP is LOW and WPEN bit programmed

HIGH disables all status register write operations.

In Circuit Programmable ROM Mode

This mechanism protects the block lock and watchdog

bits from inadvertent corruption.

To read the status register, the CS line is first pulled low

to select the device followed by the 8-bit RDSR instruc-

tion. After the RDSR opcode is sent, the contents of the

status register are shifted out on the SO line. Refer to

the read status register sequence (Figure 2).

In the locked state (programmable ROM Mode) the

WP pin is LOW and the nonvolatile bit WPEN is “1”.

This mode disables nonvolatile writes to the device’s

status register.

FN8136.0

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March 17, 2005

X5648, X5649

Figure 5. Read EEPROM Array Sequence

CS

0

1

2

3

4

5

6

7

8

9

10

20 21 22 23 24 25 26 27 28 29 30

SCK

SI

Instruction

16 Bit Address

15 14 13

3

2

1

0

Data Out

High Impedance

7

6

5

4

3

2

1

0

SO

MSB

Write Sequence

OPERATIONAL NOTES

Prior to any attempt to write data into the device, the

Write Enable Latch (WEL) must first be set by issuing

the WREN instruction (Figure 3). CS is first taken LOW,

then the WREN instruction is clocked into the device.

After all eight bits of the instruction are transmitted, CS

must then be taken HIGH. If the user continues the

write operation without taking CS HIGH after issuing the

WREN instruction, the write operation will be ignored.

The device powers-up in the following state:

– The device is in the low power standby state.

– A HIGH to LOW transition on CS is required to enter

an active state and receive an instruction.

– SO pin is high impedance.

– The write enable latch is reset.

– The flag bit is reset.

To write data to the EEPROM memory array, the user

then issues the WRITE instruction followed by the 16

bit address and then the data to be written. Any

unused address bits are specified to be “0’s”. The

WRITE operation minimally takes 32 clocks. CS must

go low and remain low for the duration of the opera-

tion. If the address counter reaches the end of a page

and the clock continues, the counter will roll back to

the first address of the page and overwrite any data

that may have been previously written.

– Reset signal is active for t

.

PURST

Data Protection

The following circuitry has been included to prevent

inadvertent writes:

– A WREN instruction must be issued to set the write

enable latch.

– CS must come HIGH at the proper clock count in

order to start a nonvolatile write cycle.

For the page write operation (byte or page write) to be

completed, CS can only be brought HIGH after bit 0 of

the last data byte to be written is clocked in. If it is

brought HIGH at any other time, the write operation

will not be completed (Figure 4).

To write to the status register, the WRSR instruction is

followed by the data to be written (Figure 5). Data bits

0 and 1 must be “0”.

While the write is in progress following a status regis-

ter or EEPROM sequence, the status register may be

read to check the WIP bit. During this time the WIP bit

will be high.

FN8136.0

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March 17, 2005

X5648, X5649

Figure 6. Read Status Register Sequence

CS

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14

SCK

Instruction

SI

Data Out

High Impedance

SO

7

6

5

4

3

2

1

0

MSB

Figure 7. Write Enable Latch Sequence

CS

0

1

2

3

4

5

6

7

SCK

SI

High Impedance

SO

FN8136.0

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March 17, 2005

X5648, X5649

Figure 8. Write Sequence

CS

0

1

2

3

4

5

6

7

8

9

10

20 21 22 23 24 25 26 27 28 29 30 31

SCK

Instruction

16 Bit Address

15 14 13

Data Byte 1

3

2

1

0

7

6

5

4

3

2

1

0

SI

CS

32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47

SCK

SI

Data Byte 2

Data Byte 3

Data Byte N

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

6

5

4

3

2

1

0

Figure 9. Status Register Write Sequence

CS

0

1

2

3

4

5

6

7

8

7

9

10 11 12 13 14 15

SCK

Instruction

Data Byte

6

5

4

3

2

1

0

SI

High Impedance

SO

SYMBOL TABLE

WAVEFORM

INPUTS

OUTPUTS

Must be

steady

Will be

steady

May change

from LOW

to HIGH

Will change

from LOW

to HIGH

May change

from HIGH

to LOW

Will change

from HIGH

to LOW

Don’t Care:

Changes

Allowed

Changing:

State Not

Known

N/A

Center Line

is High

Impedance

FN8136.0

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March 17, 2005

X5648, X5649

ABSOLUTE MAXIMUM RATINGS

COMMENT

Temperature under bias ................... -65°C to+135°C

Storage temperature ........................ -65°C to+150°C

Stresses above those listed under “Absolute Maximum

Ratings” may cause permanent damage to the device.

This is a stress rating only; the functional operation of the

device (at these or any other conditions above those

listed in the operational sections of this specification) is

not implied. Exposure to absolute maximum rating condi-

tions for extended periods may affect device reliability.

Voltage on any Pin with respect to V ... -1.0V to +7V

SS

D.C. Output Current .............................................5mA

Lead temperature (soldering, 10 seconds)........ 300°C

RECOMMENDED OPERATING CONDITIONS

Temperature

Commercial

Industrial

Min.

0°C

Max.

70°C

Voltage Option

-2.7 or -2.7A

Supply Voltage

2.7V to 5.5V

4.5V-5.5V

-40°C

+85°C

Blank or -4.5A

D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)

Limits

Symbol

Parameter

Min.

Typ.

Max.

Unit

Test Conditions

I_CC1

V_CCwrite current (active)

5

mA

SCK = V_CCx 0.1/V_CCx 0.9 @ 2MHz,

SO = Open

I_CC2

I_SB

V_CCread current (active)

0.4

1

mA

µA

SCK = V_CCx 0.1/V_CCx 0.9 @ 2MHz,

SO = Open

V_CCstandby current

WDT = OFF

CS = V_CC, V_IN= V_SSor V_CC

_CC= 5.5V

,

V

I_LI

Input leakage current

Output leakage current

Input LOW voltage

0.1

10

µA

V

V_IN= V_SSto V_CC

I_LO

V_OUT= V_SSto V_CC

(1)

V_IL

-0.5

V_CCx 0.3

V_CC+ 0.5

0.4

(1)

V_IH

Input HIGH voltage

V_CCx 0.7

V

V_OL1

V_OL2

V_OL3

V_OH1

V_OH2

V_OH3

V_OLS

Output LOW voltage

Output HIGH voltage

Reset output LOW voltage

V

V_CC> 3.3V, I_OL= 2.1mA

0.4

V

2V < V_CC≤ 3.3V, I_OL= 1mA

V_CC≤ 2V, I_OL= 0.5mA

0.4

V

V_CC- 0.8

V_CC- 0.4

V_CC- 0.2

V

V_CC> 3.3V, I_OH= –1.0mA

2V < V_CC≤ 3.3V, I_OH= –0.4mA

V_CC≤ 2V, I_OH= -0.25mA

V

0.4

V

I_OL= 1mA

CAPACITANCE T = +25°C, f = 1MHz, V = 5V

A

CC

Symbol

Test

Max.

Unit

Conditions

V_OUT= 0V

V_IN= 0V

(2)

C_OUT

Output capacitance (SO, RESET/RESET)

Input capacitance (SCK, SI, CS, WP)

8

6

pF

(2)

C_IN

Notes: (1) V_ILmin. and V_IHmax. are for reference only and are not tested.

(2) This parameter is periodically sampled and not 100% tested.

FN8136.0

March 17, 2005

10

X5648, X5649

EQUIVALENT A.C. LOAD CIRCUIT AT 5V V

A.C. TEST CONDITIONS

CC

Input pulse levels

V_CCx 0.1 to V_CCx 0.9

10ns

5V

Input rise and fall times

Input and output timing level

V_CCx 0.5

4.6kΩ

2.06kΩ

Output

3.03kΩ

RESET/RESET

30pF

100pF

A.C. CHARACTERISTICS (Over recommended operating conditions, unless otherwise specified)

Serial Input Timing

2.7-5.5V

Symbol

f_SCK

t_CYC

t_LEAD

t_LAG

t_WH

Parameter

Min.

0

Max.

Unit

MHz

ns

Clock frequency

Cycle time

2

500

250

200

250

50

CS lead time

ns

CS lag time

ns

Clock HIGH time

Clock LOW time

Data setup time

Data hold time

Input rise time

Input fall time

CS deselect time

Write cycle time

ns

t_WL

ns

t_SU

ns

t_H

50

ns

(3)

t_RI

100

ns

(3)

t_FI

ns

t_CS

500

ns

(4)

t_WC

10

ms

Serial Input Timing

t_CS

CS

t_LEAD

t_LAG

SCK

t_SU

t_H

t_RI

t_FI

SI

MSB IN

LSB IN

High Impedance

SO

FN8136.0

March 17, 2005

11

X5648, X5649

Serial Output Timing

Symbol

2.7-5.5V

Max.

Parameter

Min.

Unit

MHz

ns

f_SCK

t_DIS

t_V

Clock frequency

Output disable time

0

2

250

Output valid from clock low

Output hold time

ns

t_HO

0

ns

(3)

t_RO

Output rise time

100

ns

(3)

t_FO

Output fall time

ns

Notes: (3) This parameter is periodically sampled and not 100% tested.

(4) t_WCis the time from the rising edge of CS after a valid write sequence has been sent to the end of the self-timed internal nonvolatile

write cycle.

Serial Output Timing

CS

SCK

SO

t_CYC

t_WH

t_LAG

t_V

t_HO

t_WL

t_DIS

MSB Out

MSB–1 Out

LSB Out

ADDR

LSB IN

SI

Power-Up and Power-Down Timing

V_TRIP

V_CC

t_PURST

0 Volts

t_PURST

t_F

t_RPD

t_R

RESET (X5648)

RESET (X5649)

FN8136.0

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March 17, 2005

X5648, X5649

RESET Output Timing

Symbol

Parameter

Min.

Typ.

Max.

Unit

V_TRIP

Reset trip point voltage, X5648-4.5A, X5648-4.5A

Reset trip point voltage, X5648, X5649

Reset trip point voltage, X5648-2.7A, X5649-2.7A

Reset trip point voltage, X5648-2.7, X5649-2.7

4.5

4.63

4.38

2.93

2.63

4.75

4.5

3.0

4.25

2.85

2.55

V

2.7

V_TH

V_TRIPhysteresis (HIGH to LOW vs. LOW to HIGH V_TRIPvoltage)

20

mV

ms

ns

µs

V

t_PURST

Power-up reset time out

V_CCdetect to reset/output

V_CCfall time

100

200

280

500

(5)

t_RPD

(5)

t_F

100

1

(5)

t_R

V_CCrise time

V_RVALIDReset valid V_CC

Note: (5) This parameter is periodically sampled and not 100% tested.

V

Set Conditions

TRIP

t_THD

V_CC

V_TRIP

t_TSU

t_RP

t_P

t_VPH

t_VPS

CS

t_VPO

t_VPH

t_VPS

V_P

SCK

SI

V_P

t_VPO

FN8136.0

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X5648, X5649

V

Reset Conditions

TRIP

V_CC

*

t_RP

t_P

t_VP1

t_VPS

CS

t_VPS

t_VPO

t_VPH

V_CC

SCK

SI

V_P

t_VPO

*V_CC> Programmed V_TRIP

V

Programming Specifications V = 1.7-5.5V; Temperature = 0°C to 70°C

CC

TRIP

Parameter

t_VPS

t_VPH

t_P

Description

SCK V_TRIPprogram voltage setup time

Min. Max. Unit

1

µs

ms

V

SCK V_TRIPprogram voltage hold time

V_TRIPprogram pulse width

1

t_TSU

t_THD

t_WC

V_TRIPlevel setup time

10

V_TRIPlevel hold (stable) time

V_TRIPwrite cycle time

10

t_RP

V_TRIPprogram cycle recovery period (between successive programming cycles)

SCK V_TRIPprogram voltage off time before next cycle

Programming voltage

10

0

t_VPO

V_P

V_TRAN

V_ta1

15

18

5.0

V_TRIPprogramed voltage range

1.7

-0.1

-25

V

Initial V_TRIPprogram voltage accuracy (V_CCapplied - V_TRIP) (programmed at 25°C)

+0.4

+25

V

V_ta2

Subsequent V_TRIPprogram voltage accuracy [(V_CCapplied - V_ta1) - V_TRIP

(programmed at 25°C)

)

mV

V_tr

V_TRIPprogram voltage repeatability (successive program operations) (programmed at

25°C)

-25

+25

mV

V_tv

V_TRIPprogram variation after programming (0 - 75°C). (programmed at 25°C.)

V_TRIPprogramming parameters are periodically sampled and are not 100% tested.

FN8136.0

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X5648, X5649

TYPICAL PERFORMANCE

Supply Current vs. Temperature (I

t

vs. Temperature

V

)

SB

PURST

CC

205

200

195

190

185

180

175

170

165

18

16

Watchdog Timer On (V_CC= 5V)

14

12

10

8

Watchdog Timer On (V_CC= 5V)

6

4

Watchdog Timer Off (V_CC= 3V, 5V)

2

160

-40

25

Degrees °C

90

0

-40

25

90

Temp (°C)

V

vs. Temperature (programmed at 25°C)

TRIP

5.025

V_TRIP= 5V

5.000

4.975

3.525

3.500

V_TRIP= 3.5V

3.475

2.525

2.500

2.475

V_TRIP= 2.5V

0

25

85

Temperature

FN8136.0

March 17, 2005

15

X5648, X5649

PACKAGING INFORMATION

8-Lead Plastic Dual In-Line Package Type P

0.430 (10.92)

0.360 (9.14)

0.260 (6.60)

0.240 (6.10)

Pin 1 Index

Pin 1

0.060 (1.52)

0.020 (0.51)

0.300

(7.62) Ref.

Half Shoulder Width On

All End Pins Optional

0.145 (3.68)

0.128 (3.25)

Seating

Plane

0.025 (0.64)

0.015 (0.38)

0.065 (1.65)

0.150 (3.81)

0.125 (3.18)

0.045 (1.14)

0.110 (2.79)

0.090 (2.29)

0.020 (0.51)

0.016 (0.41)

0.325 (8.25)

0.300 (7.62)

.073 (1.84)

Max.

0°

Typ. 0.010 (0.25)

15°

NOTE:

1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)

2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH

FN8136.0

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X5648, X5649

PACKAGING INFORMATION

14-Lead Plastic, SOIC, Package Code S14

0.150 (3.80) 0.228 (5.80)

0.158 (4.00) 0.244 (6.20)

Pin 1 Index

Pin 1

0.014 (0.35)

0.020 (0.51)

0.336 (8.55)

0.345 (8.75)

(4X) 7°

0.053 (1.35)

0.069 (1.75)

0.004 (0.10)

0.010 (0.25)

0.050 (1.27)

0.050"Typical

0.010 (0.25)

0.020 (0.50)

X 45°

0.050"Typical

0° - 8°

0.250"

0.0075 (0.19)

0.010 (0.25)

0.016 (0.410)

0.037 (0.937)

0.030"Typical

14 Places

FOOTPRINT

NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)

FN8136.0

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X5648, X5649

Ordering Information

V

Operating

Temperature Range

Part Number RESET

(Active LOW)

Part Number RESET

(Active HIGH)

TRIP

V

Range

Package

8 pin PDIP

14L SOIC

CC

4.5-5.5V

4.5.4.75

0-70°C

-40-85°C

0-70°C

-40-85°C

0-70°C

X5648P-4.5A

X5648S14-4.5A

X5648S14I-4.5A

X5648P

X5649P-4.5A

X5649S14-4.5A

X5649S14I-4.5A

X5649P

4.5-5.5V

4.25.4.5

8 pin PDIP

14L SOIC

X5648S14

X5649S14

X5648S14I

X5649S14I

2.7-5.5V

2.85-3.0

2.55-2.7

14L SOIC

X5648S14-2.7A

X5648S14-2.7

X5649S14-2.7A

X5649S14-2.7

Part Mark Information

X5648/49 W

Blank = 14-Lead SOIC

P = 8 Pin DIP

X

Blank = 5V ±10%, 0°C to +70°C, V

= 4.25-4.5

TRIP

AL = 5V±10%, 0°C to +70°C, V

= 4.5-4.75

TRIP

I = 5V ±10%, -40°C to +85°C, V

= 4.25-4.5

TRIP

AM = 5V ±10%, -40°C to +85°C, V

= 4.5-4.75

TRIP

F = 2.7V to 5.5V, 0°C to +70°C, V

= 2.55-2.7

TRIP

AN = 2.7V to 5.5V, 0°C to +70°C, V

G = 2.7V to 5.5V, -40°C to +85°C, V

= 2.85-3.0

= 2.55-2.7

TRIP

AP = 2.7V to 5.5V, -40°C to +85°C, V

= 2.85-3.0

TRIP

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN8136.0

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型号:	X5649P
是否Rohs认证：	不符合
生命周期：	Transferred
IHS 制造商：	XICOR INC
包装说明：	PLASTIC, DIP-8
Reach Compliance Code：	unknown
风险等级：	5.78
Is Samacsys：	N
可调阈值：	YES
模拟集成电路 - 其他类型：	POWER SUPPLY MANAGEMENT CIRCUIT
JESD-30 代码：	R-PDIP-T8
JESD-609代码：	e0
长度：	10.03 mm
信道数量：	1
功能数量：	1
端子数量：	8
最高工作温度：	70 °C
最低工作温度：
封装主体材料：	PLASTIC/EPOXY
封装代码：	DIP
封装形状：	RECTANGULAR
封装形式：	IN-LINE
认证状态：	Not Qualified
座面最大高度：	4.32 mm
最大供电电压 (Vsup)：	5.5 V
最小供电电压 (Vsup)：	4.5 V
标称供电电压 (Vsup)：	5 V
表面贴装：	NO
技术：	CMOS
温度等级：	COMMERCIAL
端子面层：	Tin/Lead (Sn/Pb)
端子形式：	THROUGH-HOLE
端子节距：	2.54 mm
端子位置：	DUAL
宽度：	7.62 mm
Base Number Matches：	1

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