X9119
Four of the six instructions are four bytes in length. These
instructions are:
Instruction and Register
Description
• Read Wiper Counter Register – Reads the current wiper
position of the selected potentiometer.
Device Addressing
• Write Wiper Counter Register – Changes current wiper position
of the selected potentiometer.
WIPER COUNTER REGISTER (WCR)
The X9119 contains a wiper counter register (refer to Table 4) for
the XDCP potentiometer. The WCR is equivalent to a serial-in,
parallel-out register/counter with its outputs decoded to select
one of 1024 switches along its resistor array. The contents of the
WCR can be altered in one of three ways:
• Read Data Register – Reads the contents of the selected Data
Register.
• Write Data Register – Writes a new value to the selected Data
Register.
The basic sequence of the four byte instructions is illustrated in
Figure 6 on page 8. These 4-byte instructions exchange data
between the WCR and one of the data registers. A transfer from
a data register to a WCR is essentially a write to a static RAM,
with the static RAM controlling the wiper position. The response
1. It may be written directly by the host via the write wiper
counter register instruction (serial load).
2. It may be written indirectly by transferring the contents of one
of four associated data registers via the XFR data register.
3. It is loaded with the contents of its data register zero (R0)
upon power-up.
of the wiper to this action will be delayed by t
. A transfer
WRL
from the WCR (current wiper position), to a data register is a
write-to-nonvolatile memory and takes a minimum of t to
The wiper counter register is a volatile register; that is, its
contents are lost when the X9119 is powered-down. Although the
register is automatically loaded with the value in DR0 upon
power-up, this may be different from the value present at
power-down. Power-up guidelines are recommended to ensure
proper loadings of the DR0 value into the WCR.
WR
complete. The transfer can occur between one of the four
potentiometers and one of its associated registers.
Two instructions (Figure 7 on page 8) require a 2-byte sequence
to complete. These instructions transfer data between the host
and the X9119; either between the host and one of the data
registers or directly between the host and the wiper counter
register. These instructions are:
DATA REGISTERS (DR0 TO DR3)
The potentiometer has four 10-bit nonvolatile data registers.
These can be read or written directly by the host. Data can also
be transferred between any of the four data registers and the
wiper counter register. All operations changing data in one of the
data registers is a nonvolatile operation and will take a
maximum of 10ms.
• XFR Data Register to Wiper Counter Register – This transfers
the contents of one specified data register to the wiper counter
register.
• XFR Wiper Counter Register to Data Register – This transfers
the contents of the wiper counter register to the specified data
register.
If the application does not require storage of multiple settings for
the potentiometer, the Data Registers can be used as regular
memory locations for system parameters or user preference
data.
See “Instruction Format” on page 8 for more details.
POWER-UP AND POWER-DOWN REQUIREMENTS
There are no restrictions on the power-up condition of V and
CC
the voltages applied to the potentiometer pins provided that the
Bit 9 to Bit 0 are used to store one of the 1024 wiper position (0
~1023).
V
is always more positive than or equal to the voltages at R ,
CC
H
R , and R , i.e., V ≥ R , R , R . There are no restrictions on
L
W
CC
H
L
W
the power-down condition. However, the datasheet parameters
for the DCP do not apply until 1ms after V reaches its final
CC
value.
TABLE 4. WIPER CONTROL REGISTER, WCR (10-BIT), WCR9–WCR0: USED TO STORE THE CURRENT WIPER POSITION (VOLATILE, V)
WCR9
V
WCR8
V
WCR7
V
WCR6
V
WCR5
V
WCR4
V
WCR3
V
WCR2
V
WCR1
V
WCR0
V
(MSB)
(LSB)
TABLE 5. DATA REGISTER, DR (10-BIT), BIT 9–BIT 0: USED TO STORE WIPER POSITIONS OR DATA (NONVOLATILE, NV)
BIT 9
NV
BIT 8
NV
BIT 7
NV
BIT 6
NV
BIT 5
NV
BIT 4
NV
BIT 3
NV
BIT 2
NV
BIT 1
NV
BIT 0
NV
MSB
LSB
FN8162 Rev 5.00
July 5, 2016
Page 7 of 18
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