X9313ZSIZT1应用文章市场行情现货热卖使用介绍供应商报价-中国IC网-芯三七

DATASHEET

X9313

FN8177

Rev 7.00

October 7, 2015

Digitally Controlled Potentiometer (XDCP™) Linear, 32 Taps, 3 Wire Interface,

Terminal Voltages ± VCC

The Intersil X9313 is a digitally controlled potentiometer

(XDCP). The device consists of a resistor array, wiper

switches, a control section, and nonvolatile memory. The

Features

• Solid-state potentiometer

wiper position is controlled by a 3-wire interface.

• 3-wire serial interface

The potentiometer is implemented by a resistor array

composed of 31 resistive elements and a wiper switching

network. Between each element and at either end are tap

points accessible to the wiper terminal. The position of the

wiper element is controlled by the CS, U/D, and INC inputs.

The position of the wiper can be stored in nonvolatile

memory and then be recalled upon a subsequent power-up

operation.

• 32 wiper tap points

- Wiper position stored in nonvolatile memory and

recalled on power-up

• 31 resistive elements

- Temperature compensated

- End-to-end resistance range ±20%

- Terminal voltages, -V

to +V

CC

• Low power CMOS

The device can be used as a three-terminal potentiometer or

as a two-terminal variable resistor in a wide variety of

applications including:

- V

CC

= 3V or 5V

- Active current, 3mA max.

- Standby current, 500µA max.

• Control

• High reliability

• Parameter adjustments

• Signal processing

- Endurance, 100,000 data changes per bit

- Register data retention, 100 years

• R

TOTAL

values = 1k, 10k, 50k

• Packages

- 8 Ld SOIC, 8 Ld MSOP and 8 Ld PDIP

• Pb-free available (RoHS compliant)

Block Diagram

DECODER

31

5-BIT

UP/DOWN

COUNTER

U/D

INC

CS

R

/V

H

V

(SUPPLY VOLTAGE)

CC

30

29

28

R

/V

H

UP/DOWN

(U/D)

5-BIT

NONVOLATILE

MEMORY

CONTROL

AND

MEMORY

ONE OF

INCREMENT

(INC)

/V

W

THIRTY-TWO

OUTPUTS

TRANSFER

GATES

RESISTOR

ARRAY

ACTIVE

AT A

TIME

DEVICE SELECT

(CS)

R /V

L

2

STORE AND

RECALL

CONTROL

CIRCUITRY

V

(GROUND)

SS

1

0

V

CC

SS

GENERAL

R /V

L

/V

R

W

DETAILED

FN8177 Rev 7.00

October 7, 2015

Page 1 of 12

X9313

Ordering Information

TEMPERATURE

RANGE

PART

MARKING

V

RANGE

(V)

R

PKG.

DWG. #

CC

TOTAL

(k)

PART NUMBER

X9313UMIZ* (Note)

X9313USZ* (Note)

X9313USIZ* (Note)

X9313WMZ* (Note)

X9313WMIZ* (Note)

X9313WPIZ

(°C)

PACKAGE

8 Ld MSOP (Pb-free)

8 Ld SOIC (Pb-free)

8 Ld MSOP (Pb-free)

8 Ld PDIP*** (Pb-free)

8 Ld SOIC (Pb-free)

8 Ld MSOP (Pb-free)

8 Ld SOIC (Pb-free)

8 Ld MSOP

DDB

4.5 to 5.5

50

-40 to +85

0 to +70

M8.118

M8.15

X9313U Z

X9313U ZI

DDF

-40 to +85

0 to +70

M8.15

10

M8.118

MDP0031

M8.15

DDE

-40 to +85

0 to +70

X9313WP ZI

X9313W Z

X9313WS ZI

DDJ

X9313WSZ* (Note)

X9313WSIZ* (Note)

X9313ZMZ* (Note)

X9313ZMIZ* (Note)

X9313ZSZ* (Note)

X9313ZSIZ* (Note)

X9313UMZ* (Note)

X9313UMZ-3* (Note)

X9313UMIZ-3* (Note)

X9313USZ-3* (Note)

X9313WMZ-3* (Note)

X9313WMIZ-3* (Note)

X9313WSZ-3* (Note)

X9313ZMZ-3* (Note)

X9313ZMIZ-3* (Note)

X9313ZSZ-3* (Note)

X9313ZSIZ-3* (Note)

-40 to +85

0 to +70

M8.15

1

M8.118

M8.15

DDH

-40 to +85

0 to +70

X9313 Z

X9313ZS ZI

DDC

-40 to +85

0 to +70

M8.15

3 to 5.5

50

M8.118

M8.15

DDD

0 to +70

8 Ld MSOP

13UEZ

-40 to +85

0 to +70

8 Ld MSOP (Pb-free)

8 Ld SOIC (Pb-free)

8 Ld MSOP (Pb-free)

8 Ld SOIC (Pb-free)

8 Ld MSOP (Pb-free)

8 Ld SOIC (Pb-free)

X9313U ZD

DDG

10

1

0 to +70

M8.118

M8.15

13WEZ

-40 to +85

0 to +70

X9313W ZD

DDK

0 to +70

M8.118

M8.15

13ZEZ

-40 to +85

0 to +70

X9313Z ZD

X9313Z ZE

-40 to +85

M8.15

NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100%

matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil

Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

*Add “T1” suffix for tape and reel. Please refer to TB347 for details on reel specifications.

**Add "T2" suffix for tape and reel. Please refer to TB347 for details on reel specifications.

***Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications.

Up/Down (U/D)

Pin Descriptions

The U/D input controls the direction of the wiper movement

and whether the counter is incremented or decremented.

RH/VH and RL/VL

The high (RH/VH) and low (RL/VL) terminals of the X9313 are

Increment (INC)

equivalent to the fixed terminals of a mechanical

potentiometer. The terminology of RL/VL and RH/VH

references the relative position of the terminal in relation to

wiper movement direction selected by the U/D input and not

the voltage potential on the terminal.

The INC input is negative-edge triggered. Toggling INC will

move the wiper and either increment or decrement the counter

in the direction indicated by the logic level on the U/D input.

RW/VW

RW/VW is the wiper terminal and is equivalent to the movable

terminal of a mechanical potentiometer. The position of the

wiper within the array is determined by the control inputs. The

wiper terminal series resistance is typically 40 at V

= 5V.

CC

FN8177 Rev 7.00

October 7, 2015

Page 2 of 12

X9313

The wiper, when at either fixed terminal, acts like its

mechanical equivalent and does not move beyond the last

position. That is, the counter does not wrap around when

clocked to either extreme.

Chip Select (CS)

The device is selected when the CS input is LOW. The current

counter value is stored in nonvolatile memory when CS is

returned HIGH while the INC input is also HIGH. After the store

operation is complete, the X9313 will be placed in the low power

standby mode until the device is selected once again.

The electronic switches on the device operate in a “make

before break” mode when the wiper changes tap positions. If

the wiper is moved several positions, multiple taps are

Pinouts

connected to the wiper for t (INC to V change). The

IW

W

X9313

(8 LD PDIP, 8 LD SOIC)

TOP VIEW

R

value for the device can temporarily be reduced by a

TOTAL

significant amount if the wiper is moved several positions.

When the device is powered-down, the last wiper position

stored will be maintained in the nonvolatile memory. When

power is restored, the contents of the memory are recalled and

the wiper is set to the value last stored.

INC

1

2

3

4

8

7

6

5

VCC

U/D

RH/VH

VSS

CS

X9313

RL/VL

RW/VW

Instructions and Programming

The INC, U/D and CS inputs control the movement of the wiper

along the resistor array. With CS set LOW the device is

selected and enabled to respond to the U/D and INC inputs.

HIGH to LOW transitions on INC will increment or decrement

(depending on the state of the U/D input) a seven bit counter.

The output of this counter is decoded to select one of thirty-two

wiper positions along the resistive array.

X9313

(8 LD MSOP)

TOP VIEW

RH/VH

U/D

INC

VCC

1

8

7

6

5

VSS

RW/VW

RL/VL

2

3

4

X9313

The value of the counter is stored in nonvolatile memory

whenever CS transitions HIGH while the INC input is also

HIGH.

CS

The system may select the X9313, move the wiper and

deselect the device without having to store the latest wiper

position in nonvolatile memory. After the wiper movement is

performed as previously described and once the new position

is reached, the system must keep INC LOW while taking CS

HIGH. The new wiper position will be maintained until changed

by the system or until a power-up/down cycle recalled the

previously stored data.

TABLE 1. PIN NAMES

DESCRIPTION

High terminal

SYMBOL

RH/VH

RW/VW

RL/VL

VSS

Wiper terminal

Low terminal

Ground

This procedure allows the system to always power-up to a

preset value stored in nonvolatile memory; then during system

operation, minor adjustments could be made. The adjustments

might be based on user preference, system parameter

changes due to temperature drift, etc.

VCC

Supply voltage

U/D

Up/Down control input

Increment control input

Chip Select control input

INC

CS

The state of U/D may be changed while CS remains LOW. This

allows the host system to enable the device and then move the

wiper up and down until the proper trim is attained.

Principles of Operation

There are three sections of the X9313: the input control,

counter and decode section; the nonvolatile memory; and the

resistor array. The input control section operates just like an

up/down counter. The output of this counter is decoded to turn

on a single electronic switch connecting a point on the resistor

array to the wiper output. Under the proper conditions, the

contents of the counter can be stored in nonvolatile memory

and retained for future use. The resistor array is comprised of

31 individual resistors connected in series. At either end of the

array and between each resistor is an electronic switch that

transfers the potential at that point to the wiper.

TABLE 2. MODE SELECTION

CS

INC

U/D

MODE

L

H

Wiper up

L

Wiper down

H

X

Store wiper position

H

X

L

X

Standby current

No store, return to standby

FN8177 Rev 7.00

October 7, 2015

Page 3 of 12

X9313

TABLE 2. MODE SELECTION

CS

INC

U/D

MODE

L

H

Wiper up (not recommended)

Wiper down (not recommended)

L

Symbol Table

WAVEFORM

INPUTS

OUTPUTS

Must be

steady

Will be

steady

May change

from Low to

High

Will change

from Low to

High

May change

from High to

Low

Will change

from High to

Low

Don’t Care:

Changes

Allowed

Changing:

State Not

Known

N/A

Center Line

is High

Impedance

FN8177 Rev 7.00

October 7, 2015

Page 4 of 12

X9313

Absolute Maximum Ratings

Recommended Operating Conditions

Temperature Under Bias . . . . . . . . . . . . . . . . . . . . .-65°C to +135°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C

Voltage on CS, INC, U/D, and

Temperature:

Commercial. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C

Industrial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C

Supply Voltage (VCC):

X9313 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5V ±10%

X9313-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3V to 5.5V

Max Wiper current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±4.4mA

Power rating:

V

with Respect to V . . . . . . . . . . . . . . . . . . . . . . . -1V to +7V

SS

CC

Voltage on V , V , V

W

H

L

with respect to V . . . . . . . . . . . . . . . . . . . . . . . . . . . . -6V to +7V

SS

V = |V - V |:

H

L

X9313Z . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4V

X9313W, X9313U . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10V

R

 10k . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10mW

1k. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16mW

TOTAL

I

(10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±8.8mA

W

TOTAL

ESD Rating

Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

Pb-free PDIPs can be used for through hole wave solder processing

only. They are not intended for use in Reflow solder processing

applications

Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.0kV

Machine Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200V

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and

result in failures not covered by warranty.

Potentiometer Characteristics

Over recommended operating conditions, unless otherwise stated.

LIMITS

TYP

SYMBOL

PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

%

End-to-end Resistance Tolerance

±20

V

Terminal Voltage

-V

+V

CC

V

VH

H

L

CC

V

-V

+V

CC

V

VL

CC

R

Wiper Resistance

Wiper Current

I

= (V - V )/R

, V

= 5V

40

100



W

H

L

TOTAL CC

I

±4.4

mA

dBV

%

W

Noise (Note 5)

Ref: 1kHz

-120

3

Resolution

Absolute Linearity (Note 1)

R

- R

±1

MI

(Note 3)

W(n)(actual)

W(n)(expected)

Relative Linearity (Note 2)

- (R

+MI)

±0.2

MI

W(n+1)

W(n)

(Note 3)

R

Temperature Coefficient (Note 5)

±300

±20

ppm/°C

TOTAL

Ratiometric Temperature Coefficient

(Note 5)

C /C /C

W

Potentiometer Capacitances

See Circuit #3

10/10/25

pF

H

L

(Note 5)

NOTES:

1. Absolute linearity is utilized to determine actual wiper voltage versus expected voltage = (V

- V

) = ±1 MI maximum.

W(n)(actual)

+ MI) = ±0.2 MI.

W(n)(expected)

2. Relative linearity is a measure of the error in step size between taps = R

W(n+1)

- (R

W(n)

3. 1 MI = minimum increment = R

/31.

TOT

FN8177 Rev 7.00

October 7, 2015

Page 5 of 12

X9313

DC Electrical Specifications Over recommended operating conditions, unless otherwise stated.

LIMITS

TYP

SYMBOL

PARAMETER

Active Current

TEST CONDITIONS/NOTES

MIN

(Note 4)

MAX

UNIT

V

CS = V , U/D = V or V and

1

3

mA

CC

IL IL IH

INC = 0.42/2.4V @ max t

CYC

I

SB

Standby Supply Current

CS = V

- 0.3V, U/D and INC = V or

200

500

±10

µA

CC

- 0.3V

SS

V

CC

I

CS, INC, U/D Input Leakage Current

CS, INC, U/D Input HIGH Current

CS, INC, U/D Input LOW Current

CS, INC, U/D Input Capacitance

V

= V to V

SS CC

µA

V

LI

IN

V

2

IH

V

+0.8

V

IL

C

V

= 5V, V = V , T = +25°C,

IN SS

10

pF

IN

CC

A

(Note 5)

f = 1MHz

Endurance and Data Retention

PARAMETER

MIN

UNIT

Minimum endurance

100,000

Data changes per bit

per register

Data retention

100

Years

V

/R

H

R

TOTAL

V

/R

H

TEST POINT

/R

R

L

H

C

L

C

W

C

H

10pF

V

S

V

VW

TEST POINT

/R

W

25pF

FORCE

CURRENT

V

W

10pF

V /R

L

V /R

R

L

W

FIGURE 1. TEST CIRCUIT #1

FIGURE 2. TEST CIRCUIT #2

FIGURE 3. CIRCUIT #3 SPICE MACRO

MODEL

FN8177 Rev 7.00

October 7, 2015

Page 6 of 12

X9313

AC Electrical Specifications Over recommended operating conditions, unless otherwise stated.

LIMITS

TYP

SYMBOL

PARAMETER

MIN

100

2.9

1

(Note 4)

MAX

UNIT

ns

t

CS to INC Setup

CI

ID

DI

INC HIGH to U/D Change

U/D to INC Setup

INC LOW Period

ns

µs

t

µs

IL

IH

IC

t

INC HIGH Period

1

µs

INC Inactive to CS Inactive

CS Deselect Time (STORE)

CS Deselect Time (NO STORE)

1

µs

t

20

100

ms

ns

CPH

t

INC to V Change

W

5

µs

IW

t

INC Cycle Time

2

µs

CYC

t , t (Note 5)

INC Input Rise and Fall Time

Power-up to Wiper Stable

500

50

µs

R

F

t

(Note 5)

10

µs

PU

t

V

(Note 5)

V

Power-up Rate

0.2

V/ms

ms

R

CC

t

(Note 5)

Store Cycle

WR

NOTES:

4. Typical values are for T = +25°C and nominal supply voltage.

A

5. This parameter is not 100% tested.

1ms after V

reaches its final value. The V

ramp

CC

Power-Up and Power-Down Requirements

CC

specification is always in effect. In order to prevent unwanted

tap position changes, or an inadvertent store, bring the CS and

INC high before or concurrently with the VCC pin on power-up.

The recommended power-up sequence is to apply V /V

CC SS

first, then the potentiometer voltages. During power-up, the

data sheet parameters for the DCP do not fully apply until

CS

t

CYC

t

CPH

CI

IL

IH

IC

90%

INC

U/D

10%

t

R

ID

DI

F

t

IW

(SEE NOTE)

MI

V

W

NOTE: MI IN THE AC TIMING DIAGRAM REFERS TO THE MINIMUM INCREMENTAL CHANGE IN THE V OUTPUT DUE TO A CHANGE IN

W

THE WIPER POSITION.

FIGURE 4. AC TIMING DIAGRAM

FN8177 Rev 7.00

October 7, 2015

Page 7 of 12

X9313

Applications Information

Electronic digitally controlled potentiometers (XDCP) provide

three powerful application advantages:

1. The variability and reliability of a solid-state potentiometer.

2. The flexibility of computer-based digital controls.

3. The retentivity of nonvolatile memory used for the storage

of multiple potentiometer settings or data.

Basic Configurations of Electronic Potentiometers

V

R

V

R

V

H

L

V

/R

W

V

I

THREE-TERMINAL POTENTIOMETER;

VARIABLE VOLTAGE DIVIDER

TWO-TERMINAL VARIABLE RESISTOR;

VARIABLE CURRENT

Basic Circuits

BUFFERED REFERENCE VOLTAGE

CASCADING TECHNIQUES

NONINVERTING AMPLIFIER

R

+V

+5V

1

LM308A

V

+V

+

–

S

+5V

V

O

VW

OP-07

+

–

V

X

REF

-5V

VW/RW

V

OUT

R

2

+V

-5V

R

1

V

W

V

= V /R

W W

OUT

(a)

(b)

V

= (1 + R /R )V

2 1 S

O

VOLTAGE REGULATOR

OFFSET VOLTAGE ADJUSTMENT

COMPARATOR WITH HYSTERESIS

R

2

1

LT311A

–

V

S

V

S

V

(REG)

V

O

317

IN

O

+

100k

R

1

–

+

V

O

TL072

I

adj

R

2

1

10k

R

2

10k

V

= [R /(R + R )] V (max)

1 1 2 O

UL

LL

= [R /(R + R )] V (min)

1

2

O

V

(REG) = 1.25V (1 + R /R ) + I R

ADJ 2

O

2

1

+12V

-12V

(FOR ADDITIONAL CIRCUITS SEE AN115)

FN8177 Rev 7.00

October 7, 2015

Page 8 of 12

X9313

Revision History

The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make

sure that you have the latest revision.

DATE

REVISION

CHANGE

October 7, 2015

FN8177.7

Added Revision History beginning with Rev 7.

Added About Intersil Verbiage.

Updated Ordering Information on page 2.

DC Electrical Spec Table on page 6 - changed I

for Parameter V

Active Current to I

SB

CC

Updated POD M8.118 to most current revision with changes as follows:

Corrected lead width dimension in side view 1 from "0.25 - 0.036" to "0.25 - 0.36"

Updated to new intersil format by adding land pattern and moving dimensions

from table onto drawing.

Updated POD M8.15 to most current revision with changes as follows:

Changed Note 1 "1982" to "1994"

Changed in Typical Recommended Land Pattern the following:

2.41(0.095) to 2.20(0.087)

0.76 (0.030) to 0.60(0.023)

0.200 to 5.20(0.205)

Updated to new POD format by removing table and moving dimensions onto

drawing and adding land pattern.

About Intersil

Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products

address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.

For the most updated datasheet, application notes, related documentation and related parts, please see the respective product

information page found at www.intersil.com.

You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.

Reliability reports are also available from our website at www.intersil.com/support

FN8177 Rev 7.00

October 7, 2015

Page 9 of 12

X9313

Package Outline Drawing

M8.118

8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE

Rev 4, 7/11

5

3.0±0.05

A

DETAIL "X"

D

8

1.10 MAX

SIDE VIEW 2

0.09 - 0.20

4.9±0.15

3.0±0.05

5

0.95 REF

PIN# 1 ID

1

2

B

0.65 BSC

GAUGE

PLANE

TOP VIEW

0.25

3°±3°

0.55 ± 0.15

DETAIL "X"

0.85±010

H

C

SEATING PLANE

0.10 C

0.25 - 0.36

0.10 ± 0.05

0.08

C A-B D

M

SIDE VIEW 1

(5.80)

NOTES:

1. Dimensions are in millimeters.

(4.40)

(3.00)

2. Dimensioning and tolerancing conform to JEDEC MO-187-AA

and AMSEY14.5m-1994.

3. Plastic or metal protrusions of 0.15mm max per side are not

included.

(0.65)

4. Plastic interlead protrusions of 0.15mm max per side are not

included.

(0.40)

(1.40)

5. Dimensions are measured at Datum Plane "H".

6. Dimensions in ( ) are for reference only.

TYPICAL RECOMMENDED LAND PATTERN

FN8177 Rev 7.00

October 7, 2015

Page 10 of 12

X9313

Package Outline Drawing

M8.15

8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE

Rev 4, 1/12

DETAIL "A"

1.27 (0.050)

0.40 (0.016)

INDEX

AREA

6.20 (0.244)

5.80 (0.228)

0.50 (0.20)

x 45°

0.25 (0.01)

4.00 (0.157)

3.80 (0.150)

8°

0°

1

2

3

0.25 (0.010)

0.19 (0.008)

SIDE VIEW “B”

TOP VIEW

2.20 (0.087)

1

8

SEATING PLANE

0.60 (0.023)

1.27 (0.050)

1.75 (0.069)

5.00 (0.197)

4.80 (0.189)

2

3

7

6

1.35 (0.053)

-C-

4

5

0.25(0.010)

0.10(0.004)

1.27 (0.050)

0.51(0.020)

0.33(0.013)

5.20(0.205)

SIDE VIEW “A

TYPICAL RECOMMENDED LAND PATTERN

NOTES:

1. Dimensioning and tolerancing per ANSI Y14.5M-1994.

2. Package length does not include mold flash, protrusions or gate burrs.

Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006

inch) per side.

3. Package width does not include interlead flash or protrusions. Interlead

flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.

4. The chamfer on the body is optional. If it is not present, a visual index

feature must be located within the crosshatched area.

5. Terminal numbers are shown for reference only.

6. The lead width as measured 0.36mm (0.014 inch) or greater above the

seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch).

7. Controlling dimension: MILLIMETER. Converted inch dimensions are not

necessarily exact.

8. This outline conforms to JEDEC publication MS-012-AA ISSUE C.

FN8177 Rev 7.00

October 7, 2015

Page 11 of 12

X9313

Plastic Dual-In-Line Packages (PDIP)

E

N

1

D

PIN #1

INDEX

A2

A

E1

SEATING

PLANE

L

c

A1

NOTE 5

2

N/2

eA

eB

e

b

b2

MDP0031

PLASTIC DUAL-IN-LINE PACKAGE

INCHES

SYMBOL

PDIP8

0.210

0.015

0.130

0.018

0.060

0.010

0.375

0.310

0.250

0.100

0.300

0.345

0.125

8

PDIP14

0.210

0.015

0.130

0.018

0.060

0.010

0.750

0.310

0.250

0.100

0.300

0.345

0.125

14

PDIP16

0.210

0.015

0.130

0.018

0.060

0.010

0.750

0.310

0.250

0.100

0.300

0.345

0.125

16

PDIP18

PDIP20

0.210

0.015

0.130

0.018

0.060

0.010

1.020

0.310

0.250

0.100

0.300

0.345

0.125

20

TOLERANCE

MAX

NOTES

A

A1

A2

b

0.210

0.015

0.130

0.018

0.060

0.010

0.890

0.310

0.250

0.100

0.300

0.345

0.125

18

MIN

±0.005

±0.002

b2

c

+0.010/-0.015

+0.004/-0.002

±0.010

D

1

2

E

+0.015/-0.010

±0.005

E1

e

Basic

eA

eB

L

Basic

±0.025

±0.010

N

Reference

Rev. C 2/07

NOTES:

1. Plastic or metal protrusions of 0.010” maximum per side are not included.

2. Plastic interlead protrusions of 0.010” maximum per side are not included.

3. Dimensions E and eA are measured with the leads constrained perpendicular to the seating plane.

4. Dimension eB is measured with the lead tips unconstrained.

5. 8 and 16 lead packages have half end-leads as shown.

All trademarks and registered trademarks are the property of their respective owners.

For additional products, see www.intersil.com/en/products.html

Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted

in the quality certifications found at www.intersil.com/en/support/qualandreliability.html

Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such

modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are

current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its

subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or

otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN8177 Rev 7.00

October 7, 2015

Page 12 of 12

型号:	X9313ZSIZT1
Brand Name：	Intersil
生命周期：	Unknown
IHS 制造商：	INTERSIL CORP
零件包装代码：	MSOP, PDIP, SOIC
包装说明：	SOP, SOP8,.25
针数：	8, 8, 8
Reach Compliance Code：	compliant
ECCN代码：	EAR99
HTS代码：	8542.39.00.01
Factory Lead Time：	9 weeks
风险等级：	5.11
Is Samacsys：	N
其他特性：	NONVOLATILE MEMORY
控制接口：	INCREMENT/DECREMENT
转换器类型：	DIGITAL POTENTIOMETER
JESD-30 代码：	R-PDSO-G8
JESD-609代码：	e3
长度：	4.9 mm
湿度敏感等级：	1
功能数量：	1
位置数：	32
端子数量：	8
最高工作温度：	85 °C
最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY
封装代码：	SOP
封装等效代码：	SOP8,.25
封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE
峰值回流温度（摄氏度）：	260
电源：	5 V
认证状态：	Not Qualified
电阻定律：	LINEAR
最大电阻容差：	20%
最大电阻器端电压：	5 V
最小电阻器端电压：	-5 V
座面最大高度：	1.75 mm
子类别：	Digital Potentiometers
标称供电电压：	5 V
表面贴装：	YES
技术：	CMOS
标称温度系数：	300 ppm/ °C
温度等级：	INDUSTRIAL
端子面层：	Matte Tin (Sn) - annealed
端子形式：	GULL WING
端子节距：	1.27 mm
端子位置：	DUAL
处于峰值回流温度下的最长时间：	30
标称总电阻：	1000 Ω
宽度：	3.9 mm
Base Number Matches：	1

电子百科

产品导航

产品型号X9313ZSIZT1的概述

产品型号X9313ZSIZT1的Datasheet PDF文件预览

X9313ZSIZT1相关产品

X9313ZSIZT1相关文章

IC37:专业IC行业平台