XC18V02PC44C全新原装原理图各脚功能电路原理芯片引脚定义-中国IC网-芯三七

0

XC18V00 Series In-System

Programmable Configuration

PROMs

R

0

DS026 (v4.0) June 11, 2003

Product Specification

•

Dual configuration modes

Features

-

Serial Slow/Fast configuration (up to 33 MHz)

Parallel (up to 264 Mb/s at 33 MHz)

•

In-system programmable 3.3V PROMs for

configuration of Xilinx FPGAs

-

Endurance of 20,000 program/erase cycles

•

5V tolerant I/O pins accept 5V, 3.3V and 2.5V signals

3.3V or 2.5V output capability

Program/erase over full commercial/industrial

voltage and temperature range (–40°C to +85°C)

Available in PC20, SO20, PC44, and VQ44 packages

•

IEEE Std 1149.1 boundary-scan (JTAG) support

Simple interface to the FPGA

Design support using the Xilinx Alliance and

Foundation series software packages.

Cascadable for storing longer or multiple bitstreams

Low-power advanced CMOS FLASH process

•

JTAG command initiation of standard FPGA

configuration

When the FPGA is in Master-SelectMAP mode, the FPGA

generates a configuration clock that drives the PROM.

When the FPGA is in Slave-Parallel or Slave-SelectMAP

Mode, an external oscillator generates the configuration

clock that drives the PROM and the FPGA. After CE and

OE are enabled, data is available on the PROMs DATA

(D0-D7) pins. New data is available a short access time

after each rising clock edge. The data is clocked into the

FPGA on the following rising edge of the CCLK. A free-run-

ning oscillator can be used in the Slave-Parallel or

Slave-SelecMAP modes.

Description

Xilinx introduces the XC18V00 series of in-system program-

mable configuration PROMs (Figure 1). Devices in this 3.3V

family include a 4-megabit, a 2-megabit, a 1-megabit, and a

512-kilobit PROM that provide an easy-to-use, cost-effec-

tive method for re-programming and storing Xilinx FPGA

configuration bitstreams.

When the FPGA is in Master Serial mode, it generates a

configuration clock that drives the PROM. A short access

time after CE and OE are enabled, data is available on the

Multiple devices can be concatenated by using the CEO

output to drive the CE input of the following device. The

clock inputs and the DATA outputs of all PROMs in this

chain are interconnected. All devices are compatible and

can be cascaded with other members of the family or with

the XC17V00 one-time programmable Serial PROM family.

PROM DATA (D0) pin that is connected to the FPGA D

IN

pin. New data is available a short access time after each ris-

ing clock edge. The FPGA generates the appropriate num-

ber of clock pulses to complete the configuration. When the

FPGA is in Slave Serial mode, the PROM and the FPGA

are clocked by an external clock.

CLK CE

OE/Reset

TCK

Data

Control

CEO

Serial

or

Parallel

Interface

TMS

TDI

and

JTAG

Interface

Memory

D0 DATA

Serial or Parallel Mode

Data

Address

TDO

7

D[1:7]

Parallel Interface

CF

DS026_01_090502

Figure 1: XC18V00 Series Block Diagram

trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.

NOTICE OF DISCLAIMER: Xilinx is providing this design, code, or information "as is." By providing the design, code, or information as one possible implementation of this fea-

ture, application, or standard, Xilinx makes no representation that this implementation is free from any claims of infringement. You are responsible for obtaining any rights you

may require for your implementation. Xilinx expressly disclaims any warranty whatsoever with respect to the adequacy of the implementation, including but not limited to any war-

ranties or representations that this implementation is free from claims of infringement and any implied warranties of merchantability or fitness for a particular purpose.

DS026 (v4.0) June 11, 2003

www.xilinx.com

1

Product Specification

1-800-255-7778

R

XC18V00 Series In-System Programmable Configuration PROMs

Pinout and Pin Description

Table 1 provides a list of the pin names and descriptions for the 44-pin VQFP and PLCC and the 20-pin SOIC and PLCC

packages.

Table 1: Pin Names and Descriptions

Boundary

Scan

Order

20-pin

SOIC &

PLCC

Name

44-pin

VQFP

44-pin

PLCC

Function

Pin Description

D0

D1

D2

D3

D4

D5

D6

D7

CLK

4

3

DATA OUT D0 is the DATA output pin to provide data

40

29

42

27

9

2

1

for configuring an FPGA in serial mode.

OUTPUT

ENABLE

6

5

DATA OUT D0-D7 are the output pins to provide

parallel data for configuring a Xilinx

35

4

16

2

OUTPUT

ENABLE

FPGA in Slave-Parallel/SelectMap mode.

D1-D7 remain in HIGHZ state when the

PROM operates in serial mode.

2

1

DATA OUT

D1-D7 can be left unconnected when the

PROM is used in serial mode.

OUTPUT

ENABLE

8

7

DATA OUT

33

15

31

20

25

15

OUTPUT

ENABLE

(1)

24

23

DATA OUT

7

OUTPUT

ENABLE

10

9

DATA OUT

25

14

19

14

9

OUTPUT

ENABLE

17

16

DATA OUT

OUTPUT

ENABLE

14

13

DATA OUT

12

OUTPUT

ENABLE

0

DATA IN

Each rising edge on the CLK input

increments the internal address counter if

both CE is Low and OE/RESET is High.

43

13

5

3

8

OE/

RESET

20

19

18

DATA IN

When Low, this input holds the address

counter reset and the DATA output is in a

high-impedance state. This is a

19

DATA OUT

bidirectional open-drain pin that is held

Low while the PROM is reset. Polarity is

NOT programmable.

OUTPUT

ENABLE

CE

15

DATA IN

When CE is High, the device is put into

low-power standby mode, the address

counter is reset, and the DATA pins are

put in a high-impedance state.

15

21

10

2

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DS026 (v4.0) June 11, 2003

1-800-255-7778

Product Specification

R

XC18V00 Series In-System Programmable Configuration PROMs

Table 1: Pin Names and Descriptions (Continued)

Boundary

20-pin

Name

Scan

Order

44-pin

VQFP

44-pin

PLCC

SOIC &

PLCC

Function

Pin Description

(1)

CF

22

21

DATA OUT Allows JTAG CONFIG instruction to

initiate FPGA configuration without

10

16

7

OUTPUT

powering down FPGA. This is an

ENABLE

open-drain output that is pulsed Low by

the JTAG CONFIG command.

CEO

12

11

DATA OUT Chip Enable Output (CEO) is connected

to the CE input of the next PROM in the

21

27

13

OUTPUT

chain. This output is Low when CE is Low

ENABLE

and OE/RESET input is High, AND the

internal address counter has been

incremented beyond its Terminal Count

(TC) value. CEO returns to High when

OE/RESET goes Low or CE goes High.

GND

TMS

GND is the ground connection.

6, 18, 28 &

41

3, 12, 24

& 34

11

5

MODE

SELECT

The state of TMS on the rising edge of

TCK determines the state transitions at

the Test Access Port (TAP) controller.

TMS has an internal 50K ohm resistive

pull-up on it to provide a logic “1” to the

device if the pin is not driven.

5

11

TCK

TDI

CLOCK

DATA IN

This pin is the JTAG test clock. It

sequences the TAP controller and all the

JTAG test and programming electronics.

7

3

13

9

6

4

This pin is the serial input to all JTAG

instruction and data registers. TDI has an

internal 50K ohm resistive pull-up on it to

provide a logic “1” to the system if the pin

is not driven.

TDO

DATA OUT This pin is the serial output for all JTAG

instruction and data registers. TDO has

an internal 50K ohm resistive pull-up on it

to provide a logic “1” to the system if the

pin is not driven.

31

37

17

(3)

V

Positive 3.3V supply voltage for internal

logic.

17, 35 &

38

23, 41 &

44

18 & 20

CCINT

(3)

V

Positive 3.3V or 2.5V supply voltage

connected to the input buffers and

8, 16, 26 & 14, 22, 32

19

CCO

(2)

36

& 42

output voltage drivers.

NC

No connects.

1, 2, 4,

1, 6, 7, 8,

11, 12, 20, 10,17, 18,

22, 23, 24, 26,28, 29,

30, 32, 33, 30,36, 38,

34, 37, 39, 39, 40, 43

44

Notes:

1. By default, pin 7 is the D4 pin in the 20-pin packages. However, CF --> D4 programming option can be set to override the default and route

the CF function to pin 7 in the Serial mode.

2. For devices with IDCODES 0502x093h, the input buffers are supplied by V

.

CCINT

3. For devices with IDCODES, 0503x093h, these V

pins are no connects: pin 38 in 44-pin VQFP package, pin 44 in 44-pin PLCC

CCINT

package and pin 20 in 20-pin SOIC and20-pin PLCC packages.

DS026 (v4.0) June 11, 2003

Product Specification

www.xilinx.com

1-800-255-7778

3

R

XC18V00 Series In-System Programmable Configuration PROMs

Pinout Diagrams

20

19

18

17

16

15

14

13

12

11

1

2

3

4

5

6

7

8

DATA(D0)

D2

VCCINT*

VCCO

VCCINT*

TDO

D1

D3

D5

CEO

D7

GND

CLK

TDI

TMS

TCK

SO20

Top

CF/D4*

OE/RESET

D6

View

NC

TDI

7

8

9

NC

TDO

NC

D1

39

38

37

36

35

34

33

32

31

30

29

9

10

CE

NC

10

11

12

13

14

15

16

17

TMS

GND

TCK

PC44

Top View

*See pin descriptions.

GND

D3

DS026_14_060403

V

CCO

D4

CF

NC

CCO

D5

NC

18

17

16

15

14

VCCINT*

TDO

D1

D3

D5

TDI

TMS

TCK

4

5

6

7

8

PC20

Top View

*See pin descriptions.

D4/CF*

OE/RESET

DS026_12_060403

*See pin descriptions.

DS026_15_060403

NC

TDI

1

2

3

4

5

6

7

8

NC

TDO

NC

D1

33

32

31

30

29

28

27

26

25

24

23

NC

TMS

GND

TCK

VQ44

Top View

GND

D3

V

CCO

D4

CF

NC

CCO

9

10

11

D5

NC

*See pin descriptions.

DS026_13_060403

4

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1-800-255-7778

DS026 (v4.0) June 11, 2003

Product Specification

R

XC18V00 Series In-System Programmable Configuration PROMs

Xilinx FPGAs and Compatible PROMs

Table 2 provides a list of Xilinx FPGAs and compatible

PROMs.

Table 2: Xilinx FPGAs and Compatible PROMs

Configuration

Bits

XC18V00

Solution

Device

Table 2: Xilinx FPGAs and Compatible PROMs

XCV800

4,715,616

XC18V04 +

XC18V512

Configuration

Bits

XC18V00

Solution

Device

XC2VP2

XC2VP4

XC2VP7

XCV1000

6,127,744

XC18V04 +

XC18V02

1,305,440

3,006,560

4,485,472

XC18V02

XC18V04

XCV50E

XCV100E

XCV200E

XCV300E

XCV400E

XCV405E

XCV600E

XCV812E

XCV1000E

XCV1600E

XCV2000E

XCV2600E

XCV3200E

XC2S15

630,048

863,840

XC18V01

XC18V04 +

XC18V512

1,442,016

1,875,648

2,693,440

3,430,400

3,961,632

6,519,648

6,587,520

8,308,992

10,159,648

12,922,336

16,283,712

197,696

XC18V02

XC2VP20

XC2VP30

XC2VP40

XC2VP50

XC2VP70

8,214,624

11,364,608

15,563,264

19,021,472

25,604,096

2 of XC18V04

3 of XC18V04

4 of XC18V04

5 of XC18V04

XC18V02

XC18V04

6 of XC18V04 +

XC18V512

2 of XC18V04

3 of XC18V04

4 of XC18V04

XC18V512

XC18V01

XC2VP100

XC2VP125

33,645,312

42,782,208

8 of XC18V04 +

XC18V512

10 of XC18V04 +

XC18V01

XC2V40

XC2V80

360,096

635,296

XC18V512

XC18V01

XC18V02

XC18V04

XC2V250

XC2V500

XC2V1000

XC2V1500

1,697,184

2,761,888

4,082,592

5,659,296

XC2S30

336,768

XC2S50

559,200

XC2S100

XC2S150

XC2S200

XC2S50E

XC2S100E

XC2S150E

XC2S200E

XC2S300E

XC2S400E

XC2S600E

XC3S50

781,216

XC18V01

XC18V04

+ XC18V02

1,040,096

1,335,840

630,048

XC18V01

XC2V2000

XC2V3000

XC2V4000

XC2V6000

7,492,000

10,494,368

15,659,936

21,849,504

2 of XC18V04

3 of XC18V04

4 of XC18V04

XC18V02

XC18V01

863,840

XC18V01

5 of XC18V04 +

XC18V02

1,134,496

1,442,016

1,875,648

2,693,440

3,961,632

439,264

XC18V02

XC2V8000

XCV50

29,063,072

559,200

7 of XC18V04

XC18V01

XC18V02

XC18V04

XC18V02

XC18V04

XCV100

XCV150

XCV200

XCV300

XCV400

XCV600

781,216

XC18V04

1,040,096

1,335,840

1,751,808

2,546,048

3,607,968

XC18V512

XC18V01

XC3S200

XC3S400

XC3S1000

1,047,616

1,699,136

3,223,488

XC18V02

XC18V04

DS026 (v4.0) June 11, 2003

Product Specification

www.xilinx.com

1-800-255-7778

5

R

XC18V00 Series In-System Programmable Configuration PROMs

Table 2: Xilinx FPGAs and Compatible PROMs

protocol as shown in Figure 2. In-system programming

offers quick and efficient design iterations and eliminates

unnecessary package handling or socketing of devices.

The Xilinx development system provides the programming

data sequence using either Xilinx iMPACT software and a

download cable, a third-party JTAG development system, a

JTAG-compatible board tester, or a simple microprocessor

interface that emulates the JTAG instruction sequence. The

iMPACT software also outputs serial vector format (SVF)

files for use with any tools that accept SVF format and with

automatic test equipment.

Configuration

Bits

XC18V00

Solution

Device

XC3S1500

5,214,784

XC18V04 +

XC18V01

XC3S2000

XC3S4000

XC3S5000

7,673,024

11,316,864

13,271,936

2 of XC18V04

3 of XC18V04

3 of XC18V04 +

XC18V01

All outputs are held in a high-impedance state or held at

clamp levels during in-system programming.

Capacity

OE/RESET

Devices

XC18V04

XC18V02

XC18V01

XC18V512

Configuration Bits

The ISP programming algorithm requires issuance of a

reset that causes OE to go Low.

4,194,304

2,097,152

1,048,576

524,288

External Programming

Xilinx reprogrammable PROMs can also be programmed by

the Xilinx HW-130, Xilinx MultiPRO, or a third-party device

programmer. This provides the added flexibility of using

pre-programmed devices with an in-system programmable

option for future enhancements and design changes.

In-System Programming

In-System Programmable PROMs can be programmed

individually, or two or more can be daisy-chained together

and programmed in-system via the standard 4-pin JTAG

(a)

(b)

DS026_02_06/1103

Figure 2: In-System Programming Operation (a) Solder Device to PCB and (b) Program Using Download Cable

Reliability and Endurance

Design Security

Xilinx in-system programmable products provide a guaran-

teed endurance level of 20,000 in-system program/erase

cycles and a minimum data retention of 20 years. Each

device meets all functional, performance, and data reten-

tion specifications within this endurance limit.

The Xilinx in-system programmable PROM devices incor-

porate advanced data security features to fully protect the

programming data against unauthorized reading via JTAG.

Table 3 shows the security setting available.

6

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DS026 (v4.0) June 11, 2003

Product Specification

R

XC18V00 Series In-System Programmable Configuration PROMs

The read security bit can be set by the user to prevent the

internal programming pattern from being read or copied via

JTAG. When set, it allows device erase. Erasing the entire

device is the only way to reset the read security bit.

instruction scan sequence. In preparation for an instruction

scan sequence, the instruction register is parallel loaded

with a fixed instruction capture pattern. This pattern is

shifted out onto TDO (LSB first), while an instruction is

shifted into the instruction register from TDI. The detailed

composition of the instruction capture pattern is illustrated

in Figure 3.

Table 3: Data Security Options

Default = Reset

Set

The ISP Status field, IR(4), contains logic “1” if the device is

currently in ISP mode; otherwise, it contains logic “0”. The

Security field, IR(3), contains logic “1” if the device has been

programmed with the security option turned on; otherwise, it

contains logic “0”.

Read Allowed

Program/Erase Allowed

Verify Allowed

Read Inhibited via JTAG

Program/Erase Allowed

Verify Inhibited

IEEE 1149.1 Boundary-Scan (JTAG)

IR[7:5]

IR[4]

IR[3]

IR[2] IR[1:0]

0 1

The XC18V00 family is fully compliant with the IEEE Std.

1149.1 Boundary-Scan, also known as JTAG. A Test

Access Port (TAP) and registers are provided to support all

required boundary scan instructions, as well as many of the

optional instructions specified by IEEE Std. 1149.1. In addi-

tion, the JTAG interface is used to implement in-system pro-

gramming (ISP) to facilitate configuration, erasure, and

verification operations on the XC18V00 device.

TDI->

0 0 0

ISP

Security

0

->TDO

Status

Notes:

1. IR(1:0) = 01 is specified by IEEE Std. 1149.1

Figure 3: Instruction Register Values Loaded into IR as

Part of an Instruction Scan Sequence

Table 4 lists the required and optional boundary-scan

instructions supported in the XC18V00. Refer to the IEEE

Std. 1149.1 specification for a complete description of

boundary-scan architecture and the required and optional

instructions.

Boundary Scan Register

The boundary-scan register is used to control and observe

the state of the device pins during the EXTEST, SAM-

PLE/PRELOAD, and CLAMP instructions. Each output pin

on the XC18V00 has two register stages that contribute to

the boundary-scan register, while each input pin only has

one register stage.

Table 4: Boundary Scan Instructions

Boundary-Scan

Command

Binary

Code [7:0]

Description

For each output pin, the register stage nearest to TDI con-

trols and observes the output state, and the second stage

closest to TDO controls and observes the High-Z enable

state of the pin.

Required Instructions

BYPASS

11111111 Enables BYPASS

SAMPLE/

PRELOAD

00000001 Enables boundary-scan

SAMPLE/PRELOAD operation

For each input pin, the register stage controls and observes

the input state of the pin.

EXTEST

00000000 Enables boundary-scan

EXTEST operation

Identification Registers

Optional Instructions

The IDCODE is a fixed, vendor-assigned value that is used

to electrically identify the manufacturer and type of the

device being addressed. The IDCODE register is 32 bits

wide. The IDCODE register can be shifted out for examina-

tion by using the IDCODE instruction. The IDCODE is avail-

able to any other system component via JTAG.

CLAMP

11111010 Enables boundary-scan

CLAMP operation

HIGHZ

11111100 all outputs in high-impedance

state simultaneously

IDCODE

11111110 Enables shifting out

32-bit IDCODE

The IDCODE register has the following binary format:

vvvv:ffff:ffff:aaaa:aaaa:cccc:cccc:ccc1

where

USERCODE

11111101 Enables shifting out

32-bit USERCODE

XC18V00 Specific Instructions

v = the die version number

CONFIG

11101110 Initiates FPGA configuration

by pulsing CF pin Low once

f = the family code (50h for XC18V00 family)

a = the ISP PROM product ID (36h for the XC18V04)

c = the company code (49h for Xilinx)

Instruction Register

The Instruction Register (IR) for the XC18V00 is eight bits

wide and is connected between TDI and TDO during an

Note: The LSB of the IDCODE register is always read as

logic “1” as defined by IEEE Std. 1149.1.

DS026 (v4.0) June 11, 2003

Product Specification

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7

R

XC18V00 Series In-System Programmable Configuration PROMs

Table 5 lists the IDCODE register values for the XC18V00

devices.

the XC18V00 device. If the device is blank or was not

loaded during programming, the USERCODE register con-

tains FFFFFFFFh.

Table 5: IDCODES Assigned to XC18V00 Devices

XC18V00 TAP Characteristics

ISP-PROM

XC18V01

XC18V02

XC18V04

XC18V512

IDCODE

The XC18V00 family performs both in-system programming

and IEEE 1149.1 boundary-scan (JTAG) testing via a single

4-wire Test Access Port (TAP). This simplifies system

designs and allows standard Automatic Test Equipment to

perform both functions. The AC characteristics of the

XC18V00 TAP are described as follows.

05024093h or 05034093h

05025093h or 05035093h

05026093h or 05036093h

05023093h or 05033093h

TAP Timing

Figure 4 shows the timing relationships of the TAP signals.

These TAP timing characteristics are identical for both

boundary-scan and ISP operations.

The USERCODE instruction gives access to a 32-bit user

programmable scratch pad typically used to supply informa-

tion about the device’s programmed contents. By using the

USERCODE instruction, a user-programmable identifica-

tion code can be shifted out for examination. This code is

loaded into the USERCODE register during programming of

T

CKMIN1,2

TCK

TMS

T

MSS

MSH

T

DIH

DIS

TDI

T

DOV

TDO

DS026_04_032702

Figure 4: Test Access Port Timing

TAP AC Parameters

Table 6 shows the timing parameters for the TAP waveforms shown in Figure 4.

Table 6: Test Access Port Timing Parameters

Symbol

Parameter

TCK minimum clock period

Min

100

50

10

25

10

25

-

Max

Units

T

-

ns

CKMIN1

CKMIN2

T

TCK minimum clock period, Bypass Mode

TMS setup time

T

-

MSS

TMS hold time

-

MSH

T

TDI setup time

-

DIS

T

TDI hold time

-

DIH

T

TDO valid delay

25

DOV

8

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DS026 (v4.0) June 11, 2003

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Product Specification

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XC18V00 Series In-System Programmable Configuration PROMs

Connecting Configuration PROMs

Connecting the FPGA device with the configuration PROM

(see Figure 5 and Figure 6).

through a user control register in the XC18V00 device. This

control register is accessible through JTAG, and is set using

the “Parallel mode” setting on the Xilinx iMPACT software.

Serial output is the default configuration mode.

•

The DATA output(s) of the PROM(s) drives the D

input of the lead FPGA device.

IN

•

The Master FPGA CCLK output drives the CLK input(s)

of the PROM(s) (in Master-Serial and

Master Serial Mode Summary

The I/O and logic functions of the Configurable Logic Block

(CLB) and their associated interconnections are estab-

lished by a configuration program. The program is loaded

either automatically upon power up, or on command,

depending on the state of the three FPGA mode pins. In

Master Serial mode, the FPGA automatically loads the con-

figuration program from an external memory. Xilinx PROMs

are designed to accommodate the Master Serial mode.

Master-SelectMAP modes only).

•

The CEO output of a PROM drives the CE input of the

next PROM in a daisy chain (if any).

The OE/RESET pins of all PROMs are connected to

the INIT pins of all FPGA devices. This connection

assures that the PROM address counter is reset before

the start of any (re)configuration, even when a

reconfiguration is initiated by a V

glitch.

CCINT

Upon power-up or reconfiguration, an FPGA enters the Mas-

ter Serial mode whenever all three of the FPGA mode-select

pins are Low (M0=0, M1=0, M2=0). Data is read from the

PROM sequentially on a single data line. Synchronization is

provided by the rising edge of the temporary signal CCLK,

which is generated by the FPGA during configuration.

•

The PROM CE input can be driven from the DONE pin.

The CE input of the first (or only) PROM can be driven

by the DONE output of all target FPGA devices,

provided that DONE is not permanently grounded. CE

can also be permanently tied Low, but this keeps the

DATA output active and causes an unnecessary supply

current of 10 mA maximum.

Master Serial Mode provides a simple configuration inter-

face. Only a serial data line, a clock line, and two control

lines are required to configure an FPGA. Data from the

PROM is read sequentially, accessed via the internal

address and bit counters which are incremented on every

valid rising edge of CCLK. If the user-programmable,

Slave-Parallel/SelectMap mode is similar to slave serial

mode. The DATA is clocked out of the PROM one byte

per CCLK instead of one bit per CCLK cycle. See FPGA

data sheets for special configuration requirements.

dual-function D pin on the FPGA is used only for configu-

IN

Initiating FPGA Configuration

ration, it must still be held at a defined level during normal

operation. The Xilinx FPGA families take care of this auto-

matically with an on-chip pull-up resistor.

The XC18V00 devices incorporate a pin named CF that is

controllable through the JTAG CONFIG instruction. Execut-

ing the CONFIG instruction through JTAG pulses the CF

low once for 300-500 ns, which resets the FPGA and ini-

tiates configuration.

Cascading Configuration PROMs

For multiple FPGAs configured as a serial daisy-chain, or a

single FPGA requiring larger configuration memories in a

serial or SelectMAP configuration mode, cascaded PROMs

provide additional memory (Figure 5). Multiple XC18V00

devices can be concatenated by using the CEO output to

drive the CE input of the downstream device. The clock

inputs and the data outputs of all XC18V00 devices in the

chain are interconnected. After the last data from the first

PROM is read, the next clock signal to the PROM asserts its

CEO output Low and drives its DATA line to a high-imped-

ance state. The second PROM recognizes the Low level on

its CE input and enables its DATA output. See Figure 7.

The CF pin must be connected to the PROGRAM pin on the

FPGA(s) to use this feature.

The iMPACT software can also issue a JTAG CONFIG

command to initiate FPGA configuration through the “Load

FPGA” setting.

The 20-pin packages do not have a dedicated CF pin. For

20-pin packages, the CF --> D4 setting can be used to route

the CF pin function to pin 7 only if the parallel output mode

is not used.

Selecting Configuration Modes

The XC18V00 accommodates serial and parallel methods

of configuration. The configuration modes are selectable

After configuration is complete, address counters of all cas-

caded PROMs are reset if the PROM OE/RESET pin goes

Low or CE goes High.

DS026 (v4.0) June 11, 2003

Product Specification

www.xilinx.com

1-800-255-7778

9

R

XC18V00 Series In-System Programmable Configuration PROMs

VCCO

(See Note 2)

VCCO VCCINT

(See Note 2)

VCCO VCCINT

(See Note 2)

4.7K

MODE PINS

(See Note 1)

MODE PINS

(See Note 1)

DIN

DOUT

VCCINT

VCCO

D0

VCCINT

VCCO

D0

Xilinx

FPGA

Xilinx

FPGA

XC18V00

VCCO

(See

4.7K

Master

Serial

Slave

Serial

Cascaded

PROM

First

PROM

Note

1)

J1

1

TDI

CLK

CE

TDI

CLK

CE

CCLK

DONE

CCLK

TDI

2

3

4

TMS

DONE

TCK

CEO

TCK

CEO

TCK

TDO

OE/RESET

CF

OE/RESET

CF

INIT

PROGRAM

TDI

TDO

GND

TMS

TCK

TMS

TCK

TDO

Notes:

1

2

For Mode pin connections and DONE pin pullup value, refer to appropriate FPGA data sheet.

For compatible voltages, refer to the appropriate FPGA data sheet.

DS026_08_061003

Figure 5: Configuring Multiple Devices in Master/Slave Serial Mode

(2)

VCCO

(2)

VCCINT

(2)

VCCINT

VCCO

4.7K

(1)

MODE PINS

**D[0:7]

(3)

D[0:7]

(3)

D[0:7]

VCCINT

VCCO

D[0:7]

VCCINT

VCCO

Xilinx

Virtex-II

FPGA

Xilinx

Virtex-II

FPGA

(2)

VCCO

XC18V00

4.7K

Master

Serial/

SelectMAP

Slave

Serial/

SelectMAP

Cascaded

PROM

First

PROM

(1)

J1

1

TDI

CLK

CE

TDI

CLK

CCLK

TDI

2

3

4

TMS

CE

DONE

TCK

CEO

TCK

CEO

TCK

TDO

OE/RESET

CF

OE/RESET

CF

INIT

PROGRAM

TDI

TDO

GND

TMS

TCK

TMS

TCK

TDO

Notes:

1

2

3

For Mode pin connections and DONE pin pullup value, refer to the appropriate FPGA data sheet.

For compatible voltges, refer to the appropriate FPGA data sheet.

Master/Slave Serial Mode does not require D[1:7] to be connected.

DS026_09_051003

Figure 6: Configuring Multiple Virtex-II Devices with Identical Patterns in Master/Slave or Serial/SelectMAP Modes

10

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DS026 (v4.0) June 11, 2003

1-800-255-7778

Product Specification

R

XC18V00 Series In-System Programmable Configuration PROMs

OPTIONAL

Daisy-chained

FPGAs with

different

DOUT

configurations

FPGA

(2)

Vcco

OPTIONAL

Slave FPGAs

with identical

4.7K

(1)

configurations

Modes

(2)

VCCO

VCCINT

(2)

Vcco

VCCINT VCCO

(2)

Vcco

4.7K

VCCO

VCCINT

DATA

VCCINT VCCO

DATA

DIN

First

PROM

Cascaded

PROM

CCLK

CLK

CE

CLK

CE

CEO

DONE

INIT

OE/RESET

CF

OE/RESET

CF

PROGRAM

Notes:

1

2

For Mode pin connections and Done pullup value, refer to the appropriate FPGA data sheet.

For compatible voltages, refer to the appropriate FPGA data sheet.

(a) Master Serial Mode

(1)

I/O

(4)

VCCINT VCCO

(4)

External

Osc

VCCINT VCCO

(3)

CS

WRITE

(2)

Modes

1K

Vcco

1K

VIRTEX

Select MAP

(4)

Vcco

VCCINT VCCO

(4)

Vcco

NC

BUSY

4.7K

XC18Vxx

(2)

4.7K

CLK

CCLK

D[0:7]

DONE

INIT

8

PROGRAM

CEO

CF

CEO

CF

D[0:7]

CE

D[0:7]

CE

OE/RESET

Notes:

1

2

3

4

CS and WRITE must be either driven Low or pulled down externally. One option is shown.

For Mode pin connections and Done pullup value, refer to the appropriate FPGA data sheet.

External oscillator required for Virtex/Virtex-E SelectMAP or Virtex-II/Virtex-II Pro Slave-SelectMAP modes.

For compatible voltages, refer to the appropriate FPGA data sheet.

(b) Virtex/Virtex-E/Virtex-II/Virtex-II Pro SelectMAP Mode

(1)

I/O

(4)

(1)

External

Osc

VCCINT VCCO

I/O

1K

Vcco

(3)

CS

(2)

Modes

WRITE

1K

Spartan-II,

Spartan-IIE

(4)

Vcco

VCCINT VCCO

(4)

VCCINT

(4)

NC

BUSY

3.3K

XC18Vxx

(2)

4.7K

CLK

CCLK

D[0:7]

DONE

INIT

8

PROGRAM

D[0:7]

CE

CF

OE/RESET

Notes:

1

2

CS and WRITE must be pulled down to be used as I/O. One option is shown.

For Mode pin connections and Done pullup value and if Drive Done configuration option is not active, refer to

the appropriate FPGA data sheet.

3

External oscillator required for Spartan-II/Spartan-IIE Slave-Parallel modes.

4 For compatible voltages, refer to the appropriate FPGA data sheet.

(c) Spartan-II/Spartan-IIE Slave-Parallel Mode

DS026_05_060403

Figure 7: (a) Master Serial Mode (b) Virtex/Virtex-E/Virtex-II Pro SelectMAP Mode (c) Spartan-II/Spartan-IIE

Slave-Parallel Mode (dotted lines indicate optional connection)

DS026 (v4.0) June 11, 2003

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11

Product Specification

1-800-255-7778

R

XC18V00 Series In-System Programmable Configuration PROMs

Reset Activation

On power up, OE/RESET is held low until the XC18V00 is

active (1 ms). OE/RESET is connected to an external resis-

tor to pull OE/RESET HIGH releasing the FPGA INIT and

allowing configuration to begin. If the power drops below

2.0V, the PROM resets. OE/RESET polarity is not program-

mable. See Figure 8 for power-up requirements.

remains in a high-impedance state regardless of the state of

the OE input. JTAG pins TMS, TDI and TDO can be in a

high-impedance state or High. See Table 7.

5V Tolerant I/Os

The I/Os on each re-programmable PROM are fully 5V tol-

erant even through the core power supply is 3.3V. This

allows 5V CMOS signals to connect directly to the PROM

inputs without damage. In addition, the 3.3V V

supply can be applied before or after 5V signals are applied

to the I/Os. In mixed 5V/3.3V/2.5V systems, the user pins,

power

3.6V

CCINT

Recommended Operating Range

3.0V

Recommended

the core power supply (V

), and the output power sup-

CCINT

ply (V

) can have power applied in any order. This

Rise

V_CCINT

Time

CCO

makes the PROM devices immune to power supply

sequencing issues.

Customer Control Bits

0V

0ms 1ms

50ms

The XC18V00 PROMs have various control bits accessible

by the customer. These can be set after the array has been

programmed using “Skip User Array” in Xilinx iMPACT soft-

ware. The iMPACT software can set these bits to enable the

optional JTAG read security, parallel configuration mode, or

CF-->D4 pin function. See Table 7.

Time (ms)

ds026_10_061103

Figure 8: V

Power-Up Requirements

CCINT

Standby Mode

The PROM enters a low-power standby mode whenever

CE is asserted High. The address is reset. The output

Table 7: Truth Table for PROM Control Inputs

Control Inputs

Outputs

OE/RESET

CE

Internal Address

DATA

CEO

I

CC

(1)

High

Low

If address < TC : increment

Active

High-Z

High

Low

Active

Reduced

(1)

If address > TC : don’t change

Low

High

Low

High

Held reset

High-Z

High

Active

Standby

Notes:

1. TC = Terminal Count = highest address value. TC + 1 = address 0.

12

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DS026 (v4.0) June 11, 2003

Product Specification

R

XC18V00 Series In-System Programmable Configuration PROMs

Absolute Maximum Ratings^(1,2)

Symbol

Description

Supply voltage relative to GND

Value

–0.5 to +4.0

–0.5 to +5.5

–65 to +150

+220

Units

V

CCINT/ CCO

V

Input voltage with respect to GND

Voltage applied to High-Z output

Storage temperature (ambient)

Maximum soldering temperature (10s @ 1/16 in.)

Junction temperature

V

IN

V

TS

T

°C

STG

SOL

T

+125

J

Notes:

1. Maximum DC undershoot below GND must be limited to either 0.5V or 10 mA, whichever is easier to achieve. During transitions, the

device pins can undershoot to –2.0V or overshoot to +7.0V, provided this over- or undershoot lasts less then 10 ns and with the

forcing current being limited to 200 mA.

2. Stresses beyond those listed under Absolute Maximum Ratings might cause permanent damage to the device. These are stress

ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions

is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time might affect device reliability.

Recommended Operating Conditions

Symbol

Parameter

Min

3.0

2.3

0

Max

3.6

2.7

0.8

5.5

Units

V

Internal voltage supply

CCINT

V

Supply voltage for output drivers for 3.3V operation

Supply voltage for output drivers for 2.5V operation

Low-level input voltage

V

CCO

V

IL

V

High-level input voltage

2.0

0

V

IH

V

Output voltage

V

O

CCO

(1)

T

V

rise time from 0V to nominal voltage

CCINT

1

50

ms

C

VCC

T

Operating ambient temperature

–40°

85°

A

Notes:

1. At power up, the device requires the V

power supply to monotonically rise from 0V to nominal voltage within the specified

CCINT

V

rise time. If the power supply cannot meet this requirement, then the device might not perform power-on-reset properly. See

CCINT

Figure 8.

Quality and Reliability Characteristics

Symbol

Description

Min

20

Max

Units

Years

Cycles

Volts

T

Data retention

-

DR

N

Program/erase cycles (Endurance)

Electrostatic discharge (ESD)

20,000

2,000

PE

V

ESD

DS026 (v4.0) June 11, 2003

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13

Product Specification

1-800-255-7778

R

XC18V00 Series In-System Programmable Configuration PROMs

DC Characteristics Over Operating Conditions

Symbol

Parameter

Test Conditions

Min

2.4

Max

-

Units

V

High-level output voltage for 3.3V outputs

High-level output voltage for 2.5V outputs

Low-level output voltage for 3.3V outputs

Low-level output voltage for 2.5V outputs

Supply current, active mode

I

= –4 mA

= –500 µA

= 8 mA

OH

OL

90% V

-

V

CCO

V

-

0.4

25

10

100

V

OL

CC

= 500 µA

V

I

25 MHz

mA

µA

I

Supply current, standby mode

CCS

I

JTAG pins TMS, TDI, and TDO pull-up

current

V

MAX

CCINT =

ILJ

= GND

IN

I

Input leakage current

V

= Max

= GND or

–10

10

µA

IL

CCINT

IN

CCINT

I

Input and output High-Z leakage current

V

= Max

= GND or

IH

CCINT

IN

CCINT

C

Input capacitance

Output capacitance

V

= GND

IN

-

8

pF

IN

f = 1.0 MHz

C

V

= GND

14

OUT

f = 1.0 MHz

Notes:

1. Internal pull-up resistors guarantee valid logic levels at unconnected input pins. These pull-up resistors do not guarantee valid logic

levels when input pins are connected to other circuits.

14

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DS026 (v4.0) June 11, 2003

1-800-255-7778

Product Specification

R

XC18V00 Series In-System Programmable Configuration PROMs

AC Characteristics Over Operating Conditions for XC18V04 and XC18V02

CE

T

SCE

HCE

OE/RESET

CLK

T

HOE

T

HC

LC

T

CYC

T

DF

OE

T

CAC

OH

T

CE

DATA

T

OH

DS026_06_012000

Symbol

Description

Min

-

Max

Units

T

OE/RESET to data delay

CE to data delay

10

20

-

ns

OE

CE

-

T

CLK to data delay

-

CAC

T

Data hold from CE, OE/RESET, or CLK

0

OH

(2)

T

CE or OE/RESET to data float delay

-

25

-

DF

T

Clock periods

50

10

25

250

CYC

(3)

T

CLK Low time

-

LC

HC

(3)

T

CLK High time

-

(3)

T

CE setup time to CLK (guarantees proper counting)

CE High time (guarantees counters are reset)

-

SCE

HCE

HOE

-

T

OE/RESET hold time (guarantees counters are reset)

-

Notes:

1. AC test load = 50 pF.

2. Float delays are measured with 5 pF AC loads. Transition is measured at 200 mV from steady state active levels.

3. Guaranteed by design, not tested.

4. All AC parameters are measured with V = 0.0V and V = 3.0V.

IL

IH

5. If T

6. If T

High < 2 µs, T = 2 µs.

HCE

CE

Low < 2 µs, T = 2 µs.

OE

DS026 (v4.0) June 11, 2003

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15

Product Specification

1-800-255-7778

R

XC18V00 Series In-System Programmable Configuration PROMs

AC Characteristics Over Operating Conditions for XC18V01 and XC18V512

CE

T

SCE

HCE

OE/RESET

CLK

T

HOE

T

HC

LC

T

CYC

T

DF

OE

T

CAC

OH

T

CE

DATA

T

OH

DS026_06_012000

Symbol

Description

Min

-

Max

Units

T

OE/RESET to data delay

CE to data delay

10

15

-

ns

OE

CE

-

T

CLK to data delay

-

CAC

T

Data hold from CE, OE/RESET, or CLK

0

OH

(2)

T

CE or OE/RESET to data float delay

-

25

-

DF

T

Clock periods

30

10

20

250

CYC

(3)

T

CLK Low time

-

LC

HC

(3)

T

CLK High time

-

(3)

T

CE setup time to CLK (guarantees proper counting)

CE High time (guarantees counters are reset)

-

SCE

HCE

HOE

-

T

OE/RESET hold time (guarantees counters are reset)

-

Notes:

1. AC test load = 50 pF.

2. Float delays are measured with 5 pF AC loads. Transition is measured at 200 mV from steady state active levels.

3. Guaranteed by design, not tested.

4. All AC parameters are measured with V = 0.0V and V = 3.0V.

IL

IH

5. If T

6. If T

High < 2 µs, T = 2 µs.

HCE

HOE

CE

High < 2 µs, T = 2 µs.

OE

16

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DS026 (v4.0) June 11, 2003

1-800-255-7778

Product Specification

R

XC18V00 Series In-System Programmable Configuration PROMs

AC Characteristics Over Operating Conditions When Cascading for XC18V04 and

XC18V02

OE/RESET

CE

CLK

T

CDF

T

OCE

Last Bit

First Bit

DATA

CEO

T

OCK

OOE

DS026_07_020300

Symbol

Description

Min

Max

25

Units

ns

(2,3)

T

CLK to data float delay

-

CDF

OCK

OCE

OOE

(3)

T

CLK to CEO delay

20

ns

(3)

CE to CEO delay

20

ns

(3)

T

OE/RESET to CEO delay

20

ns

Notes:

1. AC test load = 50 pF.

2. Float delays are measured with 5 pF AC loads. Transition is measured at 200 mV from steady state active levels.

3. Guaranteed by design, not tested.

4. All AC parameters are measured with V = 0.0V and V = 3.0V.

IL

IH

DS026 (v4.0) June 11, 2003

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17

Product Specification

1-800-255-7778

R

XC18V00 Series In-System Programmable Configuration PROMs

AC Characteristics Over Operating Conditions When Cascading for XC18V01 and

XC18V512

OE/RESET

CE

CLK

T

CDF

T

OCE

Last Bit

First Bit

DATA

CEO

T

OCK

OOE

DS026_07_020300

Symbol

Description

Min

Max

25

Units

ns

(2,3)

T

CLK to data float delay

-

CDF

OCK

OCE

OOE

(3)

T

CLK to CEO delay

20

ns

(3)

CE to CEO delay

20

ns

(3)

T

OE/RESET to CEO delay

20

ns

Notes:

1. AC test load = 50 pF.

2. Float delays are measured with 5 pF AC loads. Transition is measured at 200 mV from steady state active levels.

3. Guaranteed by design, not tested.

4. All AC parameters are measured with V = 0.0V and V = 3.0V.

IL

IH

18

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DS026 (v4.0) June 11, 2003

1-800-255-7778

Product Specification

R

XC18V00 Series In-System Programmable Configuration PROMs

Ordering Information

XC18V04 VQ44 C

Device Number

Operating Range/Processing

XC18V04

C = (T = –40°C to +85°C)

A

Package Type

XC18V02

XC18V01

XC18V512

VQ44 = 44-pin Plastic Quad Flat Package

PC44 = 44-pin Plastic Chip Carrier

SO20 = 20-pin Small-Outline Package

PC20 = 20-pin Plastic Leaded Chip Carrier

(1)

(2)

Notes:

1. XC18V04 and XC18V02 only.

2. XC18V01 and XC18V512 only.

Valid Ordering Combinations

XC18V04VQ44C

XC18V04PC44C

XC18V02VQ44C

XC18V02PC44C

XC18V01VQ44C

XC18V01PC20C

XC18V01SO20C

XC18V512VQ44C

XC18V512PC20C

XC18V512SO20C

Marking Information

44-pin Package

XC18V04 VQ44

Device Number

Operating Range/Processing

XC18V04

C = (T = –40°C to +85°C)

A

Package Type

XC18V02

XC18V01

XC18V512

VQ44 = 44-pin Plastic Quad Flat Package

PC44 = 44-pin Plastic Leaded Chip Carrier

(1)

Notes:

1. XC18V02 and XC18V04 only.

(1)

20-pin Package

Due to the small size of the serial PROM packages, the complete ordering part number cannot be marked on the

package. The XC prefix is deleted and the package code is simplified. Device marking is as follows:

18V01 S C

Device Number

Operating Range/Processing

18V01

18V512

C = (T = –40°C to +85°C)

A

Package Type

S = 20-pin Small-Outline Package

J = 20-pin Plastic Leaded Chip Carrier

Notes:

1. XC18V01 and XC18V512 only.

DS026 (v4.0) June 11, 2003

Product Specification

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1-800-255-7778

19

R

XC18V00 Series In-System Programmable Configuration PROMs

Revision History

The following table shows the revision history for this document.

Date

2/9/99

8/23/99

9/1/99

9/16/99

Version

1.0

Revision

First publication of this early access specification

Edited text, changed marking, added CF and parallel load

Corrected JTAG order, Security and Endurance data.

1.1

1.2

1.3

Corrected SelectMAP diagram, control inputs, reset polarity. Added JTAG and CF

description, 256 Kbit and 128 Kbit devices.

01/20/00

02/18/00

04/04/00

2.0

2.1

2.2

Added Q44 Package, changed XC18xx to XC18Vxx

Updated JTAG configuration, AC and DC characteristics

Removed stand alone resistor on INIT pin in Figure 5. Added Virtex-E and EM parts to

FPGA table.

06/29/00

11/13/00

2.3

2.4

Removed XC18V128 and updated format. Added AC characteristics for XC18V01,

XC18V512, and XC18V256 densities.

Features: changed 264 MHz to 264 Mb/s at 33 MHz; AC Spec.: T

units to ns, T

HCE

SCE

CE High time units to µs. Removed Standby Mode statement: “The lower power standby

modes available on some XC18V00 devices are set by the user in the programming

software”. Changed 10,000 cycles endurance to 20,000 cycles.

01/15/01

04/04/01

04/30/01

2.5

2.6

2.7

Updated Figures 5 and 6, added 4.7 resistors. Identification registers: changes ISP

PROM product ID from 06h to 26h.

Updated Figure 6, Virtex SelectMAP mode; added XC2V products to Compatible PROM

table; changed Endurance from 10,000 cycles, 10 years to 20,000, 20 years;

Updated Figure 6: removed Virtex-E in Note 2, fixed SelectMAP mode connections.

Under AC Characteristics Over Operating Conditions for XC18V04 and XC18V02,

changed T

from 25 ms to 25 ns.

SCE

06/11/01

09/28/01

2.8

2.9

AC Characteristics Over Operating Conditions for XC18V01 and XC18V512.

Changed Min values for T from 20 ms to 20 ns and for T from 2 ms to 2 µs.

SCE

HCE

Changed the boundary scan order for the CEO pin in Table 1, updated the configuration

bits values in the table under Xilinx FPGAs and Compatible PROMs, and added

information to the Recommended Operating Conditions table.

11/12/01

12/06/01

02/27/02

03/15/02

03/27/02

06/14/02

07/24/02

09/06/02

3.0

3.1

3.2

3.3

3.4

3.5

3.6

3.7

Updated for Spartan-IIE FPGA family.

Changed Figure 7(c).

Updated Table 2 and Figure 6 for the Virtex-II Pro family of devices.

Updated Xilinx software and modified Figure 6 and Figure 7.

Made changes to pages 1-3, 5, 7-11, 13, 14, and 18. Added new Figure 8 and Figure 9.

Made additions and changes to Table 2.

Changed last bullet under Connecting Configuration PROMs, page 9.

Multiple minor changes throughout, plus the addition of Pinout Diagrams, page 4 and

the deletion of Figure 9.

10/31/02

3.8

Made minor change on Figure 7 (b) and changed orientation of SO20 diagram on page 5.

20

www.xilinx.com

DS026 (v4.0) June 11, 2003

1-800-255-7778

Product Specification

R

XC18V00 Series In-System Programmable Configuration PROMs

11/18/02

04/17/03

06/11/03

3.9

3.10

4.0

Added XC2S400E and XC2S600E to Table 2.

Changes to Description, External Programming, and Table 2.

Added alternate IDCODES to Table 5, discontinued XC18V256 density, eliminated

industrial ordering combinations, extended commercial temperature range, and added

MultiPRO Desktop Tool support. Changed T

and T

to 250 ns in the tables on

HOE

HCE

page 15 and page 16. Made change in capacitance values DC Characteristics Over

Operating Conditions. Added Note 3 to Table 1. Other minor edits.

DS026 (v4.0) June 11, 2003

www.xilinx.com

21

Product Specification

1-800-255-7778

型号:	XC18V02PC44C
是否无铅：	含铅
是否Rohs认证：	不符合
生命周期：	Active
零件包装代码：	LCC
包装说明：	LCC-44
针数：	44
Reach Compliance Code：	not_compliant
ECCN代码：	EAR99
风险等级：	2.26
最长访问时间：	20 ns
最大时钟频率 (fCLK)：	20 MHz
数据保留时间-最小值：	20
耐久性：	20000 Write/Erase Cycles
JESD-30 代码：	S-PQCC-J44
JESD-609代码：	e0
长度：	16.5862 mm
内存密度：	2097152 bit
内存集成电路类型：	CONFIGURATION MEMORY
内存宽度：	8
湿度敏感等级：	3
功能数量：	1
端子数量：	44
字数：	262144 words
字数代码：	256000
工作模式：	SYNCHRONOUS
最高工作温度：	85 °C
最低工作温度：	-40 °C
组织：	256KX8
封装主体材料：	PLASTIC/EPOXY
封装代码：	QCCJ
封装等效代码：	LDCC44,.7SQ
封装形状：	SQUARE
封装形式：	CHIP CARRIER
并行/串行：	PARALLEL/SERIAL
峰值回流温度（摄氏度）：	225
电源：	2.5/3.3,3.3 V
认证状态：	Not Qualified
座面最大高度：	4.572 mm
最大待机电流：	0.01 A
子类别：	Flash Memories
最大压摆率：	0.025 mA
最大供电电压 (Vsup)：	3.6 V
最小供电电压 (Vsup)：	3 V
标称供电电压 (Vsup)：	3.3 V
表面贴装：	YES
技术：	CMOS
温度等级：	INDUSTRIAL
端子面层：	Tin/Lead (Sn85Pb15)
端子形式：	J BEND
端子节距：	1.27 mm
端子位置：	QUAD
处于峰值回流温度下的最长时间：	30
类型：	NOR TYPE
宽度：	16.5862 mm
Base Number Matches：	1

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