欢迎访问ic37.com |
会员登录 免费注册
发布采购
所在地: 型号: 精确
  • 批量询价
  •  
  • 供应商
  • 型号
  • 数量
  • 厂商
  • 封装
  • 批号
  • 交易说明
  • 询价
  •  
  • 北京元坤伟业科技有限公司

         该会员已使用本站17年以上

  • XC2C128-6VQG100C
  • 数量-
  • 厂家-
  • 封装-
  • 批号-
  • -
  • QQ:857273081QQ:857273081 复制
    QQ:1594462451QQ:1594462451 复制
  • 010-62104931、62106431、62104891、62104791 QQ:857273081QQ:1594462451
更多
  • XC2C128-6VQG100C图
  • 深圳市芯福林电子有限公司

     该会员已使用本站15年以上
  • XC2C128-6VQG100C 现货库存
  • 数量1600 
  • 厂家XILINX 
  • 封装TQFP100 
  • 批号新年份 
  • 真实库存全新原装正品!代理此型号!
  • QQ:2881495751QQ:2881495751 复制
  • 0755-88917743 QQ:2881495751
  • XC2C128-6VQG100C图
  • 集好芯城

     该会员已使用本站13年以上
  • XC2C128-6VQG100C 现货库存
  • 数量2378 
  • 厂家XILINX(赛灵思) 
  • 封装 
  • 批号22+ 
  • 原装原厂现货
  • QQ:3008092965QQ:3008092965 复制
    QQ:3008092965QQ:3008092965 复制
  • 0755-83239307 QQ:3008092965QQ:3008092965
  • XC2C128-6VQG100C图
  • 深圳市毅创腾电子科技有限公司

     该会员已使用本站16年以上
  • XC2C128-6VQG100C 现货库存
  • 数量720 
  • 厂家XILINX 
  • 封装QFP100 
  • 批号22+ 
  • 现货只做原装假一赔十!
  • QQ:2355507162QQ:2355507162 复制
    QQ:2355507165QQ:2355507165 复制
  • 86-755-83616256 QQ:2355507162QQ:2355507165
  • XC2C128-6VQG100C图
  • 深圳市宏捷佳电子科技有限公司

     该会员已使用本站12年以上
  • XC2C128-6VQG100C 现货库存
  • 数量50000 
  • 厂家XILINX 
  • 封装QFP100 
  • 批号2020+ 
  • 绝对房间进口原装现货
  • QQ:2885134398QQ:2885134398 复制
    QQ:2885134554QQ:2885134554 复制
  • 0755-22669259 QQ:2885134398QQ:2885134554
  • XC2C128-6VQG100C图
  • 深圳市芯脉实业有限公司

     该会员已使用本站11年以上
  • XC2C128-6VQG100C 现货库存
  • 数量5980 
  • 厂家XILINX 
  • 封装TQFP100 
  • 批号22+ 
  • 新到现货、一手货源、当天发货、bom配单
  • QQ:2881512844QQ:2881512844 复制
  • 075584507705 QQ:2881512844
  • XC2C128-6VQG100C图
  • 深圳市拓森弘电子有限公司

     该会员已使用本站1年以上
  • XC2C128-6VQG100C
  • 数量5300 
  • 厂家XILINX(赛灵思) 
  • 封装VQFP-100(14x14) 
  • 批号21+ 
  • 全新原装正品,库存现货实报
  • QQ:1300774727QQ:1300774727 复制
  • 13714410484 QQ:1300774727
  • XC2C128-6VQG100C图
  • 深圳市芯福林电子有限公司

     该会员已使用本站15年以上
  • XC2C128-6VQG100C
  • 数量65000 
  • 厂家XILINX(赛灵思) 
  • 封装VQFP-100(14x14) 
  • 批号23+ 
  • 真实库存全新原装正品!代理此型号
  • QQ:2881495753QQ:2881495753 复制
  • 0755-23605827 QQ:2881495753
  • XC2C128-6VQG100C图
  • 深圳市芯福林电子有限公司

     该会员已使用本站15年以上
  • XC2C128-6VQG100C
  • 数量56000 
  • 厂家XILINX 
  • 封装QFP100 
  • 批号23+ 
  • 真实库存全新原装正品!代理此型号
  • QQ:2881495751QQ:2881495751 复制
  • 0755-88917743 QQ:2881495751
  • XC2C128-6VQG100C图
  • 深圳市旺能芯科技有限公司

     该会员已使用本站4年以上
  • XC2C128-6VQG100C
  • 数量26000 
  • 厂家XILINX 
  • 封装TQFP100 
  • 批号22+ 
  • 深圳全新原装库存现货
  • QQ:2881495751QQ:2881495751 复制
  • 13602549709 QQ:2881495751
  • XC2C128-6VQG100C图
  • 深圳市龙腾新业科技有限公司

     该会员已使用本站17年以上
  • XC2C128-6VQG100C
  • 数量2378 
  • 厂家XILINX(赛灵思) 
  • 封装 
  • 批号24+ 
  • 原装原厂现货
  • QQ:562765057QQ:562765057 复制
    QQ:370820820QQ:370820820 复制
  • 0755-84509636 QQ:562765057QQ:370820820
  • XC2C128-6VQG100C图
  • 柒号芯城电子商务(深圳)有限公司

     该会员已使用本站13年以上
  • XC2C128-6VQG100C
  • 数量700000 
  • 厂家XILINX 
  • 封装VQFP-100(14X14) 
  • 批号2023+ 
  • 柒号芯城跟原厂的距离只有0.07公分
  • QQ:2881677436QQ:2881677436 复制
    QQ:2881620402QQ:2881620402 复制
  • 18922803401 QQ:2881677436QQ:2881620402
  • XC2C128-6VQG100C图
  • 深圳市羿芯诚电子有限公司

     该会员已使用本站7年以上
  • XC2C128-6VQG100C
  • 数量8800 
  • 厂家XILINX/赛灵思 
  • 封装QFP100 
  • 批号新年份 
  • 羿芯诚只做原装,原厂渠道,价格优势可谈!
  • QQ:2853992132QQ:2853992132 复制
  • 0755-82570683 QQ:2853992132
  • XC2C128-6VQG100C图
  • 深圳市羿芯诚电子有限公司

     该会员已使用本站7年以上
  • XC2C128-6VQG100C
  • 数量8500 
  • 厂家原厂品牌 
  • 封装原厂封装 
  • 批号新年份 
  • 羿芯诚只做原装长期供,支持实单
  • QQ:2880123150QQ:2880123150 复制
  • 0755-82570600 QQ:2880123150
  • XC2C128-6VQG100C图
  • 毅创腾(集团)有限公司

     该会员已使用本站16年以上
  • XC2C128-6VQG100C
  • 数量973 
  • 厂家XILINX 
  • 封装QFP100 
  • 批号22+ 
  • ★只做原装★正品现货★原盒原标★
  • QQ:2355507165QQ:2355507165 复制
    QQ:2355507168QQ:2355507168 复制
  • 86-755-83210801 QQ:2355507165QQ:2355507168
  • XC2C128-6VQG100C图
  • 深圳市和诚半导体有限公司

     该会员已使用本站11年以上
  • XC2C128-6VQG100C
  • 数量5600 
  • 厂家XILINX 
  • 封装TQFP100 
  • 批号23+ 
  • 只做原装正品,深圳现货
  • QQ:2276916927QQ:2276916927 复制
    QQ:1977615742QQ:1977615742 复制
  • 18929336553 QQ:2276916927QQ:1977615742
  • XC2C128-6VQG100C图
  • 深圳市得捷芯城科技有限公司

     该会员已使用本站11年以上
  • XC2C128-6VQG100C
  • 数量90 
  • 厂家XILINX(赛灵思) 
  • 封装VQFP-100(14x14) 
  • 批号23+ 
  • 优势代理渠道,原装正品,可全系列订货开增值税票
  • QQ:3007977934QQ:3007977934 复制
    QQ:3007947087QQ:3007947087 复制
  • 0755-82546830 QQ:3007977934QQ:3007947087
  • XC2C128-6VQG100C图
  • 北京耐芯威科技有限公司

     该会员已使用本站12年以上
  • XC2C128-6VQG100C
  • 数量5000 
  • 厂家Xilinx Inc. 
  • 封装100-VQFP(14x14) 
  • 批号21+ 
  • 全新原装、现货库存,欢迎询价
  • QQ:2880824479QQ:2880824479 复制
    QQ:1344056792QQ:1344056792 复制
  • 96-010-62104931 QQ:2880824479QQ:1344056792
  • XC2C128-6VQG100C图
  • 北京耐芯威科技有限公司

     该会员已使用本站13年以上
  • XC2C128-6VQG100C
  • 数量5000 
  • 厂家Xilinx Inc. 
  • 封装100-VQFP(14x14) 
  • 批号21+ 
  • 全新原装、现货库存,欢迎询价
  • QQ:2880824479QQ:2880824479 复制
    QQ:1344056792QQ:1344056792 复制
  • 86-010-010-62104931 QQ:2880824479QQ:1344056792
  • XC2C128-6VQG100C图
  • 深圳市晶美隆科技有限公司

     该会员已使用本站15年以上
  • XC2C128-6VQG100C
  • 数量6800 
  • 厂家XILINX/赛灵思 
  • 封装QFP 
  • 批号24+ 
  • 假一罚十,原装进口正品现货供应
  • QQ:198857245QQ:198857245 复制
  • 0755-82865294 QQ:198857245
  • XC2C128-6VQG100C图
  • 集好芯城

     该会员已使用本站13年以上
  • XC2C128-6VQG100C
  • 数量15884 
  • 厂家XILINX/赛灵思 
  • 封装QFP 
  • 批号最新批次 
  • 原装原厂 现货现卖
  • QQ:3008092965QQ:3008092965 复制
    QQ:3008092965QQ:3008092965 复制
  • 0755-83239307 QQ:3008092965QQ:3008092965
  • XC2C128-6VQG100C图
  • 深圳市宏捷佳电子科技有限公司

     该会员已使用本站6年以上
  • XC2C128-6VQG100C
  • 数量6500 
  • 厂家XILINX 
  • 封装QFP 
  • 批号24+ 
  • 全新原装★真实库存★含13点增值税票!
  • QQ:2885134615QQ:2885134615 复制
    QQ:2353549508QQ:2353549508 复制
  • 0755-83201583 QQ:2885134615QQ:2353549508
  • XC2C128-6VQG100C图
  • 深圳市宏捷佳电子科技有限公司

     该会员已使用本站12年以上
  • XC2C128-6VQG100C
  • 数量12300 
  • 厂家XILINX 
  • 封装TQFP100 
  • 批号24+ 
  • ★原装真实库存★13点税!
  • QQ:2353549508QQ:2353549508 复制
    QQ:2885134615QQ:2885134615 复制
  • 0755-83201583 QQ:2353549508QQ:2885134615
  • XC2C128-6VQG100C图
  • 深圳市得捷芯城科技有限公司

     该会员已使用本站11年以上
  • XC2C128-6VQG100C
  • 数量7548 
  • 厂家XILINX/赛灵思 
  • 封装TQFP100 
  • 批号23+ 
  • 原厂可订货,技术支持,直接渠道。可签保供合同
  • QQ:3007947087QQ:3007947087 复制
    QQ:3007947087QQ:3007947087 复制
  • 0755-83061789 QQ:3007947087QQ:3007947087
  • XC2C128-6VQG100C图
  • 深圳市恒益昌科技有限公司

     该会员已使用本站6年以上
  • XC2C128-6VQG100C
  • 数量4500 
  • 厂家XILINX 
  • 封装QFP100 
  • 批号23+ 
  • 原装正品长期供货
  • QQ:3336148967QQ:3336148967 复制
    QQ:974337758QQ:974337758 复制
  • 0755-82723761 QQ:3336148967QQ:974337758
  • XC2C128-6VQG100C图
  • 深圳市华斯顿电子科技有限公司

     该会员已使用本站16年以上
  • XC2C128-6VQG100C
  • 数量61699 
  • 厂家XILINX 
  • 封装QFP100 
  • 批号2023+ 
  • 绝对原装全新正品现货/优势渠道商、原盘原包原盒
  • QQ:364510898QQ:364510898 复制
    QQ:515102657QQ:515102657 复制
  • 0755-83777708“进口原装正品专供” QQ:364510898QQ:515102657
  • XC2C128-6VQG100C图
  • 深圳市西源信息科技有限公司

     该会员已使用本站9年以上
  • XC2C128-6VQG100C
  • 数量8800 
  • 厂家XILINX 
  • 封装VQFP-100(14x14) 
  • 批号最新批号 
  • 原装现货零成本有接受价格就出
  • QQ:3533288158QQ:3533288158 复制
    QQ:408391813QQ:408391813 复制
  • 0755-84876394 QQ:3533288158QQ:408391813
  • XC2C128-6VQG100C图
  • 北京齐天芯科技有限公司

     该会员已使用本站15年以上
  • XC2C128-6VQG100C
  • 数量5000 
  • 厂家Xilinx Inc. 
  • 封装100-VQFP(14x14) 
  • 批号2024+ 
  • 全新原装、现货库存,欢迎询价
  • QQ:2880824479QQ:2880824479 复制
    QQ:1344056792QQ:1344056792 复制
  • 010-62104931 QQ:2880824479QQ:1344056792
  • XC2C128-6VQG100C图
  • 深圳市恒达亿科技有限公司

     该会员已使用本站12年以上
  • XC2C128-6VQG100C
  • 数量405 
  • 厂家XILINX 
  • 封装TQFP100 
  • 批号23+ 
  • 原标原盒!只有原装!代理产品!
  • QQ:1245773710QQ:1245773710 复制
    QQ:867789136QQ:867789136 复制
  • 0755-82772189 QQ:1245773710QQ:867789136
  • XC2C128-6VQG100C图
  • 北京齐天芯科技有限公司

     该会员已使用本站15年以上
  • XC2C128-6VQG100C
  • 数量5000 
  • 厂家Xilinx Inc. 
  • 封装100-VQFP(14x14) 
  • 批号2024+ 
  • 全新原装、现货库存,欢迎询价
  • QQ:2880824479QQ:2880824479 复制
    QQ:1344056792QQ:1344056792 复制
  • 010-62104931 QQ:2880824479QQ:1344056792
  • XC2C128-6VQG100C图
  • 深圳市宏世佳电子科技有限公司

     该会员已使用本站13年以上
  • XC2C128-6VQG100C
  • 数量3785 
  • 厂家Xilinx 
  • 封装100-TQFP 
  • 批号2023+ 
  • 全新原厂原装产品、公司现货销售
  • QQ:2881894393QQ:2881894393 复制
    QQ:2881894392QQ:2881894392 复制
  • 0755- QQ:2881894393QQ:2881894392
  • XC2C128-6VQG100C图
  • 深圳市美思瑞电子科技有限公司

     该会员已使用本站12年以上
  • XC2C128-6VQG100C
  • 数量12245 
  • 厂家XILINX/赛灵思 
  • 封装QFP100 
  • 批号22+ 
  • 现货,原厂原装假一罚十!
  • QQ:2885659458QQ:2885659458 复制
    QQ:2885657384QQ:2885657384 复制
  • 0755-83952260 QQ:2885659458QQ:2885657384
  • XC2C128-6VQG100C图
  • 深圳市华芯盛世科技有限公司

     该会员已使用本站13年以上
  • XC2C128-6VQG100C
  • 数量865000 
  • 厂家XILINX/赛灵思 
  • 封装VQFP 
  • 批号最新批号 
  • 一级代理,原装特价现货!
  • QQ:2881475757QQ:2881475757 复制
  • 0755-83225692 QQ:2881475757
  • XC2C128-6VQG100C图
  • 深圳市金嘉锐电子有限公司

     该会员已使用本站14年以上
  • XC2C128-6VQG100C
  • 数量28620 
  • 厂家Xilinx 
  • 封装100-TQFP 
  • 批号24+ 
  • 【原装优势★★★绝对有货】
  • QQ:2643490444QQ:2643490444 复制
  • 0755-22929859 QQ:2643490444
  • XC2C128-6VQG100C图
  • 深圳市惊羽科技有限公司

     该会员已使用本站11年以上
  • XC2C128-6VQG100C
  • 数量2368 
  • 厂家XILINX-赛灵思 
  • 封装QFP-100 
  • 批号▉▉:2年内 
  • ▉▉¥81.4元一有问必回一有长期订货一备货HK仓库
  • QQ:43871025QQ:43871025 复制
  • 131-4700-5145---Q-微-恭-候---有-问-秒-回 QQ:43871025
  • XC2C128-6VQG100C图
  • 上海熠富电子科技有限公司

     该会员已使用本站15年以上
  • XC2C128-6VQG100C
  • 数量4500 
  • 厂家XILINX 
  • 封装N/A 
  • 批号2024 
  • 上海原装现货库存,欢迎查询!
  • QQ:2719079875QQ:2719079875 复制
    QQ:2300949663QQ:2300949663 复制
  • 15821228847 QQ:2719079875QQ:2300949663
  • XC2C128-6VQG100C图
  • 深圳市斌腾达科技有限公司

     该会员已使用本站9年以上
  • XC2C128-6VQG100C
  • 数量1686 
  • 厂家Xilinx 
  • 封装100-VQFP(14x14) 
  • 批号18+ 
  • 进口原装!长期供应!绝对优势价格(诚信经营
  • QQ:2881704051QQ:2881704051 复制
    QQ:2881704535QQ:2881704535 复制
  • 0755-82815082 QQ:2881704051QQ:2881704535
  • XC2C128-6VQG100C图
  • 深圳市宏世佳电子科技有限公司

     该会员已使用本站13年以上
  • XC2C128-6VQG100C
  • 数量3785 
  • 厂家Xilinx 
  • 封装100-TQFP 
  • 批号2023+ 
  • 全新原厂原装产品、公司现货销售
  • QQ:2881894393QQ:2881894393 复制
    QQ:2881894392QQ:2881894392 复制
  • 0755- QQ:2881894393QQ:2881894392
  • XC2C128-6VQG100C图
  • 深圳市富科达科技有限公司

     该会员已使用本站13年以上
  • XC2C128-6VQG100C
  • 数量22314 
  • 厂家XILINX/PBF 
  • 封装QFP 
  • 批号2020+ 
  • 绝对全新原装进口现货热卖,价格优势
  • QQ:1220223788QQ:1220223788 复制
    QQ:1327510916QQ:1327510916 复制
  • 86-0755-28767101 QQ:1220223788QQ:1327510916
  • XC2C128-6VQG100C图
  • 深圳市英德州科技有限公司

     该会员已使用本站2年以上
  • XC2C128-6VQG100C
  • 数量45200 
  • 厂家XILINX(赛灵思) 
  • 封装VQFP-100(14x14) 
  • 批号1年内 
  • 原厂渠道 正品保障 长期供应
  • QQ:2355734291QQ:2355734291 复制
  • -0755-88604592 QQ:2355734291
  • XC2C128-6VQG100C图
  • 昂富(深圳)电子科技有限公司

     该会员已使用本站4年以上
  • XC2C128-6VQG100C
  • 数量72282 
  • 厂家XILINX/赛灵思 
  • 封装NA 
  • 批号23+ 
  • 一站式BOM配单,短缺料找现货,怕受骗,就找昂富电子.
  • QQ:GTY82dX7
  • 0755-23611557【陈妙华 QQ:GTY82dX7
  • XC2C128-6VQG100C图
  • 深圳市宏世佳电子科技有限公司

     该会员已使用本站13年以上
  • XC2C128-6VQG100C
  • 数量3685 
  • 厂家XILINX 
  • 封装VQFP 
  • 批号2023+ 
  • 全新原厂原装产品、公司现货销售
  • QQ:2881894392QQ:2881894392 复制
    QQ:2881894393QQ:2881894393 复制
  • 0755- QQ:2881894392QQ:2881894393
  • XC2C128-6VQG100C图
  • 深圳市欧昇科技有限公司

     该会员已使用本站10年以上
  • XC2C128-6VQG100C
  • 数量9000 
  • 厂家XILINX 
  • 封装VQFP 
  • 批号2021+ 
  • 港瑞电子是实报/实单可以来谈价
  • QQ:2885514621QQ:2885514621 复制
    QQ:1017582752QQ:1017582752 复制
  • 0755-83237676 QQ:2885514621QQ:1017582752

产品型号XC2C128-6VQG100C的概述

XC2C128-6VQG100C 芯片概述 XC2C128-6VQG100C 是由赛灵思(Xilinx)公司生产的一款复杂可编程逻辑器件(CPLD),它属于赛灵思 CoolRunner-II 系列。该系列芯片特别适合于低功耗应用和低延迟逻辑处理。XC2C128 主要被用于需要灵活性与高集成度的场景,如消费电子、通信设备和工业控制等。CPLD 作为一种集成电路,可以提供可编程逻辑来实现不同的功能,极大地增强了设计工程师在硬件实现过程中的灵活性。 芯片详细参数 XC2C128-6VQG100C 的主要技术参数如下: - 逻辑单元数量:128 - 逻辑门数量:828 - 时钟频率:可达 100 MHz - 电源电压:1.5V(核心电源),3.3V(I/O 电源) - I/O 引脚数:100 个引脚 - 工作温度范围:-40°C 到 +100°C - 封装类型:VQG100 (很适合高密度的布...

产品型号XC2C128-6VQG100C的Datasheet PDF文件预览

0
R
CoolRunner-II CPLD Family  
0
0
DS090 (v3.1) September 11, 2008  
Product Specification  
-
-
SSTL2_1,SSTL3_1, and HSTL_1 on 128  
macrocell and denser devices  
Hot pluggable  
Features  
Optimized for 1.8V systems  
-
-
Industry’s fastest low power CPLD  
Densities from 32 to 512 macrocells  
PLA architecture  
-
-
Wide package availability including fine pitch:  
-
Superior pinout retention  
100% product term routability across function block  
Industry’s best 0.18 micron CMOS CPLD  
-
-
Optimized architecture for effective logic synthesis  
Multi-voltage I/O operation — 1.5V to 3.3V  
Chip Scale Package (CSP) BGA, Fine Line BGA,  
TQFP, PQFP, VQFP, and QFN packages  
Pb-free available for all packages  
Advanced system features  
-
Fastest in system programming  
1.8V ISP using IEEE 1532 (JTAG) interface  
-
·
Design entry/verification using Xilinx and industry  
standard CAE tools  
-
-
-
-
-
On-The-Fly Reconfiguration (OTF)  
IEEE1149.1 JTAG Boundary Scan Test  
Optional Schmitt trigger input (per pin)  
Multiple I/O banks on all devices  
Free software support for all densities using Xilinx®  
WebPACK™ tool  
Industry leading nonvolatile 0.18 micron CMOS  
process  
Unsurpassed low power management  
·
DataGATE external signal control  
-
Flexible clocking modes  
-
-
Guaranteed 1,000 program/erase cycles  
Guaranteed 20 year data retention  
·
·
·
Optional DualEDGE triggered registers  
Clock divider (÷ 2,4,6,8,10,12,14,16)  
CoolCLOCK  
Family Overview  
-
Global signal options with macrocell control  
Xilinx CoolRunner™-II CPLDs deliver the high speed and  
ease of use associated with the XC9500/XL/XV CPLD fam-  
ily with the extremely low power versatility of the XPLA3  
family in a single CPLD. This means that the exact same  
parts can be used for high-speed data communications/  
computing systems and leading edge portable products,  
with the added benefit of In System Programming. Low  
power consumption and high-speed operation are com-  
bined into a single family that is easy to use and cost effec-  
tive. Clocking techniques and other power saving features  
extend the users’ power budget. The design features are  
supported starting with Xilinx ISE® 4.1i WebPACK tool.  
Additional details can be found in Further Reading,  
page 14.  
·
Multiple global clocks with phase selection per  
macrocell  
Multiple global output enables  
Global set/reset  
·
·
-
-
Abundant product term clocks, output enables and  
set/resets  
Efficient control term clocks, output enables and  
set/resets for each macrocell and shared across  
function blocks  
Advanced design security  
Open-drain output option for Wired-OR and LED  
drive  
Optional bus-hold, 3-state or weak pullup on select  
I/O pins  
Optional configurable grounds on unused I/Os  
Mixed I/O voltages compatible with 1.5V, 1.8V,  
2.5V, and 3.3V logic levels on all parts  
-
-
-
Table 1 shows the macrocell capacity and key timing  
parameters for the CoolRunner-II CPLD family.  
-
-
Table 1: CoolRunner-II CPLD Family Parameters  
XC2C32A  
32  
XC2C64A  
64  
XC2C128  
128  
XC2C256  
256  
XC2C384  
384  
XC2C512  
512  
Macrocells  
Max I/O  
33  
64  
100  
184  
240  
270  
T
T
T
F
(ns)  
(ns)  
(ns)  
3.8  
4.6  
5.7  
5.7  
7.1  
7.1  
PD  
SU  
CO  
1.9  
2.0  
2.4  
2.4  
2.9  
2.6  
3.7  
3.9  
4.2  
4.5  
5.8  
5.8  
(MHz)  
323  
263  
244  
256  
217  
179  
SYSTEM1  
© 2002–2008 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.  
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.  
DS090 (v3.1) September 11, 2008  
www.xilinx.com  
1
Product Specification  
R
CoolRunner-II CPLD Family  
Table 2: CoolRunner-II CPLD DC Characteristics  
XC2C32A XC2C64A  
XC2C128  
XC2C256  
XC2C384  
XC2C512  
I
I
(μA), 0 MHz, 25°C (typical)  
16  
17  
5
19  
10  
21  
27  
23  
45  
25  
55  
CC  
(mA), 50 MHz, 70°C (max)  
2.5  
CC  
1. ICC is dynamic current.  
Table 2 shows key DC characteristics for the CoolRunner-II  
family.  
in CoolRunner-II CPLDs generates minimal heat, allowing  
the use of tiny packages during high-speed operation.  
Table 3 shows the CoolRunner-II CPLD package offering  
with corresponding I/O count. All packages are surface  
mount, with over half of them being ball-grid technologies.  
The ultra tiny packages permit maximum functional capacity  
in the smallest possible area. The CMOS technology used  
With the exception of the Pb-free QF packages, there are at  
least two densities present in each package with three in the  
VQ100 (100-pin 1.0mm QFP), TQ144 (144-pin 1.4mm  
QFP), and FT256 (256-ball 1.0mm spacing FLBGA). The  
FT256 is particularly important for slim dimensioned porta-  
ble products with mid- to high-density logic requirements.  
Table 3: CoolRunner-II CPLD Family Packages and I/O Count  
XC2C32A  
XC2C64A  
XC2C128  
XC2C256  
XC2C384 XC2C512  
(1)  
QFG32  
VQ44  
21  
33  
33  
-
-
33  
33  
37  
45  
45  
64  
64  
-
-
-
-
-
-
-
-
-
-
(1)  
VQG44  
-
-
-
(1)  
QFG48  
CP56  
-
-
-
-
33  
33  
-
-
-
-
-
(1)  
CPG56  
VQ100  
-
80  
80  
100  
100  
100  
100  
-
-
-
-
-
80  
80  
106  
106  
118  
118  
173  
173  
184  
184  
-
-
(1)  
VQG100  
CP132  
-
-
-
-
-
-
(1)  
(1)  
(1)  
CPG132  
TQ144  
-
-
-
-
-
-
118  
118  
173  
173  
212  
212  
240  
240  
-
TQG144  
PQ208  
-
-
-
-
-
173  
173  
212  
212  
270  
270  
PQG208  
FT256  
-
-
-
-
-
-
(1)  
FTG256  
FG324  
-
-
-
-
-
-
(1)  
FGG324  
Notes:  
-
-
-
-
1. The letter "G" as the third character indicates a Pb-free package.  
Table 4 details the distribution of advanced features across  
the CoolRunner-II CPLD family. The family has uniform  
basic features with advanced features included in densities  
where they are most useful. For example, it is very unlikely  
that four I/O banks are needed on 32 and 64 macrocell  
parts, but very likely they are for 384 and 512 macrocell  
parts. The I/O banks are groupings of I/O pins using any  
one of a subset of compatible voltage standards that share  
2
www.xilinx.com  
DS090 (v3.1) September 11, 2008  
Product Specification  
R
CoolRunner-II CPLD Family  
the same V  
level. (See Table 5 for a summary of  
CCIO  
CoolRunner-II CPLD I/O standards.)  
Table 4: CoolRunner-II CPLD Family Features  
XC2C32A XC2C64A XC2C128 XC2C256 XC2C384 XC2C512  
IEEE 1532  
I/O banks  
2
-
2
-
2
2
4
4
Clock division  
DualEDGE  
Registers  
DataGATE  
LVTTL  
-
-
LVCMOS33, 25,  
18, and 15  
(1)  
SSTL2_1  
SSTL3_1  
HSTL_1  
-
-
-
-
-
-
Configurable  
ground  
Quadruple data  
security  
Open drain outputs  
Hot plugging  
Schmitt Inputs  
1. LVCMOS15 requires the use of Schmitt-trigger inputs.  
industry’s highest pinout retention, under very broad design  
conditions. The architecture is explained in more detail with  
the discussion of the underlying FBs, logic and intercon-  
nect.  
Architecture Description  
CoolRunner-II CPLD is a highly uniform family of fast, low  
power CPLDs. The underlying architecture is a traditional  
CPLD architecture combining macrocells into Function  
Blocks (FBs) interconnected with a global routing matrix,  
the Xilinx Advanced Interconnect Matrix (AIM). The FBs use  
a Programmable Logic Array (PLA) configuration which  
allows all product terms to be routed and shared among any  
of the macrocells of the FB. Design software can efficiently  
synthesize and optimize logic that is subsequently fit to the  
FBs and connected with the ability to utilize a very high per-  
centage of device resources. Design changes are easily  
and automatically managed by the software, which exploits  
the 100% routability of the Programmable Logic Array within  
each FB. This extremely robust building block delivers the  
The design software automatically manages these device  
resources so that users can express their designs using  
completely generic constructs without knowledge of these  
architectural details. More advanced users can take advan-  
tage of these details to more thoroughly understand the  
software’s choices and direct its results.  
Figure 1 shows the high-level architecture whereby FBs  
attach to pins and interconnect to each other within the  
internal interconnect matrix. Each FB contains 16 macro-  
cells. The BSC path is the JTAG Boundary Scan Control  
DS090 (v3.1) September 11, 2008  
www.xilinx.com  
3
Product Specification  
R
CoolRunner-II CPLD Family  
path. The BSC and ISP block has the JTAG controller and  
In-System Programming Circuits.  
BSC Path  
Clock and Control Signals  
Function  
Block 1  
Function  
Block n  
MC1  
MC2  
MC1  
MC2  
I/O Pin  
I/O Pin  
I/O Pin  
I/O Pin  
16 FB  
16 FB  
16  
16  
PLA  
PLA  
AIM  
40  
40  
MC16  
MC16  
I/O Pin  
JTAG  
I/O Pin  
Direct Inputs  
Direct Inputs  
16  
16  
BSC and ISP  
DS090_01_121201  
Figure 1: CoolRunner-II CPLD Architecture  
flexible, and very robust when compared to fixed or cas-  
caded product term FBs.  
Function Block  
The CoolRunner-II CPLD FBs contain 16 macrocells, with  
40 entry sites for signals to arrive for logic creation and con-  
nection. The internal logic engine is a 56 product term PLA.  
All FBs, regardless of the number contained in the device,  
are identical. For a high-level view of the FB, see Figure 2.  
Classic CPLDs typically have a few product terms available  
for a high-speed path to a given macrocell. They rely on  
capturing unused p-terms from neighboring macrocells to  
expand their product term tally, when needed. The result of  
this architecture is a variable timing model and the possibil-  
ity of stranding unusable logic within the FB.  
MC1  
MC2  
The PLA is different — and better. First, any product term  
can be attached to any OR gate inside the FB macrocell(s).  
Second, any logic function can have as many p-terms as  
needed attached to it within the FB, to an upper limit of 56.  
Third, product terms can be re-used at multiple macrocell  
OR functions so that within a FB, a particular logical product  
need only be created once, but can be re-used up to 16  
times within the FB. Naturally, this plays well with the fitting  
software, which identifies product terms that can be shared.  
16  
40  
PLA  
Out  
To AIM  
The software places as many of those functions as it can  
into FBs, so it happens for free. There is no need to force  
macrocell functions to be adjacent or any other restriction  
save residing in the same FB, which is handled by the soft-  
ware. Functions need not share a common clock, common  
set/reset, or common output enable to take full advantage of  
the PLA. Also, every product term arrives with the same  
time delay incurred. There are no cascade time adders for  
putting more product terms in the FB. When the FB product  
term budget is reached, there is a small interconnect timing  
penalty to route signals to another FB to continue creating  
logic. Xilinx design software handles all this automatically.  
MC16  
3
Global Global  
Set/Reset Clocks  
DS090_02_101001  
Figure 2: CoolRunner-II CPLD Function Block  
At the high level, the product terms (p-terms) reside in a  
programmable logic array (PLA). This structure is extremely  
4
www.xilinx.com  
DS090 (v3.1) September 11, 2008  
Product Specification  
R
CoolRunner-II CPLD Family  
resets, and output enables. Each macrocell flip-flop is con-  
figurable for either single edge or DualEDGE clocking, pro-  
viding either double data rate capability or the ability to  
distribute a slower clock (thereby saving power). For single  
edge clocking or latching, either clock polarity can be  
selected per macrocell. CoolRunner-II CPLD macrocell  
details are shown in Figure 3. Note that in Figure 4, stan-  
dard logic symbols are used except the trapezoidal multi-  
plexers have input selection from statically programmed  
configuration select lines (not shown). Xilinx application  
note XAPP376 gives a detailed explanation of how logic is  
created in the CoolRunner-II CPLD family.  
Macrocell  
The CoolRunner-II CPLD macrocell is extremely efficient  
and streamlined for logic creation. Users can develop sum  
of product (SOP) logic expressions that comprise up to 40  
inputs and span 56 product terms within a single function  
block. The macrocell can further combine the SOP expres-  
sion into an XOR gate with another single p-term expres-  
sion. The resulting logic expression’s polarity is also  
selectable. As well, the logic function can be pure combina-  
torial or registered, with the storage element operating  
selectably as a D or T flip-flop, or transparent latch. Avail-  
able at each macrocell are independent selections of global,  
function block level or local p-term derived clocks, sets,  
From AIM  
40  
49 P-terms  
To PTA, PTB, PTC of  
other macrocells  
Direct Input  
from  
I/O Block  
4 P-terms  
Feedback  
to AIM  
CTC, CTR,  
CTS, CTE  
PTA  
PTB  
PTC  
PTA  
CTS  
GSR  
GND  
V
CC  
GND  
To I/O Block  
S
D/T  
CE  
Q
FIF  
Latch  
PLA OR Term  
PTC  
DualEDGE  
CK  
GCK0  
GCK1  
GCK2  
R
CTC  
PTC  
PTA  
CTR  
GSR  
GND  
DS090_03_121201  
Figure 3: CoolRunner-II CPLD Macrocell  
When configured as a D-type flip-flop, each macrocell has  
an optional clock enable signal permitting state hold while a  
clock runs freely. Note that Control Terms (CT) are available  
to be shared for key functions within the FB, and are gener-  
ally used whenever the exact same logic function would be  
repeatedly created at multiple macrocells. The CT product  
terms are available for FB clocking (CTC), FB asynchro-  
nous set (CTS), FB asynchronous reset (CTR), and FB out-  
put enable (CTE).  
tional functionality is retained for use as a buried logic node  
if needed. F is the maximum clock frequency to which  
a T flip-flop can reliably toggle.  
Toggle  
Advanced Interconnect Matrix (AIM)  
The Advanced Interconnect Matrix is a highly connected  
low power rapid switch. The AIM is directed by the software  
to deliver up to a set of 40 signals to each FB for the cre-  
ation of logic. Results from all FB macrocells, as well as, all  
pin inputs circulate back through the AIM for additional con-  
nection available to all other FBs as dictated by the design  
Any macrocell flip-flop can be configured as an input regis-  
ter or latch, which takes in the signal from the macrocell’s  
I/O pin, and directly drives the AIM. The macrocell combina-  
DS090 (v3.1) September 11, 2008  
www.xilinx.com  
5
Product Specification  
R
CoolRunner-II CPLD Family  
software. The AIM minimizes both propagation delay and  
power as it makes attachments to the various FBs.  
also available. Table 5 summarizes various supported volt-  
age standards associated with specific part capacities. All  
inputs and disabled outputs are voltage tolerant up to 3.3V.  
I/O Block  
The CoolRunner-II family supports SSTL2-1, SSTL3-1 and  
HSTL-1 high-speed I/O standards in the 128-macrocell and  
larger devices. Figure 4 details the I/O pin, where it is noted  
that the inputs requiring comparison to an external refer-  
ence voltage are available. These I/O standards all require  
I/O blocks are primarily transceivers. However, each I/O is  
either automatically compliant with standard voltage ranges  
or can be programmed to become so. See XAPP382 for  
detailed information on CoolRunner-II I/Os.  
V
pins for proper operation. The CoolRunner-II CPLD  
REF  
In addition to voltage levels, each input can selectively  
arrive through Schmitt-trigger inputs. This adds a small time  
delay, but substantially reduces noise on that input pin.  
Approximately 500 mV of hysteresis is added when  
Schmitt-trigger inputs are selected. All LVCMOS inputs can  
have hysteresis input. Hysteresis also allows easy genera-  
tion of external clock circuits. The Schmitt-trigger path is  
best seen in Figure 4. See Table 5 for Schmitt-trigger com-  
patibility with I/O standards.  
allows any I/O pin to act as a V  
layout engineer extra freedom when laying out the pins.  
However, if V pin placement is not done properly, addi-  
pin, granting the board  
REF  
REF  
tional V  
pins might be required, resulting in a loss of  
REF  
potential I/O pins or board re-work. See XAPP399 for  
details regarding V pins and their placement.  
REF  
V
has pin-range requirements that must be observed.  
REF  
The Xilinx software aids designers in remaining within the  
proper pin range.  
Outputs can be directly driven, 3-stated or open-drain con-  
figured. A choice of slow or fast slew rate output signal is  
Available on 128 Macrocell Devices and Larger  
To AIM  
Global termination  
Pullup/Bus-Hold  
V
REF  
Hysteresis  
To Macrocell  
Direct Input  
Enabled  
CTE  
PTB  
GTS[0:3]  
CGND  
V
CCIO  
4
Open Drain  
Disabled  
From Macrocell  
DS090_04_121201  
Figure 4: CoolRunner-II CPLD I/O Block Diagram  
Table 5 summarizes the single ended I/O standard support  
and shows which standards require V values and board  
REF  
termination. V  
detail is given in specific data sheets.  
REF  
Table 5: CoolRunner-II CPLD I/O Standard Summary  
IOSTANDARD  
Board Termination Voltage  
(V  
Attribute  
V
Input V  
N/A  
)
TT  
Schmitt-trigger Support  
Optional  
CCIO  
REF  
LVTTL  
3.3  
N/A  
N/A  
N/A  
N/A  
N/A  
0.75  
1.25  
1.5  
LVCMOS33  
LVCMOS25  
LVCMOS18  
LVCMOS15  
HSTL_1  
3.3  
2.5  
1.8  
1.5  
1.5  
2.5  
3.3  
N/A  
Optional  
N/A  
Optional  
N/A  
Optional  
N/A  
Not optional  
Not optional  
Not optional  
Not optional  
0.75  
1.25  
1.5  
SSTL2_1  
SSTL3_1  
6
www.xilinx.com  
DS090 (v3.1) September 11, 2008  
Product Specification  
R
CoolRunner-II CPLD Family  
DataGATE, designers can approach zero power, should  
they choose to, in their designs.  
Output Banking  
CPLDs are widely used as voltage interface translators. To  
that end, the output pins are grouped in large banks. The  
XC2C32A, XC2C64A, XC2C128 and XC2C256 devices  
support two output banks. With two, the outputs switch to  
one of two selected output voltage levels, unless both banks  
are set to the same voltage. The larger parts (384 and 512  
macrocell) support four output banks split evenly. They can  
support groupings of one, two, three, or four separate output  
voltage levels. This kind of flexibility permits easy interfacing  
to 3.3V, 2.5V, 1.8V, and 1.5V in a single part.  
I
CC  
0
Frequency  
DataGATE  
DS090_05_101001  
Low power is the hallmark of CMOS technology. Other  
CPLD families use a sense amplifier approach to creating  
product terms, which always has a residual current compo-  
nent being drawn. This residual current can be several hun-  
dred milliamps, making them unusable in portable systems.  
CoolRunner-II CPLDs use standard CMOS methods to cre-  
ate the CPLD architecture and deliver the corresponding  
low current consumption, without doing any special tricks.  
However, sometimes designers want to reduce their system  
current even more by selectively disabling circuitry not  
being used.  
Figure 5: CMOS I vs. Switching Frequency Curve  
CC  
Figure 6 shows how DataGATE basically works. One I/O pin  
drives the DataGATE Assertion Rail. It can have any  
desired logic function on it. It can be as simple as mapping  
an input pin to the DataGATE function or as complex as a  
counter or state machine output driving the DataGATE I/O  
pin through a macrocell. When the DataGATE rail is  
asserted High, any pass transistor switch attached to it is  
blocked. Each pin has the ability to attach to the AIM  
through a DataGATE pass transistor, and thus be blocked. A  
latch automatically captures the state of the pin when it  
becomes blocked. The DataGATE Assertion Rail threads  
throughout all possible I/Os, so each can participate if cho-  
sen. Note that one macrocell is singled out to drive the rail,  
and that macrocell is exposed to the outside world through a  
pin, for inspection. If DataGATE is not needed, this pin is an  
ordinary I/O.  
The patented DataGATE technology to permits a straight-  
forward approach to additional power reduction. Each I/O  
pin has a series switch that can block the arrival of free run-  
ning signals that are not of interest. Signals that serve no  
use might increase power consumption, and can be dis-  
abled. Users are free to do their design, then choose sec-  
tions to participate in the DataGATE function. DataGATE is  
a logic function that drives an assertion rail threaded  
through the medium and high-density CoolRunner-II CPLD  
parts. Designers can select inputs to be blocked under the  
control of the DataGATE function, effectively blocking con-  
trolled switching signals so they do not drive internal chip  
capacitances. Output signals that do not switch are held by  
the bus hold feature. Any set of input pins can be chosen to  
participate in the DataGATE function. Figure 5 shows the  
There are two attributes associated with the DataGATE fea-  
ture in CoolRunner-II CPLDs. The first attribute specifies if  
an input is affected by DataGATE and the second desig-  
nates the DataGATE control signal.  
The DataGATE feature is selectable on a per pin basis.  
Each input pin that uses DataGATE must be assigned a  
DATA_GATE attribute.  
familiar CMOS I versus switching frequency graph. With  
The DataGATE assertion rail can be driven from either an  
I/O pin or internal logic. The DataGATE enable signal is a  
dedicated DGE/I/O pin for each package in CoolRunner-II  
CPLDs. Upon implementation, the software recognizes a  
design using DataGATE and automatically assigns this I/O  
pin to the DataGATE enable control function, DGE. Inter-  
CC  
DS090 (v3.1) September 11, 2008  
www.xilinx.com  
7
Product Specification  
R
CoolRunner-II CPLD Family  
nally generated DataGATE control logic can be assigned to  
this I/O pin with the BUFG=DATA_GATE attribute.  
DataGATE Assertion Rail  
MC1  
MC2  
MC1  
MC2  
Latch  
To AIM  
To AIM  
PLA  
PLA  
Latch  
Latch  
To AIM  
MC16  
MC16  
AIM  
MC1  
MC2  
MC1  
MC2  
PLA  
PLA  
Latch  
Latch  
To AIM  
To AIM  
MC16  
MC16  
DS090_06_111201  
Figure 6: DataGATE Architecture (output drivers not shown)  
purpose I/Os if they are not needed as global signals. The  
DataGATE assertion rail is also a global signal.  
Global Signals  
Global signals, clocks (GCK), sets/resets (GSR), and output  
enables (GTS), are designed to strongly resemble each  
other. This approach enables design software to make the  
best utilization of their capabilities. Each global capability is  
supplemented by a corresponding product term version.  
Figure 7 shows the common structure of the global signal  
trees. The pin input is buffered, then drives multiple internal  
global signal traces to deliver low skew and reduce loading  
delays. GCK, GSR, and GTS can also be used as general  
DS090_07_101001  
Figure 7: Global Clocks (GCK), Sets/Resets (GSR), and  
Output Enables (GTS)  
8
www.xilinx.com  
DS090 (v3.1) September 11, 2008  
Product Specification  
R
CoolRunner-II CPLD Family  
DualEDGE  
Additional Clock Options: Division,  
DualEDGE, and CoolCLOCK  
Each macrocell has the ability to double its input clock  
switching frequency. Figure 9 shows the macrocell flip-flop  
with the DualEDGE option (doubled clock) at each macro-  
cell. The source to double can be a control term clock, a  
product term clock or one of the available global clocks. The  
ability to switch on both clock edges, also known as dual  
edge triggered (DET), is vital for a number of synchronous  
memory interface applications as well as certain double  
data rate I/O applications.  
Clock Divider  
A
clock divider circuit has been included in the  
CoolRunner-II CPLD architecture to divide one externally  
supplied global clock by standard values. The allowable val-  
ues for the division are 2, 4, 6, 8, 10, 12, 14, and 16 (see  
Figure 8). This capability is supplied on the GCK2 pin. The  
resulting clock produced has a 50% duty cycle for all possi-  
ble divisions. The output of the clock divider is on global  
routing. If the clock divider is used, the undivided clock is  
available internally. If the undivided clock is required inter-  
nally it is input through a separate clock pin.  
CoolRunner-II CPLD DET registers can be used for logic  
functions that include shift registers, counters, comparators,  
and state machines. Designers must evaluate the desired  
performance of the CPLD logic to determine use of DET  
registers.  
The clock divider circuit encompasses a synchronous reset  
(CDRST) to guarantee no spurious clocks can carry  
through on to the global clock nets. When the CDRST signal  
is asserted, the clock divider output is disabled after the cur-  
rent cycle. When the CDRST signal is deasserted the clock  
divider output becomes active upon the first edge of GCK2.  
The CDRST pin functions as a reset pin regardless of which  
CLK_DIV primitive is used. If a clock divider is used in the  
design, the CDRST pin is reserved and if it is driven High  
the clock divider is reset. If a reset port of a clock divider is  
not used, it is tied Low on the board. The clock divider circuit  
includes an active High synchronous reset, referred to as  
CDRST.  
The DET register can be inferred in any ABEL, HDL, or  
schematic design. A designer can infer a single-edge trig-  
gered (SET) register in any HDL design. The DET register is  
available with all macrocells in all devices of the  
CoolRunner-II family.  
CoolCLOCK  
In addition to the DualEDGE flip-flop, power savings can  
occur by combining the clock division circuitry with the  
DualEDGE circuitry. This capability is called CoolCLOCK  
and is designed to reduce clocking power within the CPLD.  
Because the clock net can be an appreciable power drain,  
the clock power can be reduced by driving the net at half fre-  
quency, then doubling the clock rate using DualEDGE trig-  
gering at the macrocells. Figure 10 shows how CoolCLOCK  
is created by internal clock cascading with the divider and  
DualEDGE flip-flop working together.  
The CoolRunner-II CPLD clock divider includes a built-in  
delay circuit. With the delay feature enabled, the output of  
the clock divider is delayed for one full count cycle. When  
used, the clock divider does not output a rising clock edge  
until after the divider reaches the delay value. The delay fea-  
ture is either enabled or disabled upon configuration.  
GCK2 is the only clock network that can be divided, the  
CoolCLOCK feature is only available on GCK2. The Cool-  
CLOCK feature can be implemented by assigning an  
attribute to an input clock. The CoolCLOCK attribute  
replaces the need to instantiate the clock divider and infer  
DET registers. The CoolCLOCK feature is available on  
CoolRunner-II 128 macrocell devices and larger. See  
XAPP378 for more detail.  
Xilinx Synthesis Technology (XST) allows a clock divider  
component to be instantiated directly in the HDL source  
code. See XAPP378 for instantiation examples in VHDL,  
Verilog, and ABEL.  
÷2  
÷4  
÷6  
÷8  
GCK2  
Clock  
In  
÷10  
÷12  
÷14  
÷16  
CDRST  
CDRST  
DS090_08_121201  
Figure 8: Clock Division Circuitry for GCK2  
DS090 (v3.1) September 11, 2008  
Product Specification  
www.xilinx.com  
9
R
CoolRunner-II CPLD Family  
D/T  
CE  
Q
FIF  
Latch  
PTC  
DualEDGE  
CK  
GCK0  
GCK1  
GCK2  
CLK_CT  
PTC  
DS090_09_121201  
Figure 9: Macrocell Clock Chain with DualEDGE Option Shown  
D/T  
CE  
Q
FIF  
Latch  
PTC  
DualEDGE  
CK  
GCK0  
GCK1  
GCK2  
CTC  
PTC  
÷2  
÷4  
÷6  
÷8  
GCK2  
Clock  
In  
÷10  
÷12  
÷14  
÷16  
Synch Rst  
Synch Reset  
Figure 10: CoolCLOCK Created by Cascading Clock Divider and DualEDGE Option  
eliminating any electrical or visual detection of configuration  
patterns. These security bits can be reset only by erasing  
the entire device. See WP170 for more detail.  
Design Security  
Designs can be secured during programming to prevent  
either accidental overwriting or pattern theft via readback.  
Four independent levels of security are provided on-chip,  
10  
www.xilinx.com  
DS090 (v3.1) September 11, 2008  
Product Specification  
R
CoolRunner-II CPLD Family  
specific part, and knows the specific delay values for a given  
speed grade. Equations for the higher level timing values  
Timing Model  
Figure 11 shows the CoolRunner-II CPLD timing model. It  
represents one aspect of the overall architecture from a tim-  
ing viewpoint. Each little block is a time delay that a signal  
incurs if the signal passes through such a resource. Timing  
reports are created by tallying the incremental signal delays  
as signals progress within the CPLD. Software creates the  
timing reports after a design has been mapped onto the  
(i.e., T and F  
) are available. Table 6 summarizes  
PD  
SYSTEM  
the individual parameters and provides a brief definition of  
their associated functions. Xilinx application note XAPP375  
details the CoolRunner-II CPLD family timing with several  
examples.  
TF  
TLOGI2  
TPDI  
TIN  
TLOGI1  
D/T  
T
COI  
T
T
SUI  
HI  
TSLEW  
THYS  
THYS  
THYS  
THYS  
THYS  
T
ECSU  
TDIN  
TGCK  
TGSR  
TGTS  
TOUT  
T
ECHO  
T
TCT  
CE  
S/R  
AOI  
TEN  
TOEM  
XAPP375_03_010303  
Figure 11: CoolRunner-II CPLD Timing Model  
Note: Always refer to the timing report in ISE Software for accurate timing values for paths.  
Table 6: Timing Parameter Definitions  
Table 6: Timing Parameter Definitions (Continued)  
Symbol  
Parameter  
Symbol  
Parameter  
Buffer Delays  
Macrocell Delays  
T
T
T
T
T
T
T
T
Input Buffer Delay  
T
T
T
T
T
T
Macrocell input to output valid  
lN  
PDI  
Direct data register input delay  
Global clock (GCK) buffer delay  
Global set/reset (GSR) buffer delay  
Global output enable (GTS) buffer delay  
Output buffer delay  
Macro register setup before clock  
Macro register hold after clock  
DIN  
SUI  
GCK  
GSR  
GTS  
OUT  
EN  
HI  
Macro register enable clock setup time  
Macro register enable clock hold time  
Macro register clock to output valid  
Macro register set/reset to output valid  
Hysteresis selection delay adder  
ECSU  
ECHO  
COI  
Output buffer enable/disable delay  
Output buffer slew rate control delay  
T
AOI  
T
SLEW  
HYS  
P-term Delays  
Feedback Delays  
T
T
T
Control Term delay (single PT or FB-CT)  
Single P-term logic delay  
T
T
Feedback delay  
CT  
F
Macrocell to Global OE delay  
LOGI1  
LOGI2  
OEM  
Multiple P-term logic delay adder  
DS090 (v3.1) September 11, 2008  
www.xilinx.com  
11  
Product Specification  
R
CoolRunner-II CPLD Family  
as well. The internal controllers can operate as fast as  
66 MHz.  
Programming  
The programming data sequence is delivered to the device  
using either Xilinx iMPACT software and a Xilinx download  
Table 7: JTAG Instructions  
cable,  
a
third-party JTAG development system,  
a
Code  
Instruction  
Description  
JTAG-compatible board tester, or a simple microprocessor  
interface that emulates the JTAG instruction sequence. The  
iMPACT software also outputs serial vector format (SVF)  
files for use with any tools that accept SVF format, including  
automatic test equipment. See CoolRunner-II CPLD  
Application Notes for more information on how to program.  
00000000  
EXTEST  
Force boundary scan data onto  
outputs  
00000011 PRELOAD Latch macrocell data into  
boundary scan cells  
11111111  
00000010  
00000001  
BYPASS  
INTEST  
IDCODE  
Insert bypass register between  
TDI and TDO  
In System Programming  
All CoolRunner-II CPLD parts are 1.8V in system program-  
mable. This means they derive their programming voltage  
and currents from the 1.8V V  
pins on the part. The V  
Force boundary scan data onto  
inputs and feedbacks  
(internal supply voltage)  
pins do not participate in this  
Read IDCODE  
CC  
CCIO  
11111101 USERCODE Read USERCODE  
operation, as they might assume another voltage ranging as  
high as 3.3V down to 1.5V (however, all V  
, V  
,
11111100  
HIGHZ  
Force output into high  
impedance state  
CCIO  
CCINT  
V
, and GND pins must be connected for the device to  
CCAUX  
be programmed, and operate correctly). A 1.8V V  
is  
CC  
11111010  
CLAMP  
Latch present output state  
required to properly operate the internal state machines and  
charge pumps that reside within the CPLD to do the nonvol-  
atile programming operations. I/O pins are not in user mode  
during JTAG programming; they are held in 3-state with a  
weak pullup. The JTAG interface buffers are powered by a  
Power-Up Characteristics  
CoolRunner-II CPLD parts must operate under the  
demands of both the high-speed and the portable market  
places; therefore, they must support hot plugging for the  
high-speed world and tolerate most any power sequence to  
its various voltage pins. They must also not draw excessive  
current during power-up initialization. To those ends, the  
general behavior is summarized as follows:  
dedicated power pin, V  
, which is independent of all  
CCAUX  
other supply pins. V  
must be connected. Xilinx soft-  
CCAUX  
ware is provided to deliver the bitstream to the CPLD and  
drive the appropriate IEEE 1532 protocol. To that end, there  
is a set of IEEE 1532 commands that are supported in the  
CoolRunner-II CPLD parts. Programming times are less  
than one second for 32 to 256 macrocell parts. Program-  
ming times are less than four seconds for 384 and 512 mac-  
rocell parts. Programming of CoolRunner-II CPLDs is only  
guaranteed when operating in the commercial temperature  
and voltage ranges as defined in the device-specific data  
sheets.  
1. I/O pins are disabled until the end of power-up.  
2. As supply rises, configuration bits transfer from  
nonvolatile memory to SRAM cells.  
3. As power up completes, the outputs become as  
configured (input, output, or I/O).  
4. For specific configuration times and power up  
requirements, see XAPP389.  
On-The-Fly Reconfiguration (OTF)  
CoolRunner-II CPLD I/O pins are well behaved under all  
operating conditions. During power-up, CoolRunner-II  
devices employ internal circuitry which keeps the devices in  
The Xilinx ISE 5.2i tool supports OTF for CoolRunner-II  
CPLDs. This permits programming a new nonvolatile pat-  
tern into the part while another pattern is currently in use.  
OTF has the same voltage and temperature specifications  
as system programming. During pattern transition I/O pins  
the quiescent state until the V  
supply voltage is at a  
CCINT  
safe level (approximately 1.3V). In the quiescent state,  
JTAG pins are disabled, and all device outputs are disabled  
with the pins weakly pulled High, as shown in Table 8. When  
the supply voltage reaches a safe level, all user registers  
become initialized, and the device is immediately available  
for operation, as shown in Figure 12. Best results are  
are in high impedance with a weak pullup to V  
. Transi-  
CCIO  
tion time typically lasts between 50 and 300 μs, depending  
on density. See XAPP388 for more information.  
JTAG Instructions  
Table 7 shows the commands available to users. These  
same commands can be used by third party ATE products,  
obtained with a smooth V rise in less than 4 ms. Final  
CC  
V
value should occur within 1 second.  
CC  
If the device is in the erased state (before any user pattern  
is programmed), the device outputs remain disabled with a  
weak pull-up. The JTAG pins are enabled to allow the device  
12  
www.xilinx.com  
DS090 (v3.1) September 11, 2008  
Product Specification  
R
CoolRunner-II CPLD Family  
to be programmed at any time. All devices are shipped in  
the erased state from the factory.  
V
CCINT  
Applying power to a blank part might result in a higher cur-  
rent flow as the part initializes. This behavior is normal and  
might persist for approximately 2 seconds, depending on  
the power supply ramp.  
1.3V  
(Typ)  
If the device is programmed, the device inputs and outputs  
take on their configured states for normal operation. The  
JTAG pins are enabled to allow device erasure or bound-  
ary-scan tests at any time.  
0V  
No  
Power  
Quiescent  
State  
Quiescent  
State  
No  
Power  
User Operation  
Initialization Transition of User Array  
x382_10  
Figure 12: Device Behavior During Power Up  
Table 8: I/O Power-Up Characteristics  
Device Circuitry  
IOB Bus-Hold/Weak Pullup  
Device Outputs  
Quiescent State  
Weak Pull-up  
Disabled  
Erased Device Operation  
Valid User Operation  
Bus-Hold/Weak Pullup  
As Configured  
Weak Pull-up  
Disabled  
Disabled  
Disabled  
Enabled  
Device Inputs and Clocks  
Function Block  
Disabled  
As Configured  
Disabled  
As Configured  
JTAG Controller  
Disabled  
Enabled  
and the CoolRunner-II CPLD will not be damaged. For best  
results, Xilinx recommends that V be applied before  
I/O Banking  
CoolRunner-II CPLD XC2C32A and XC2C64A macrocell  
parts support two V rails that can range from 3.3V  
down to 1.5V operation. Two V  
the 128 and 256 macrocell parts where outputs on each rail  
can independently range from 3.3V down to 1.5V operation.  
CCINT  
V
To ensure that the internal logic is correct before the  
CCIO  
CCIO  
I/Os are active. CoolRunner-II CPLDs can reside on boards  
where the board is inserted into a “live” connector (hot  
plugged) and the parts will be well-behaved as if powering  
up in a standard way.  
rails are supported on  
CCIO  
Four V  
rails are supported on the 384 and 512 macro-  
CCIO  
cell parts. Any of the V  
rails can assume any one of the  
CCIO  
Development System Support  
V
values of 1.5V, 1.8V, 2.5V, or 3.3V. Designers should  
CCIO  
Xilinx CoolRunner-II CPLDs are supported by all configura-  
tions of Xilinx standard release development software as  
well as the freely available ISE WebPACK software avail-  
able from www.xilinx.com. Third party development tools  
include synthesis tools from Cadence, Exemplar, Mentor  
Graphics, Synplicity, and Synopsys.  
assign input and output voltages to a bank with V  
the voltage range of that input or output voltage. The V  
(internal supply voltage) for a CoolRunner-II CPLD must be  
maintained within 1.8V 5% for correct speed operation and  
proper in system programming.  
set at  
CCIO  
CC  
Mixed Voltage, Power Sequencing, and  
Hot Plugging  
As mentioned in I/O Banking, CoolRunner-II CPLD parts  
support mixed voltage I/O signals. It is important to assign  
signals to an I/O bank with the appropriate I/O voltage. Driv-  
ing a high voltage into a low voltage bank can result in neg-  
ative current flow through the power supply pins. The power  
ATE Support  
Third party ATE development support is available for both  
programming and board/chip level testing. Vendors provid-  
ing this support include Agilent, GenRad, and Teradyne.  
Other third party providers are expected to deliver solutions  
in the future.  
applied to the V  
and V  
pins can occur in any order  
CCIO  
CC  
DS090 (v3.1) September 11, 2008  
www.xilinx.com  
13  
Product Specification  
R
CoolRunner-II CPLD Family  
Absolute Maximum Ratings  
(1)  
Symbol  
Parameter  
Supply voltage relative to GND  
Min.  
–0.5  
–0.5  
0
Max.  
2.0  
4.0  
70  
Unit  
V
(2)  
V
CC  
(3)  
V
Input voltage relative to GND  
Ambient Temperature (C-grade)  
Ambient Temperature (I-grade)  
Maximum junction temperature  
Storage temperature  
V
I
T
°C  
°C  
°C  
°C  
A
–40  
–40  
–65  
85  
(4)  
T
150  
150  
J
T
STR  
Notes:  
1. Stresses above those listed might cause malfunction or permanent damage to the device. This is a stress rating only. Functional  
operation at these or any other condition above those indicated in the operational and programming specification is not implied.  
2. The chip supply voltage should rise monotonically.  
3. Maximum DC undershoot below GND must be limited to either 0.5V or 10 mA, whichever is easier to achieve. During transitions, the  
device pins might undershoot to –2.0V or overshoot to 4.5 V, provided this overshoot or undershoot lasts less than 10 ns and with the  
forcing current being limited to 200 mA. The I/O voltage can never exceed 4.0V.  
4. For soldering guidelines and thermal considerations, see the Device Packaging information on the Xilinx website. For Pb-free  
packages, see XAPP427.  
Quality and Reliability Parameters  
Symbol  
Parameter  
Min  
20  
Max  
Units  
Years  
Cycles  
Volts  
T
Data retention  
-
-
-
DR  
N
Program/erase cycles (Endurance)  
Electrostatic discharge(1)  
1,000  
2,000  
PE  
V
ESD  
Notes:  
1. ESD is measured to 2000V using the human body model. Pins exposed to this limit can incur additional leakage current to  
a maximum of 10 μA when driven to 3.9V.  
Warranty Disclaimer  
THESE PRODUCTS ARE SUBJECT TO THE TERMS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED  
AT http://www.xilinx.com/warranty.htm. THIS LIMITED WARRANTY DOES NOT EXTEND TO ANY USE OF THE  
PRODUCTS IN AN APPLICATION OR ENVIRONMENT THAT IS NOT WITHIN THE SPECIFICATIONS STATED ON THE  
THEN-CURRENT XILINX DATA SHEET FOR THE PRODUCTS. PRODUCTS ARE NOT DESIGNED TO BE FAIL-SAFE  
AND ARE NOT WARRANTED FOR USE IN APPLICATIONS THAT POSE A RISK OF PHYSICAL HARM OR LOSS OF  
LIFE. USE OF PRODUCTS IN SUCH APPLICATIONS IS FULLY AT THE RISK OF CUSTOMER SUBJECT TO  
APPLICABLE LAWS AND REGULATIONS.  
http://www.xilinx.com/support/documenta-  
tion/application_notes/xapp317.pdf  
Further Reading  
(Power Evaluation Equation for CoolRunner-II CPLDs)  
Application Notes  
http://www.xilinx.com/support/documentation/application_no  
tes/xapp377.pdf (Low Power Design)  
http://www.xilinx.com/support/documenta-  
tion/application_notes/xapp784.pdf  
(Bulletproof Design Practices)  
http://www.xilinx.com/support/documentation/application_no  
tes/xapp378.pdf (Advanced Features)  
http://www.xilinx.com/support/documentation/application_no  
tes/xapp375.pdf (Timing Model)  
http://www.xilinx.com/support/documentation/application_no  
tes/xapp379.pdf (High Speed Design)  
http://www.xilinx.com/support/documentation/application_no  
tes/xapp376.pdf (Logic Engine)  
http://www.xilinx.com/support/documentation/application_no  
tes/xapp380.pdf (Cross Point Switch)  
14  
www.xilinx.com  
DS090 (v3.1) September 11, 2008  
Product Specification  
R
CoolRunner-II CPLD Family  
http://www.xilinx.com/support/documentation/application_no  
tes/xapp381.pdf (Demo Board)  
CoolRunner-II CPLD Data Sheets  
http://www.xilinx.com/support/documentation/data_sheets/d  
s090.pdf (CoolRunner-II Family Data Sheet)  
http://www.xilinx.com/support/documentation/application_no  
tesxapp382.pdf (I/O Characteristics)  
http://www.xilinx.com/support/documentation/data_sheets/d  
http://www.xilinx.com/support/documentation/application_no  
tes/xapp383.pdf (Single Error Correction Double Error  
Detection)  
s310.pdf (XC2C32A Data Sheet)  
http://www.xilinx.com/support/documentation/data_sheets/d  
s311.pdf (XC2C64A Data Sheet)  
http://www.xilinx.com/support/documentation/application_no  
tes/xapp384.pdf (DDR SDRAM Interface)  
http://www.xilinx.com/support/documentation/data_sheets/d  
s093.pdf (XC2C128 Data Sheet)  
http://www.xilinx.com/support/documentation/application_no  
tes/xapp387.pdf (PicoBlaze Microcontroller)  
http://www.xilinx.com/support/documentation/data_sheets/d  
s094.pdf (XC2C256 Data Sheet)  
http://www.xilinx.com/support/documentation/application_no  
tes/xapp388.pdf (On the Fly Reconfiguration)  
http://www.xilinx.com/support/documentation/data_sh  
eets/ds095.pdf (XC2C384 Data Sheet)  
http://www.xilinx.com/support/documentation/application_no  
tes/xapp389.pdf (Powering CoolRunner-II)  
http://www.xilinx.com/support/documentation/data_sheets/d  
s096.pdf (XC2C512 Data Sheet)  
http://www.xilinx.com/support/documentation/application_no  
tes/xapp393.pdf (8051 Microcontroller Interface)  
CoolRunner-II CPLD White Papers  
http://www.xilinx.com/support/documenta-  
tion/white_papers/wp170.pdf (Secure Applications)  
http://www.xilinx.com/support/documentation/application_no  
tes/xapp394.pdf (Interfacing with Mobile SDRAM)  
http://www.xilinx.com/support/documentation/application_no  
tes/xapp399.pdf (Assigning CoolRunner-II VREF Pins)  
Packages  
Package Drawings  
Revision History  
The following table shows the revision history for this document.  
Date  
Version  
1.0  
Revision  
01/03/02  
07/04/02  
07/24/02  
09/24/02  
01/28/03  
02/26/03  
03/12/03  
10/09/03  
01/26/04  
02/26/04  
Initial Xilinx release  
1.1  
Revisions and updates  
Revisions and updates  
1.2  
1.3  
Additions to "Power Characteristics" section  
1.4  
Addition of the "Further Reading" section  
1.5  
Multiple minor revisions  
1.6  
Minor revision to "Quality and Reliability Parameters"  
Update Hewlett-Packard to Agilent, OFR to OTF, and other revisions  
Incorporate links to Data Sheets, Application Notes, and Device Packages  
1.7  
1.8  
1.9  
Change to Power-Up Characteristics, page 11. Change T  
to T . Add Schmitt-trigger  
FIN DIN  
I/O compatibility information. Added T  
specification.  
SOL  
05/21/04  
07/30/04  
01/10/05  
03/07/05  
2.0  
2.1  
2.2  
2.3  
Add XC2C32A and XC2C64A devices.  
Pb-free documentation. Changes to T and F  
to match individual data sheets.  
system  
SU  
Added information about programming options, page 11.  
Changes to Table 1, T , T , T , and F Removed link to obsolete White Paper.  
PD SU CO  
SYSTEM1.  
Modifications to Table 5, IOSTANDARDs. Added Table 2, DC Characteristics.  
DS090 (v3.1) September 11, 2008  
www.xilinx.com  
15  
Product Specification  
R
CoolRunner-II CPLD Family  
Date  
Version  
2.4  
Revision  
04/15/05  
06/28/05  
03/20/06  
Change to F  
for XC2C128.  
SYSTEM1  
2.5  
Move to Product Specification  
2.6  
Add Warranty Disclaimer; modified Global Signals section to say that GCK, GSR and GTS  
can be used as general purpose I/O.  
07/24/06  
12/7/06  
2.7  
2.8  
Change to Hot Plugging recommendations, page 13 (V  
sequencing).  
before V  
power  
CCIO  
CCINT  
Add description of I/O pin status during JTAG programming, page 12. Add note about power  
pins during programming. Add link to application note 389, page 12. Added clarification to  
clock divider description, page 9.  
02/15/07  
03/08/07  
09/11/08  
2.9  
3.0  
3.1  
Add greater description to advanced features. Added Ambient Temperature specification.  
Add link to power estimation appnote, page 14.  
Removed reference to XC2C32 and XC2C64 devices. See Product Discontinuation Notice  
xcn05017.pdf.  
Removed references to PC44 and PCG44 packages. See Product Discontinuation Notice  
xcn07022.pdf.  
16  
www.xilinx.com  
DS090 (v3.1) September 11, 2008  
Product Specification  
配单直通车
  •  
  • 供货商
  • 型号 *
  • 数量*
  • 厂商
  • 封装
  • 批号
  • 交易说明
  • 询价
批量询价选中的记录已选中0条,每次最多15条。
 复制成功!