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  • 北京元坤伟业科技有限公司

         该会员已使用本站17年以上

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  • 深圳市芯福林电子有限公司

     该会员已使用本站15年以上
  • XC2C256-7VQ100C 现货库存
  • 数量1600 
  • 厂家XILINX 
  • 封装QFP100 
  • 批号新年份 
  • 真实库存全新原装正品!代理此型号!
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  • 深圳市毅创腾电子科技有限公司

     该会员已使用本站16年以上
  • XC2C256-7VQ100C 现货库存
  • 数量3200 
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  • 批号22+ 
  • 专业分销XILINX产品!原装正品!
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  • 集好芯城

     该会员已使用本站13年以上
  • XC2C256-7VQ100C 现货库存
  • 数量1751 
  • 厂家XILINX(赛灵思) 
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  • 批号22+ 
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  • 深圳市恒益昌科技有限公司

     该会员已使用本站6年以上
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  • 数量6000 
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  • 批号23+ 
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  • 深圳市华科泰电子商行

     该会员已使用本站13年以上
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  • 数量650 
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  • HECC GROUP CO.,LIMITED

     该会员已使用本站17年以上
  • XC2C256-7VQ100C 现货库存
  • 数量2680 
  • 厂家XILINX 
  • 封装QFP 
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  • 上海磐岳电子有限公司

     该会员已使用本站11年以上
  • XC2C256-7VQ100C 现货库存
  • 数量9000 
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  • 封装VQ100 
  • 批号2024+ 
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  • 深圳市芯福林电子有限公司

     该会员已使用本站15年以上
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  • 数量65000 
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  • 封装QFP 
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  • 真实库存全新原装正品!代理此型号
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  • 深圳市芯福林电子有限公司

     该会员已使用本站15年以上
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  • 数量98500 
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  • 封装QFP 
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  • 真实库存全新原装正品!代理此型号
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  • 深圳市龙腾新业科技有限公司

     该会员已使用本站17年以上
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  • 数量1751 
  • 厂家XILINX(赛灵思) 
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  • 深圳市正纳电子有限公司

     该会员已使用本站15年以上
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  • 数量5000 
  • 厂家XILINX/赛灵思 
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  • 千层芯半导体(深圳)有限公司

     该会员已使用本站9年以上
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  • 数量30617 
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  • 主打XILINX品牌价格绝对优势
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  • 深圳市恒达亿科技有限公司

     该会员已使用本站12年以上
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  • 数量3000 
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  • 封装QFP 
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  • 柒号芯城电子商务(深圳)有限公司

     该会员已使用本站13年以上
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  • 数量700000 
  • 厂家XILINX 
  • 封装VQFP-100(14X14) 
  • 批号2023+ 
  • 柒号芯城跟原厂的距离只有0.07公分
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  • 深圳市卓越微芯电子有限公司

     该会员已使用本站12年以上
  • XC2C256-7VQ100C
  • 数量6500 
  • 厂家XILINX 
  • 封装QFP 
  • 批号20+ 
  • 百分百原装正品 真实公司现货库存 本公司只做原装 可开13%增值税发票,支持样品,欢迎来电咨询!
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  • 深圳市和诚半导体有限公司

     该会员已使用本站11年以上
  • XC2C256-7VQ100C
  • 数量5600 
  • 厂家XILINX 
  • 封装QFP100 
  • 批号23+ 
  • 只做原装正品,深圳现货
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  • 深圳市得捷芯城科技有限公司

     该会员已使用本站11年以上
  • XC2C256-7VQ100C
  • 数量3320 
  • 厂家XILINX/赛灵思 
  • 封装NA/ 
  • 批号23+ 
  • 原厂直销,现货供应,账期支持!
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  • 深圳市晶美隆科技有限公司

     该会员已使用本站15年以上
  • XC2C256-7VQ100C
  • 数量85000 
  • 厂家XILINX/赛灵思 
  • 封装VQFP 
  • 批号24+ 
  • 假一罚十,原装进口正品现货供应,价格优势。
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  • 0755-82865294 QQ:198857245
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  • 集好芯城

     该会员已使用本站13年以上
  • XC2C256-7VQ100C
  • 数量5801 
  • 厂家XILINX/赛灵思 
  • 封装QFP100 
  • 批号最新批次 
  • 原厂原装公司现货
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  • 深圳市宏捷佳电子科技有限公司

     该会员已使用本站6年以上
  • XC2C256-7VQ100C
  • 数量6500 
  • 厂家XILINX 
  • 封装TQFP 
  • 批号24+ 
  • 全新原装★真实库存★含13点增值税票!
  • QQ:2885134615QQ:2885134615 复制
    QQ:2353549508QQ:2353549508 复制
  • 0755-83201583 QQ:2885134615QQ:2353549508
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  • 深圳市宏捷佳电子科技有限公司

     该会员已使用本站12年以上
  • XC2C256-7VQ100C
  • 数量12300 
  • 厂家XILINX 
  • 封装QFP100 
  • 批号24+ 
  • ★原装真实库存★13点税!
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    QQ:2885134615QQ:2885134615 复制
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  • 深圳市晶美隆科技有限公司

     该会员已使用本站14年以上
  • XC2C256-7VQ100C
  • 数量18530 
  • 厂家XILINX 
  • 封装TQFP10.. 
  • 批号23+ 
  • 全新原装正品现货热卖
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  • 深圳市恒益昌科技有限公司

     该会员已使用本站6年以上
  • XC2C256-7VQ100C
  • 数量4500 
  • 厂家XILINX 
  • 封装QFP 
  • 批号23+ 
  • 原装正品长期供货
  • QQ:3336148967QQ:3336148967 复制
    QQ:974337758QQ:974337758 复制
  • 0755-82723761 QQ:3336148967QQ:974337758
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  • 深圳市华科泰电子商行

     该会员已使用本站13年以上
  • XC2C256-7VQ100C
  • 数量650 
  • 厂家XILINX 
  • 封装QFP 
  • 批号2009+ 
  • 绝对原装现货特价
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    QQ:1439873477QQ:1439873477 复制
  • 0755-82567800 QQ:405945546QQ:1439873477
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  • 深圳市恒达亿科技有限公司

     该会员已使用本站12年以上
  • XC2C256-7VQ100C
  • 数量6000 
  • 厂家XILINX 
  • 封装QFP100 
  • 批号23+ 
  • 全新原装公司现货销售
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  • 北京中其伟业科技有限公司

     该会员已使用本站16年以上
  • XC2C256-7VQ100CR02
  • 数量10000 
  • 厂家XILINX 
  • 封装 
  • 批号16+ 
  • 特价,原装正品,绝对公司现货库存,原装特价!
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  • 010-62104891 QQ:2880824479
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  • 深圳市宏世佳电子科技有限公司

     该会员已使用本站13年以上
  • XC2C256-7VQ100C
  • 数量3785 
  • 厂家Xilinx 
  • 封装100-TQFP 
  • 批号2023+ 
  • 全新原厂原装产品、公司现货销售
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  • 深圳市美思瑞电子科技有限公司

     该会员已使用本站12年以上
  • XC2C256-7VQ100C
  • 数量9217 
  • 厂家XILINX 
  • 封装QFP 
  • 批号22+ 
  • 市场最低价!原厂原装假一罚十
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  • 深圳市华芯盛世科技有限公司

     该会员已使用本站13年以上
  • XC2C256-7VQ100C
  • 数量865000 
  • 厂家XILINX 
  • 封装XILINX 
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  • 一级代理,原装特价现货!
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  • HECC GROUP CO.,LIMITED

     该会员已使用本站17年以上
  • XC2C256-7VQ100C
  • 数量2680 
  • 厂家XILINX 
  • 封装QFP 
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  • 原装假一赔十!可提供正规渠道证明!
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  • 深圳市金嘉锐电子有限公司

     该会员已使用本站14年以上
  • XC2C256-7VQ100C
  • 数量28620 
  • 厂家Xilinx 
  • 封装100-TQFP 
  • 批号24+ 
  • 【原装优势★★★绝对有货】
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  • 深圳市惊羽科技有限公司

     该会员已使用本站11年以上
  • XC2C256-7VQ100C
  • 数量2368 
  • 厂家XILINX-赛灵思 
  • 封装QFP-100 
  • 批号▉▉:2年内 
  • ▉▉¥113元一有问必回一有长期订货一备货HK仓库LPC4357FET256
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  • 深圳市华斯顿电子科技有限公司

     该会员已使用本站16年以上
  • XC2C256-7VQ100C
  • 数量12258 
  • 厂家XILINX 
  • 封装TQFP 
  • 批号2023+ 
  • 绝对原装正品全新进口深圳现货
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  • 深圳分公司0755-83777708“进口原装正品专供” QQ:1002316308QQ:515102657
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  • 深圳市斌腾达科技有限公司

     该会员已使用本站9年以上
  • XC2C256-7VQ100C
  • 数量1686 
  • 厂家Xilinx 
  • 封装100-VQFP(14x14) 
  • 批号18+ 
  • 进口原装!长期供应!绝对优势价格(诚信经营
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  • HECC GROUP CO.,LIMITED

     该会员已使用本站17年以上
  • XC2C256-7VQ100C
  • 数量1032 
  • 厂家XILINX 
  • 封装QFP 
  • 批号24+ 
  • 原装假一赔十!可提供正规渠道证明!
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  • 深圳市宏世佳电子科技有限公司

     该会员已使用本站13年以上
  • XC2C256-7VQ100C
  • 数量3785 
  • 厂家Xilinx 
  • 封装100-TQFP 
  • 批号2023+ 
  • 全新原厂原装产品、公司现货销售
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  • HECC GROUP CO.,LIMITED

     该会员已使用本站17年以上
  • XC2C256-7VQ100C
  • 数量1032 
  • 厂家XILINX 
  • 封装QFP 
  • 批号24+ 
  • 原装假一赔十!可提供正规渠道证明!
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  • 深圳市英德州科技有限公司

     该会员已使用本站2年以上
  • XC2C256-7VQ100C
  • 数量45200 
  • 厂家XILINX(赛灵思) 
  • 封装VQFP-100(14x14) 
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  • 昂富(深圳)电子科技有限公司

     该会员已使用本站4年以上
  • XC2C256-7VQ100C
  • 数量72282 
  • 厂家XILINX/赛灵思 
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产品型号XC2C256-7VQ100C的概述

XC2C256-7VQ100C 芯片概述 XC2C256-7VQ100C 是由 Xilinx 公司生产的一款配置逻辑芯片(CPLD),它属于 Xilinx 的 CoolRunner-II 系列。这一系列芯片以其高效的功耗和灵活的配置能力而受到广泛关注。XC2C256 芯片专注于中等密度逻辑应用,适用于需要快速处理和较高集成度的电子设计。其主要应用领域包括消费电子、通信设备、工业控制等。 详细参数 在理解 XC2C256-7VQ100C 的具体特性时,有几个关键参数值得关注: 1. 逻辑单元:XC2C256-7VQ100C 含有 256 个逻辑单元(LUT),每个逻辑单元支持 4 路输入。这一结构使得该芯片在执行组合逻辑和时序逻辑时具备较强的灵活性。 2. 时钟频率:此芯片的工作频率通常可以达到 100MHz,适用于需要时钟控制的逻辑处理。 3. 电源电压:芯片工作电压为 1.8V,具有...

产品型号XC2C256-7VQ100C的Datasheet PDF文件预览

0
R
XC2C256 CoolRunner-II CPLD  
0
0
DS094 (v2.7) March 7, 2005  
Preliminary Product Specification  
Features  
Description  
Optimized for 1.8V systems  
The CoolRunner™-II 256-macrocell device is designed for  
both high performance and low power applications. This  
lends power savings to high-end communication equipment  
and high speed to battery operated devices. Due to the low  
power stand-by and dynamic operation, overall system reli-  
ability is improved  
-
-
As fast as 5.7 ns pin-to-pin delays  
As low as 13 µA quiescent current  
Industry’s best 0.18 micron CMOS CPLD  
-
Optimized architecture for effective logic synthesis.  
Refer to the CoolRunner™-II family data sheet for  
architecture description.  
This device consists of sixteen Function Blocks inter-con-  
nected by a low power Advanced Interconnect Matrix (AIM).  
The AIM feeds 40 true and complement inputs to each  
Function Block. The Function Blocks consist of a 40 by 56  
P-term PLA and 16 macrocells which contain numerous  
configuration bits that allow for combinational or registered  
modes of operation.  
-
Multi-voltage I/O operation — 1.5V to 3.3V  
Available in multiple package options  
-
-
-
-
-
-
100-pin VQFP with 80 user I/O  
144-pin TQFP with 118 user I/O  
132-ball CP (0.5mm) BGA with 106 user I/O  
208-pin PQFP with 173 user I/O  
256-ball FT (1.0mm) BGA with 184 user I/O  
Pb-free available for all packages  
Additionally, these registers can be globally reset or preset  
and configured as a D or T flip-flop or as a D latch. There  
are also multiple clock signals, both global and local product  
term types, configured on a per macrocell basis. Output pin  
configurations include slew rate limit, bus hold, pull-up,  
open drain and programmable grounds. A Schmitt-trigger  
input is available on a per input pin basis. In addition to stor-  
ing macrocell output states, the macrocell registers may be  
configured as "direct input" registers to store signals directly  
from input pins.  
Advanced system features  
-
Fastest in system programming  
1.8V ISP using IEEE 1532 (JTAG) interface  
·
-
-
-
IEEE1149.1 JTAG Boundary Scan Test  
Optional Schmitt-trigger input (per pin)  
Unsurpassed low power management  
·
DataGATE enable (DGE) signal control  
-
-
-
Two separate I/O banks  
RealDigital 100% CMOS product term generation  
Flexible clocking modes  
Clocking is available on a global or Function Block basis.  
Three global clocks are available for all Function Blocks as  
a synchronous clock source. Macrocell registers can be  
individually configured to power up to the zero or one state.  
A global set/reset control line is also available to asynchro-  
nously set or reset selected registers during operation.  
Additional local clock, synchronous clock-enable, asynchro-  
nous set/reset and output enable signals can be formed  
using product terms on a per-macrocell or per-Function  
Block basis.  
·
·
·
Optional DualEDGE triggered registers  
Clock divider (divide by 2,4,6,8,10,12,14,16)  
CoolCLOCK  
-
Global signal options with macrocell control  
·
Multiple global clocks with phase selection per  
macrocell  
·
·
Multiple global output enables  
Global set/reset  
-
-
Advanced design security  
PLA architecture  
A DualEDGE flip-flop feature is also available on a per mac-  
rocell basis. This feature allows high performance synchro-  
nous operation based on lower frequency clocking to help  
reduce the total power consumption of the device.  
·
·
Superior pinout retention  
100% product term routability across function  
block  
-
-
Open-drain output option for Wired-OR and LED  
drive  
Optional bus-hold, 3-state or weak pull-up on  
selected I/O pins  
Optional configurable grounds on unused I/Os  
Mixed I/O voltages compatible with 1.5V, 1.8V,  
2.5V, and 3.3V logic levels  
Circuitry has also been included to divide one externally  
supplied global clock (GCK2) by eight different selections.  
This yields divide by even and odd clock frequencies.  
The use of the clock divide (division by 2) and DualEDGE  
flip-flop gives the resultant CoolCLOCK feature.  
-
-
DataGATE is a method to selectively disable inputs of the  
CPLD that are not of interest during certain points in time.  
·
SSTL2-1, SSTL3-1, and HSTL-1 I/O compatibility  
-
Hot pluggable  
© 2005 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.  
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.  
1
Preliminary Product Specification  
R
XC2C256 CoolRunner-II CPLD  
By mapping a signal to the DataGATE function, lower power  
can be achieved due to reduction in signal switching.  
for I/O standard voltages. The LVTTL I/O standard is a gen-  
eral purpose EIA/JEDEC standard for 3.3V applications that  
use an LVTTL input buffer and Push-Pull output buffer. The  
LVCMOS standard is used in 3.3V, 2.5V, 1.8V applications.  
Both HSTL and SSTL I/O standards make use of a VREF pin  
for JEDEC compliance. CoolRunner-II CPLDs are also 1.5V  
I/O compatible with the use of Schmitt-trigger inputs  
Another feature that eases voltage translation is I/O bank-  
ing. Two I/O banks are available on the CoolRunner-II 256  
macrocell device that permit easy interfacing to 3.3V, 2.5V,  
1.8V, and 1.5V devices.  
The CoolRunner-II 256 macrocell CPLD is I/O compatible  
with various I/O standards (see Table 1). This device is also  
1.5V I/O compatible with the use of Schmitt-trigger inputs.  
Table 1: I/O Standards for XC2C256(1)  
Board  
IOSTANDARD Output Input Input Termination  
RealDigital Design Technology  
Attribute  
VCCIO  
VCCIO VREF Voltage VTT  
Xilinx CoolRunner-II CPLDs are fabricated on a 0.18 micron  
process technology which is derived from leading edge  
FPGA product development. CoolRunner-II CPLDs employ  
RealDigital, a design technique that makes use of CMOS  
technology in both the fabrication and design methodology.  
RealDigital design technology employs a cascade of CMOS  
gates to implement sum of products instead of traditional  
sense amplifier methodology. Due to this technology, Xilinx  
CoolRunner-II CPLDs achieve both high-performance and  
low power operation.  
LVTTL  
3.3  
3.3  
3.3  
2.5  
1.8  
1.5  
1.5  
2.5  
3.3  
N/A  
N/A  
N/A  
N/A  
N/A  
0.75  
1.25  
1.5  
N/A  
N/A  
N/A  
N/A  
N/A  
0.75  
1.25  
1.5  
LVCMOS33  
LVCMOS25  
LVCMOS18  
LVCMOS15 (2)  
HSTL_1  
3.3  
2.5  
1.8  
1.5  
1.5  
SSTL2_1  
2.5  
SSTL3_1  
3.3  
(1)For information on Vref, see XAPP399.  
(2) LVCMOS15 requires Schmitt-trigger inputs.  
Supported I/O Standards  
The CoolRunner-II 256 macrocell features LVCMOS,  
LVTTL, SSTL and HSTL I/O implementations. See Table 1  
100  
75  
50  
25  
0
50  
100  
150  
200  
250  
0
Frequency (MHz)  
Figure 1: ICC vs Frequency  
Table 2: ICC vs Frequency (LVCMOS 1.8V TA = 25°C)(1)  
Frequency (MHz)  
100 120 150  
0.021 11.68 19.40 27.01 38.18 45.54 56.32 63.37 70.40 80.90 88.03  
0
30  
50  
70  
170  
190  
220  
240  
Typical ICC (mA)  
Notes:  
1. 16-bit up/down, resettable binary counter (one counter per function block).  
DS094 (v2.7) March 7, 2005  
Preliminary Product Specification  
R
XC2C256 CoolRunner-II CPLD  
Absolute Maximum Ratings  
Symbol  
Description  
Supply voltage relative to ground  
Supply voltage for output drivers  
Value  
Units  
V
VCC  
–0.5 to 2.0  
–0.5 to 4.0  
–0.5 to 4.0  
–0.5 to 4.0  
–0.5 to 4.0  
–0.5 to 4.0  
–65 to +150  
+150  
VCCIO  
V
(2)  
VJTAG  
VAUX  
JTAG input voltage limits  
V
JTAG input supply voltage  
Input voltage relative to ground  
Voltage applied to 3-state output  
Storage Temperature (ambient)  
Junction Temperature  
V
(1)  
VIN  
V
(1)  
VTS  
V
(3)  
TSTG  
TJ  
°C  
°C  
Notes:  
1. Maximum DC undershoot below GND must be limited to either 0.5V or 10 mA, whichever is easiest to achieve. During transitions,  
the device pins may undershoot to –2.0v or overshoot to +4.5V, provided this over or undershoot lasts less than 10 ns and with the  
forcing current being limited to 200 mA.  
2. Valid over commercial temperature range.  
3. For soldering guidelines and thermal considerations, see the Device Packaging information on the Xilinx website. For Pb free  
packages, see XAPP427.  
Recommended Operating Conditions  
Symbol  
Parameter  
Supply voltage for internal logic  
and input buffers  
Min  
1.7  
1.7  
3.0  
2.3  
1.7  
1.4  
1.7  
Max  
1.9  
1.9  
3.6  
2.7  
1.9  
1.6  
3.6  
Units  
VCC  
Commercial TA = 0°C to +70°C  
Industrial TA = –40°C to +85°C  
V
V
V
V
V
V
V
VCCIO  
Supply voltage for output drivers @ 3.3V operation  
Supply voltage for output drivers @ 2.5V operation  
Supply voltage for output drivers @ 1.8V operation  
Supply voltage for output drivers @ 1.5V operation  
JTAG programming  
VAUX  
DC Electrical Characteristics (Over Recommended Operating Conditions)  
Symbol  
ICCSB  
ICCSB  
ICC  
Parameter  
Standby current Commercial  
Standby current Industrial  
Dynamic current  
Test Conditions  
VCC = 1.9V, VCCIO = 3.6V  
VCC = 1.9V, VCCIO = 3.6V  
f = 1 MHz  
Typical  
Max.  
Units  
µA  
33  
54  
-
150  
300  
410  
27  
µA  
µA  
f = 50 MHz  
-
mA  
pF  
CJTAG  
CCLK  
CIO  
JTAG input capacitance  
Global clock input capacitance  
I/O capacitance  
f = 1 MHz  
-
10  
f = 1 MHz  
-
12  
pF  
f = 1 MHz  
-
10  
pF  
(2)  
IIL  
Input leakage current  
I/O High-Z leakage  
VIN = 0V or VCCIO to 3.9V  
VIN = 0V or VCCIO to 3.9V  
-
+/–1  
+/–1  
µA  
(2)  
IIH  
-
µA  
Notes:  
1. 16-bit up/down, resettable binary counter (one counter per function block) tested at VCC= VCCIO = 1.9V  
2. See Quality and Reliability section of the CoolRunner-II family data sheet  
3
Preliminary Product Specification  
R
XC2C256 CoolRunner-II CPLD  
LVCMOS 3.3V and LVTTL 3.3V DC Voltage Specifications  
Symbol  
VCCIO  
VIH  
Parameter  
Input source voltage  
Test Conditions  
Min.  
Max.  
3.6  
3.9  
0.8  
-
Units  
-
3.0  
V
V
V
V
V
V
V
High level input voltage  
Low level input voltage  
High level output voltage  
-
2
VIL  
-
–0.3  
VOH  
IOH = –8 mA, VCCIO = 3V  
OH = –0.1 mA, VCCIO = 3V  
IOL = 8 mA, VCCIO = 3V  
IOL = 0.1 mA, VCCIO = 3V  
VCCIO – 0.4V  
I
VCCIO – 0.2V  
-
VOL  
Low level output voltage  
-
-
0.4  
0.2  
LVCMOS 2.5V DC Voltage Specifications  
Symbol  
VCCIO  
VIH  
Parameter  
Input source voltage  
Test Conditions  
Min.  
2.3  
Max.  
2.7  
3.9  
0.7  
-
Units  
-
V
V
V
V
V
V
V
High level input voltage  
Low level input voltage  
High level output voltage  
-
1.7  
VIL  
-
–0.3  
VOH  
IOH = –8 mA, VCCIO = 2.3V  
VCCIO – 0.4V  
I
OH = –0.1 mA, VCCIO = 2.3V VCCIO – 0.2V  
-
VOL  
Low level output voltage  
IOL = 8 mA, VCCIO = 2.3V  
IOL = 0.1 mA, VCCIO = 2.3V  
-
-
0.4  
0.2  
LVCMOS 1.8V DC Voltage Specifications  
Symbol  
VCCIO  
VIH  
Parameter  
Input source voltage  
Test Conditions  
Min.  
Max.  
Units  
-
1.7  
1.9  
V
V
V
V
V
V
V
High level input voltage  
Low level input voltage  
High level output voltage  
-
0.65 x VCCIO  
3.9  
VIL  
-
–0.3  
0.35 x VCCIO  
VOH  
IOH = –8 mA, VCCIO = 1.7V  
OH = –0.1 mA, VCCIO = 1.7V  
IOL = 8 mA, VCCIO = 1.7V  
VCCIO – 0.45  
-
-
I
VCCIO – 0.2  
VOL  
Low level output voltage  
-
-
0.45  
0.2  
I
OL = 0.1 mA, VCCIO = 1.7V  
(1)  
LVCMOS 1.5V DC Voltage Specifications  
Symbol  
VCCIO  
VT+  
Parameter  
Test Conditions  
Min.  
Max.  
Units  
Input source voltage  
-
1.4  
1.6  
V
V
V
V
V
Input hysteresis threshold voltage  
-
0.5 x VCCIO  
0.2 x VCCIO  
VCCIO – 0.45  
VCCIO – 0.2  
0.8 x VCCIO  
VT-  
-
0.5 x VCCIO  
VOH  
High level output voltage  
IOH = –8 mA, VCCIO = 1.4V  
OH = –0.1 mA, VCCIO = 1.4V  
-
-
I
DS094 (v2.7) March 7, 2005  
Preliminary Product Specification  
R
XC2C256 CoolRunner-II CPLD  
Symbol  
VOL  
Parameter  
Test Conditions  
Min.  
Max.  
0.4  
Units  
Low level output voltage  
IOL = 8 mA, VCCIO = 1.4V  
OL = 0.1 mA, VCCIO = 1.4V  
-
-
V
V
I
0.2  
Notes:  
1. Hysteresis used on 1.5V inputs.  
Schmitt Trigger Input DC Voltage Specifications  
Symbol  
VCCIO  
VT+  
Parameter  
Test Conditions  
Min.  
1.4  
Max.  
3.9  
Units  
Input source voltage  
-
-
-
V
V
V
Input hysteresis threshold voltage  
0.5 x VCCIO  
0.2 x VCCIO  
0.8 x VCCIO  
0.5 x VCCIO  
VT-  
SSTL2-1 DC Voltage Specifications  
Symbol  
Parameter  
Test Conditions  
Min.  
2.3  
Typ  
Max.  
Units  
VCCIO  
Input source voltage  
Input reference voltage  
Termination voltage  
-
2.5  
2.7  
1.35  
V
V
V
V
V
V
V
(1)  
VREF  
-
1.15  
1.25  
(2)  
VTT  
-
VREF – 0.04  
VREF + 0.18  
–0.3  
1.25  
VREF + 0.04  
3.9  
VIH  
VIL  
High level input voltage  
Low level input voltage  
High level output voltage  
Low level output voltage  
-
-
-
-
-
-
VREF – 0.18  
-
VOH  
VOL  
Notes:  
IOH = –8 mA, VCCIO = 2.3V  
IOL = 8 mA, VCCIO = 2.3V  
VCCIO – 0.62  
-
0.54  
1.  
VREF should track the variations in VCCIO, also peak to peak AC noise on VREF may not exceed ± 2% VREF  
2. VTT of transmitting device must track VREF of receiving devices  
5
Preliminary Product Specification  
R
XC2C256 CoolRunner-II CPLD  
SSTL3-1 DC Voltage Specifications  
Symbol  
Parameter  
Test Conditions  
Min.  
3.0  
Typ  
3.3  
1.5  
1.5  
-
Max.  
3.6  
Units  
VCCIO  
Input source voltage  
Input reference voltage  
Termination voltage  
-
V
V
V
V
V
V
V
(1)  
VREF  
-
1.3  
1.7  
(2)  
VTT  
-
VREF – 0.05  
VREF + 0.2  
–0.3  
VREF + 0.05  
VCCIO + 0.3  
VREF – 0.2  
-
VIH  
VIL  
High level input voltage  
Low level input voltage  
High level output voltage  
Low level output voltage  
-
-
-
VOH  
VOL  
Notes:  
IOH = –8 mA, VCCIO = 3V  
IOL = 8 mA, VCCIO = 3V  
VCCIO – 1.1  
-
-
-
0.7  
1. VREF should track the variations in VCCIO, also peak to peak AC noise on VREF may not exceed ± 2% VREF  
2. VTT of transmitting device must track VREF of receiving devices  
HSTL1 DC Voltage Specifications  
Symbol  
Parameter  
Test Conditions  
Min.  
1.4  
Typ  
Max.  
Units  
VCCIO  
Input source voltage  
Input reference voltage  
Termination voltage  
-
-
-
-
-
1.5  
1.6  
V
V
V
V
V
V
V
(1)  
VREF  
0.68  
0.75  
0.90  
(2)  
VTT  
-
VCCIO x 0.5  
-
VIH  
VIL  
High level input voltage  
Low level input voltage  
High level output voltage  
Low level output voltage  
VREF + 0.1  
–0.3  
-
-
-
-
1.9  
VREF – 0.1  
VOH  
VOL  
Notes:  
IOH = –8 mA, VCCIO = 1.7V VCCIO – 0.4  
IOL = 8 mA, VCCIO = 1.7V  
-
-
0.4  
1. VREF should track the variations in VCCIO, also peak-to-peak AC noise on VREF may not exceed ± 2% VREF  
2. VTT of transmitting device must track VREF of receiving devices  
DS094 (v2.7) March 7, 2005  
Preliminary Product Specification  
R
XC2C256 CoolRunner-II CPLD  
AC Electrical Characteristics Over Recommended Operating Conditions  
-6  
-7  
Symbol  
TPD1  
Parameter  
Propagation delay single p-term  
Min.  
-
Max.  
Min. Max. Units  
5.7  
-
-
6.7  
ns  
ns  
TPD2  
TSUD  
TSU1  
TSU2  
THD  
Propagation delay OR array  
-
6.0  
7.5  
Direct input register clock setup time  
Setup time (single p-term)  
2.6  
2.4  
2.7  
0
-
3.0  
2.8  
3.3  
0
-
ns  
-
-
ns  
Setup time (OR array)  
-
-
ns  
Direct input register hold time  
P-term hold time  
-
-
ns  
TH  
0
-
4.5  
450  
256  
238  
145  
139  
-
0
-
6.0  
300  
152  
141  
114  
108  
-
ns  
TCO  
Clock to output  
-
-
ns  
(1)  
FTOGGLE  
Internal toggle rate  
-
-
MHz  
MHz  
MHz  
MHz  
MHz  
ns  
(2)  
(2)  
FSYSTEM1  
FSYSTEM2  
Maximum system frequency  
-
-
Maximum system frequency  
-
-
(3)  
FEXT1  
Maximum external frequency  
Maximum external frequency  
Direct input register p-term clock setup time  
P-term clock setup time (single p-term)  
P-term clock setup time (OR array)  
Direct input register p-term clock hold time  
P-term clock hold  
-
-
(3)  
FEXT2  
-
-
TPSUD  
TPSU1  
TPSU2  
TPHD  
TPH  
0.9  
0.7  
1.0  
0.9  
0.7  
-
1.7  
1.5  
2.0  
1.2  
1.0  
-
-
-
ns  
-
-
ns  
-
-
ns  
-
-
ns  
TPCO  
P-term clock to output  
6.2  
5.6  
7.0  
7.4  
7.0  
5.5  
-
7.3  
7.0  
8.0  
9.9  
8.1  
7.6  
-
ns  
TOE/TOD  
Global OE to output enable/disable  
P-term OE to output enable/disable  
Macrocell driven OE to output enable/disable  
P-term set/reset to output valid  
Global set/reset to output valid  
Register clock enable setup time  
Register clock enable hold time  
Global clock pulse width High or Low  
P-term pulse width High or Low  
Asynchronous preset/reset pulse width (High or Low)  
Set-up before DataGATE latch assertion  
Hold to DataGATE latch assertion  
DataGATE recovery to new data  
DataGATE low pulse width  
-
-
ns  
TPOE/TPOD  
TMOE/TMOD  
TPAO  
-
-
ns  
-
-
ns  
-
-
ns  
TAO  
-
-
ns  
TSUEC  
THEC  
2.5  
0
3.1  
0
ns  
-
-
ns  
TCW  
1.4  
6.0  
6.0  
0
-
2.2  
7.5  
7.5  
0
-
ns  
TPCW  
-
-
ns  
TAPRPW  
TDGSU  
TDGH  
-
-
ns  
-
-
ns  
4.0  
-
-
6.0  
-
-
ns  
TDGR  
8.2  
-
9.0  
-
ns  
TDGW  
2.5  
1.3  
3.5  
2.0  
ns  
TCDRSU  
CDRST setup time before falling edge GCLK2  
-
-
ns  
7
Preliminary Product Specification  
R
XC2C256 CoolRunner-II CPLD  
Symbol  
-6  
-7  
Parameter  
Min.  
0
Max.  
Min. Max. Units  
TCDRH  
TCONFIG  
Notes:  
Hold time CDRST after falling edge GCLK2  
Configuration time  
-
-
0
-
-
ns  
(4)  
150  
150  
µs  
1. FTOGGLE is the maximum clock frequency to which a T-Flip Flop can reliably toggle (see the CoolRunner-II family data sheet for more  
information).  
2.  
F
SYSTEM1 (1/TCYCLE) is the internal operating frequency for a device fully populated with one 16-bit counter through one p-term per  
macrocell while FSYSTEM2 is through the OR array.  
3. FEXT1 (1/TSU1+TCO) is the maximum external frequency using one p-term while FEXT2 is through the OR array.  
4. Typical configuration current during TCONFIG is approximately 7.7 mA.  
DS094 (v2.7) March 7, 2005  
Preliminary Product Specification  
R
XC2C256 CoolRunner-II CPLD  
(
Internal Timing Parameters  
-6  
-7  
Symbol  
Buffer Delays  
TIN  
Parameter(2)  
Min.  
Max.  
Min.  
Max.  
Units  
Input buffer delay  
-
-
-
-
-
-
-
2.4  
3.1  
1.8  
2.0  
2.1  
2.3  
3.5  
-
-
-
-
-
-
-
2.6  
3.9  
2.7  
3.5  
3.0  
2.6  
4.0  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
TDIN  
Direct data register input delay  
Global Clock buffer delay  
Global set/reset buffer delay  
Global 3-state buffer delay  
Output buffer delay  
TGCK  
TGSR  
TGTS  
TOUT  
TEN  
Output buffer enable/disable delay  
P-term Delays  
TCT  
Control term delay  
-
-
-
1.1  
0.5  
0.3  
-
-
-
1.4  
1.1  
0.5  
ns  
ns  
ns  
TLOGI1  
TLOGI2  
Macrocell Delay  
TPDI  
Single P-term delay adder  
Multiple P-term delay adder  
Input to output valid  
Setup before clock  
Hold after clock  
-
1.3  
0
0.5  
-
1.8  
0
0.7  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
TSUI  
-
-
-
-
THI  
TECSU  
TECHO  
TCOI  
Enable clock setup time  
Enable clock hold time  
Clock to output valid  
Set/reset to output valid  
Clock doubler delay  
0.8  
0
-
1.8  
0
-
-
-
-
0.4  
1.2  
0
-
0.7  
1.5  
0
TAOI  
-
-
TCDBL  
-
-
Feedback Delays  
TF  
Feedback delay  
-
-
1.7  
1.7  
-
-
3.0  
2.5  
ns  
ns  
TOEM  
Macrocell to global OE delay  
I/O Standard Time Adder Delays 1.5V CMOS  
TIN15  
Standard input adder  
Hysteresis input adder  
Output adder  
-
-
-
-
0.8  
3.0  
0.8  
4.0  
-
-
-
-
1.0  
4.0  
1.0  
5.0  
ns  
ns  
ns  
ns  
THYS15  
TOUT15  
TSLEW15  
Output slew rate adder  
I/O Standard Time Adder Delays 1.8V CMOS  
THYS18  
TOUT18  
TSLEW  
Hysteresis input adder  
Output adder  
-
-
-
2.0  
0
-
-
-
3.0  
0
ns  
ns  
ns  
Output slew rate adder  
2.0  
4.0  
9
Preliminary Product Specification  
R
XC2C256 CoolRunner-II CPLD  
Internal Timing Parameters (Continued)  
-6  
-7  
Symbol  
I/O Standard Time Adder Delays 2.5V CMOS  
Parameter(2)  
Min.  
Max.  
Min.  
Max.  
Units  
TIN25  
Standard input adder  
Hysteresis input adder  
Output adder  
-
-
-
-
0.6  
1.5  
0.8  
3.0  
-
-
-
-
1.0  
3.0  
2.0  
4.0  
ns  
ns  
ns  
ns  
THYS25  
TOUT25  
TSLEW25  
Output slew rate adder  
I/O Standard Time Adder Delays 3.3V CMOS/TTL  
TIN33  
Standard input adder  
Hysteresis input adder  
Output adder  
-
-
-
-
0.5  
1.2  
1.2  
3.0  
-
-
-
-
2.0  
3.0  
3.0  
4.0  
ns  
ns  
ns  
ns  
THYS33  
TOUT33  
TSLEW33  
Output slew rate adder  
I/O Standard Time Adder Delays HSTL, SSTL  
-
-
-
-
-
-
-
-
-
-
-
-
SSTL2-1  
SSTL3-1  
HSTL-1  
Notes:  
Input adder to TIN, TDIN, TGCK, TGSR,TGTS  
0.4  
-0.5  
0.4  
-0.5  
0.6  
0
1.0  
0.0  
1.0  
0.0  
1.0  
0
ns  
ns  
ns  
ns  
ns  
ns  
Output adder to TOUT  
Input adder to TIN, TDIN, TGCK, TGSR,TGTS  
Output adder to TOUT  
Input adder to TIN, TDIN, TGCK, TGSR,TGTS  
Output adder to TOUT  
1. 1.5 ns input pin signal rise/fall.  
Switching Characteristics  
AC Test Circuit  
V
CC  
VCC = VCCIO = 1.8V, T = 25oC  
5.5  
R
1
Device  
Under Test  
Test Point  
5.0  
4.5  
4.0  
R
C
L
2
Output Type  
LVTTL33  
R
R
C
L
1
2
268  
275Ω  
188Ω  
235Ω  
275Ω  
35 pF  
35 pF  
35pF  
35pF  
35pF  
LVCMOS33  
LVCMOS25  
LVCMOS18  
LVCMOS15  
188Ω  
112.5Ω  
150Ω  
112.5Ω  
150Ω  
3.5  
3.0  
C
includes test fixtures and probe capacitance.  
L
1.5 nsec maximum rise/fall times on inputs.  
1
2
4
8
16  
DS_ACT_08_14_02  
Figure 3: AC Load Circuit  
Number of Outputs Switching  
DS092_02_092302  
Figure 2: Derating Curve for TPD  
DS094 (v2.7) March 7, 2005  
Preliminary Product Specification  
R
XC2C256 CoolRunner-II CPLD  
3.3V  
2.5V  
60  
50  
40  
30  
20  
10  
0
1.8V  
Iol  
1.5V  
0
.5  
1.0  
1.5  
2.0  
2.5  
3.0  
3.5  
VO (Output Volts)  
XC256_VoIo_all_020703  
Figure 4: Typical I/V Curve for XC2C256  
11  
Preliminary Product Specification  
R
XC2C256 CoolRunner-II CPLD  
11  
Pin Descriptions (Continued)  
Function Macro-  
Pin Descriptions  
Function Macro-  
I/O  
I/O  
Block  
cell  
VQ100 CP132 TQ144 PQ208 FT256 Bank  
Block  
cell  
VQ100 CP132 TQ144 PQ208 FT256 Bank  
3
1
-
-
-
B5  
-
136  
135  
134  
-
196  
195  
194  
193  
192  
191  
-
A6  
D7  
B7  
E9  
A7  
D8  
-
2
2
2
2
2
2
-
1
1
-
-
-
-
-
2
208  
206  
205  
203  
202  
-
B3  
B4  
C4  
A2  
A3  
A4  
-
2
2
2
2
2
2
-
3
2
1
2
-
3
3
-
1(GSR)  
3
99  
-
A3  
-
143  
3
4
-
A5  
-
1
4
142  
3
5
93  
133  
1
5
-
-
-
3
6
C6  
-
1
6
97  
-
B4  
-
140  
3
7
-
-
-
-
1
7
-
3
8
-
-
-
-
1
8
-
-
-
-
-
-
3
9
-
-
-
-
-
-
1
9
-
-
-
-
-
-
3
10  
11  
12  
13  
14  
15  
16  
1
-
-
-
-
-
-
1
10  
11  
12  
13  
14  
15  
16  
1
-
-
-
-
-
-
3
-
-
-
-
-
-
1
-
-
-
-
-
-
3
92  
-
-
-
189  
188  
187  
186  
185  
15  
16  
17  
18  
19  
20  
-
B8  
C8  
A8  
E11  
E10  
F2  
F3  
G4  
G3  
F5  
G5  
-
2
2
2
2
2
2
2
2
2
2
2
-
1
96  
95  
94  
-
-
139  
201  
200  
199  
198  
197  
3
B5  
A5  
E8  
B6  
C7  
D3  
C3  
E3  
B2  
D4  
D2  
-
2
2
2
2
2
2
2
2
2
2
2
-
3
B6  
A6  
C7  
B7  
E3  
-
-
1
-
138  
3
91  
-
132  
-
1
A4  
-
137  
-
3
1
3
90  
8
9
10  
-
131  
11  
12  
13  
14  
15  
16  
-
1
-
C5  
A1  
-
-
4
2(GTS2)  
1
-
2
-
4
2
2
2
4
4
3
E2  
E1  
F3  
F2  
-
2(GTS3)  
3
2
-
B2  
B1  
C3  
-
3
4
5
-
5
4
4
2
4
6
4
5
11  
12  
-
2(GTS0)  
5
3
-
7
4
6
2
6
8
4
7
2
7
-
-
-
-
4
8
-
-
-
-
-
-
2
8
-
-
-
-
-
-
4
9
-
-
-
-
-
-
2
9
-
-
-
-
-
-
4
10  
11  
12  
13  
14  
15  
16  
-
-
-
-
-
-
2
10  
11  
12  
13  
14  
15  
16  
-
-
-
-
-
-
4
-
-
-
-
-
-
2
-
-
-
-
-
-
4
-
F1  
G1  
-
17  
-
21  
22  
23  
-
H2  
H4  
H3  
H1  
H5  
2
2
2
2
2
2(GTS1)  
4
-
C2  
C1  
D2  
-
6
7
9
10  
-
9
E5  
B1  
E4  
C1  
E2  
2
2
2
2
2
4
13  
-
2
2
2
2
10  
12  
14  
-
4
18  
-
6
7
-
4
-
-
4
-
-
-
25  
D1  
DS094 (v2.7) March 7, 2005  
Preliminary Product Specification  
R
XC2C256 CoolRunner-II CPLD  
Pin Descriptions (Continued)  
Pin Descriptions (Continued)  
Function Macro-  
I/O  
Function Macro-  
I/O  
Block  
cell  
VQ100 CP132 TQ144 PQ208 FT256 Bank  
Block  
cell  
VQ100 CP132 TQ144 PQ208 FT256 Bank  
5
1
-
-
L3  
-
33  
-
49  
48  
47  
46  
45  
44  
-
R1  
N4  
N2  
M3  
P1  
M2  
-
1
1
1
1
1
1
-
7
1
-
-
-
-
-
-
37  
36  
35  
34  
32  
31  
-
K4  
L2  
K3  
L1  
K5  
K2  
-
1
1
1
1
1
1
-
5
2
-
-
7
2
5
3
-
7
3
-
-
-
5(GCK1)  
4
23  
L2  
L1  
K3  
-
32  
31  
30  
-
7
4
-
-
-
5
5
7
5
19  
18  
-
J2  
J1  
-
26  
25  
-
5(GCK0)  
6
22  
-
7
6
5
5
5
5
5
5
5
5
5
5
6
7
7
7
8
-
-
-
-
-
-
7
8
-
-
-
-
-
-
9
-
-
-
-
-
-
7
9
-
-
-
-
-
-
10  
11  
12  
13  
14  
15  
16  
1
-
-
-
-
-
-
7
10  
11  
12  
13  
14  
15  
16  
1
-
-
-
-
-
-
-
-
-
-
-
-
7
17  
16  
15  
14  
-
H3  
H2  
H1  
G3  
G2  
-
24  
23  
22  
21  
20  
19  
44  
45  
46  
-
30  
29  
28  
27  
-
J4  
K1  
J3  
J2  
J5  
J1  
R6  
N6  
R3  
M6  
T3  
P6  
-
1
1
1
1
1
1
1
1
1
1
1
1
-
-
-
-
43  
41  
40  
39  
38  
50  
51  
L3  
N1  
L4  
M1  
L5  
N3  
P2  
1
1
1
1
1
1
1
7
-
-
-
7
-
-
28  
-
7
-
-
7
-
K1  
M1  
M2  
-
7
-
-
-
34  
35  
8
-
N4  
-
64  
65  
66  
67  
69  
70  
-
6
2
24  
8
2
-
(CDRST)  
8
3
-
-
6
3
4
-
27  
-
-
N2  
-
-
38  
-
54  
55  
56  
57  
-
P4  
P5  
R2  
T1  
-
1
1
1
1
-
8
4
-
-
6(GCK2)  
8
5
-
-
48  
49  
-
6
5
8
6
32  
-
-
6
6
-
-
-
8
7
-
6
7
-
-
-
8
8
-
-
-
-
-
-
6
8
-
-
-
-
-
-
8
9
-
-
-
-
-
-
6
9
-
-
-
-
-
-
8
10  
11  
12  
13  
14  
15  
16  
-
-
-
-
-
-
6
10  
11  
12  
13  
14  
15  
16  
-
-
-
-
-
-
8
33  
34  
35  
36  
37  
-
M5  
N5  
P5  
M6  
N6  
-
50  
51  
52  
-
71  
72  
73  
74  
75  
76  
T4  
P7  
T5  
N7  
R7  
M7  
1
1
1
1
1
1
6
-
-
-
-
-
-
8
6(DGE)  
28  
-
P2  
M3  
N3  
P3  
M4  
39  
40  
41  
42  
43  
58  
60  
61  
62  
63  
T2  
N5  
R4  
M5  
R5  
1
1
1
1
1
8
6
6
6
6
8
29  
-
8
-
8
-
30  
13  
Preliminary Product Specification  
R
XC2C256 CoolRunner-II CPLD  
Pin Descriptions (Continued)  
Pin Descriptions (Continued)  
Function Macro-  
I/O  
Function Macro-  
I/O  
Block  
cell  
VQ100 CP132 TQ144 PQ208 FT256 Bank  
Block  
11  
11  
11  
11  
11  
11  
11  
11  
11  
11  
11  
11  
11  
11  
11  
11  
12  
12  
12  
12  
12  
12  
12  
12  
12  
12  
12  
12  
12  
12  
12  
12  
cell  
VQ100 CP132 TQ144 PQ208 FT256 Bank  
9
1
78  
79  
-
C12  
B12  
-
112  
113  
-
160  
161  
162  
163  
164  
165  
-
B13  
B14  
C13  
A15  
C12  
B12  
-
2
2
2
2
2
2
-
1
-
-
B10  
-
-
B11  
D11  
A11  
D10  
B10  
E12  
-
2
2
2
2
2
2
-
9
2
2
-
173  
174  
175  
-
9
3
3
-
A10  
-
9
4
80  
A12  
114  
4
-
-
-
120  
121  
-
9
5
5
-
C9  
9
6
81  
-
C11  
115  
-
6
-
-
-
9
7
-
7
-
-
-
9
8
-
-
-
-
-
-
8
-
-
-
-
-
-
9
9
-
-
-
-
-
-
-
9
-
-
-
-
-
-
9
10  
11  
12  
13  
14  
15  
16  
1
-
-
-
-
-
10  
11  
12  
13  
14  
15  
16  
1
-
-
-
-
-
-
9
-
-
-
166  
167  
168  
169  
170  
171  
159  
158  
155  
154  
153  
152  
-
D13  
A14  
E13  
A13  
C11  
A12  
A16  
B15  
C14  
G11  
B16  
D15  
-
2
2
2
2
2
2
2
2
2
2
2
2
-
85  
86  
87  
89  
-
A8  
124  
125  
126  
128  
129  
130  
-
178  
179  
180  
182  
183  
184  
145  
144  
143  
142  
140  
139  
-
F12  
B9  
2
2
2
2
2
2
2
2
2
2
2
2
-
9
82  
-
B11  
-
116  
117  
118  
119  
-
B8  
9
C8  
C9  
C10  
A9  
9
-
A11  
-
-
9
-
-
9
-
C10  
A13  
B13  
C13  
C14  
D12  
D13  
-
-
-
D9  
F15  
G14  
E16  
H12  
F16  
H16  
-
10  
10  
10  
10  
10  
10  
10  
10  
10  
10  
10  
10  
10  
10  
10  
10  
77  
76  
74  
73  
72  
71  
-
111  
110  
107  
106  
105  
104  
-
-
-
2
2
-
-
100  
-
3
3
-
-
4
4
-
-
-
5
5
-
F12  
-
6
6
-
F13  
-
7
7
-
-
-
8
-
-
-
-
-
-
8
-
-
-
-
-
-
9
-
-
-
-
-
-
9
-
-
-
-
-
-
10  
11  
12  
13  
14  
15  
16  
-
-
-
-
-
-
10  
11  
12  
13  
14  
15  
16  
-
-
F14  
G12  
G13  
-
-
-
-
-
151  
150  
149  
148  
147  
146  
E14  
C16  
F14  
F13  
E15  
G13  
2
2
2
2
2
2
68  
-
98  
97  
96  
95  
94  
-
138  
137  
136  
135  
134  
-
G15  
H13  
G16  
H14  
H15  
J12  
2
2
2
2
2
2
70  
-
D14  
-
103  
-
67  
66  
65  
-
-
E12  
-
102  
-
-
-
-
E13  
101  
-
DS094 (v2.7) March 7, 2005  
Preliminary Product Specification  
R
XC2C256 CoolRunner-II CPLD  
Pin Descriptions (Continued)  
Pin Descriptions (Continued)  
Function Macro-  
I/O  
Function Macro-  
I/O  
Block  
13  
13  
13  
13  
13  
13  
13  
13  
13  
13  
13  
13  
13  
13  
13  
13  
14  
14  
14  
14  
14  
14  
14  
14  
14  
14  
14  
14  
14  
14  
14  
14  
cell  
VQ100 CP132 TQ144 PQ208 FT256 Bank  
Block  
cell  
VQ100 CP132 TQ144 PQ208 FT256 Bank  
1
-
53  
-
N13  
75  
76  
77  
-
107  
108  
109  
110  
111  
112  
-
R15  
T16  
N14  
R16  
N15  
M15  
-
1
1
1
1
1
1
-
15  
1
-
-
-
-
83  
-
118  
119  
120  
121  
122  
123  
-
L15  
L13  
M12  
M16  
K14  
L16  
-
1
1
1
1
1
1
-
2
N14  
15  
2
L14  
3
M12  
15  
3
-
-
4
54  
-
-
15  
4
-
-
-
5
M13  
78  
79  
-
15  
5
-
-
-
6
55  
-
-
15  
6
-
-
-
7
-
15  
7
-
-
-
8
-
-
-
-
-
-
15  
8
-
-
-
-
-
-
-
9
-
-
-
-
-
-
15  
9
-
-
-
-
-
10  
11  
12  
13  
14  
15  
16  
1
-
-
-
-
-
-
15  
10  
11  
12  
13  
14  
15  
16  
1
-
-
-
-
-
-
-
-
-
-
-
-
15  
58  
59  
60  
61  
63  
64  
-
K13  
K14  
J12  
J13  
H13  
H12  
-
85  
86  
87  
88  
91  
92  
-
125  
126  
127  
128  
-
K15  
L12  
K16  
J14  
J15  
J13  
P10  
R10  
T10  
R9  
N9  
M8  
-
1
1
1
1
1
1
1
1
1
1
1
1
-
-
M14  
80  
81  
82  
-
113  
114  
115  
116  
117  
106  
103  
102  
101  
100  
-
M13  
P16  
N16  
L14  
M14  
P15  
P14  
P13  
R13  
N13  
R14  
-
1
1
1
1
1
1
1
1
1
1
1
-
15  
56  
-
-
15  
L12  
15  
-
-
15  
-
L13  
-
15  
131  
90  
89  
88  
87  
86  
85  
-
52  
-
P14  
74  
71  
70  
69  
-
16  
2
-
16  
2
-
-
-
3
50  
-
P12  
16  
3
-
M8  
-
-
4
M11  
16  
4
-
-
5
49  
-
N11  
16  
5
43  
42  
-
N8  
-
60  
59  
-
6
P11  
68  
-
16  
6
7
-
-
-
16  
7
-
8
-
-
-
-
-
-
16  
8
-
-
-
-
-
-
9
-
-
-
-
-
-
16  
9
-
-
-
-
-
-
10  
11  
12  
13  
14  
15  
16  
-
-
-
-
-
-
16  
10  
11  
12  
13  
14  
15  
16  
-
-
-
-
-
-
-
-
-
-
-
-
16  
41  
40  
39  
-
P8  
M7  
N7  
-
58  
57  
56  
-
84  
83  
82  
80  
78  
77  
T8  
P8  
R8  
T7  
N8  
T6  
1
1
1
1
1
1
-
-
-
-
99  
97  
95  
-
T15  
R12  
N11  
M11  
N10  
1
1
1
1
1
16  
-
66  
64  
-
16  
46  
44  
-
P10  
-
16  
16  
-
-
54  
53  
P9  
61  
91  
16  
-
P6  
Notes:  
1. GTS = global output enable, GSR = global reset/set, GCK =  
global clock, CDRST = clock divide reset, DGE = DataGATE  
enable.  
15  
Preliminary Product Specification  
R
XC2C256 CoolRunner-II CPLD  
XC2C256 JTAG, Power/Ground, No Connect Pins and Total User I/O  
Pin Type  
VQ100  
CP132  
M10  
TQ144  
PQ208  
FT256  
TCK  
TDI  
48  
67  
98  
94  
P12  
45  
83  
M9  
63  
R11  
TDO  
TMS  
B9  
122  
176  
A10  
47  
N10  
65  
8
96  
N12  
F4  
VAUX (JTAG supply voltage)  
Power internal (VCC  
5
D3  
11  
)
26, 57  
20, 38, 51  
P1, K12, A2  
1, 37, 84  
27, 55, 73, 93  
1, 53, 124  
P3, K13, D12, D5  
Power Bank 1 I/O (VCCIO1  
Power Bank 2 I/O (VCCIO2  
Ground  
)
J3, P7,  
G14, P13  
33, 59, 79, 92,  
105, 132  
J6, K6, L7, L8, J11,  
K11, L10, L9  
)
88, 98  
A14, C4, A7 109, 127, 141  
26, 133, 157,  
172, 181, 204  
F7, F8, G6, H6, F10,  
F9, H11  
21, 25, 31,  
62, 69, 75,  
84, 100  
K2, N1, P4, 29, 36, 47, 62,  
13, 24, 42, 52,  
F11, F6, G10, G7, G8,  
G9, H10, H7, H8, H9,  
J10, J7, J8, J9, K10,  
K7, K8, K9, L11, L6  
N9, N12,  
J14, H14,  
E14, B14,  
A9, B3  
72, 89, 90, 99, 68, 81, 93, 104,  
108, 123, 144  
129, 130, 141,  
156, 177, 190,  
207  
No connects  
Total user I/O  
-
-
-
-
A1, C2, E6, D1, E1, G2,  
F1, G1, M4, T9, P9,  
M9, M10, T11, T12,  
T13, P11, T14, J16,  
K12, D16, G12, C15,  
D14, D6, C6, E7, C5  
80  
106  
118  
173  
184  
DS094 (v2.7) March 7, 2005  
Preliminary Product Specification  
R
XC2C256 CoolRunner-II CPLD  
Ordering Information  
Commercia  
l (C)  
Pin/Ball  
Spacing (C/Watt) (C/Watt)  
θJA  
θJC  
10.9  
10.9  
Package Body  
Dimensions  
Industrial  
(I)(1)  
Part Number  
Package Type  
I/O  
XC2C256-6VQ100C  
0.5mm  
43.1  
43.1  
Very Thin Quad Flat  
Pack  
14mm x 14mm  
80  
C
XC2C256-7VQ100C  
0.5mm  
Very Thin Quad Flat  
Pack  
14mm x 14mm  
80  
C
XC2C256-6CP132C  
XC2C256-7CP132C  
XC2C256-6TQ144C  
XC2C256-7TQ144C  
XC2C256-6PQ208C  
0.5mm  
0.5mm  
0.5mm  
0.5mm  
0.5mm  
65.0  
65.0  
37.2  
37.2  
36.9  
15.0  
15.0  
7.2  
Chip Scale Package  
Chip Scale Package  
Thin Quad Flat Pack  
Thin Quad Flat Pack  
8mm x 8mm  
8mm x 8mm  
106  
106  
118  
118  
C
C
C
C
C
20mm x 20mm  
20mm x 20mm  
7.2  
9.7  
Plastic Quad Flat  
Pack  
28mm x 28mm 173  
XC2C256-7PQ208C  
0.5mm  
36.9  
9.7  
Plastic Quad Flat  
Pack  
28mm x 28mm 173  
C
XC2C256-6FT256C  
XC2C256-7FT256C  
1.0mm  
1.0mm  
34.6  
34.6  
6.1  
6.1  
Fine Pitch Thin BGA  
Fine Pitch Thin BGA  
17mm x 17mm 184  
17mm x 17mm 184  
C
C
XC2C256-6VQG100C  
XC2C256-7VQG100C  
XC2C256-6CPG132C  
XC2C256-7CPG132C  
XC2C256-6TQG144C  
XC2C256-7TQG144C  
XC2C256-6PQG208C  
XC2C256-7PQG208C  
XC2C256-6FTG256C  
XC2C256-7FTG256C  
0.5mm  
0.5mm  
0.5mm  
0.5mm  
0.5mm  
0.5mm  
0.5mm  
0.5mm  
1.0mm  
1.0mm  
43.1  
43.1  
65.0  
65.0  
37.2  
37.2  
36.9  
36.9  
34.6  
34.6  
10.9  
10.9  
15.0  
15.0  
7.2  
Very Thin Quad Flat  
Pack; Pb-free  
14mm x 14mm  
14mm x 14mm  
8mm x 8mm  
80  
80  
C
C
C
C
C
C
C
C
C
C
Very Thin Quad Flat  
Pack; Pb-free  
Chip Scale Package;  
Pb-free  
106  
106  
118  
118  
Chip Scale Package;  
Pb-free  
8mm x 8mm  
Thin Quad Flat Pack;  
Pb-free  
20mm x 20mm  
20mm x 20mm  
7.2  
Thin Quad Flat Pack;  
Pb-free  
9.7  
Plastic Quad Flat  
Pack; Pb-free  
28mm x 28mm 173  
28mm x 28mm 173  
17mm x 17mm 184  
17mm x 17mm 184  
9.7  
Plastic Quad Flat  
Pack; Pb-free  
6.1  
Fine Pitch Thin BGA;  
Pb-free  
6.1  
Fine Pitch Thin BGA;  
Pb-free  
XC2C256-7VQ100I  
0.5mm  
43.1  
10.9  
Very Thin Quad Flat  
Pack  
14mm x 14mm  
80  
I
XC2C256-7CP132I  
XC2C256-7TQ144I  
XC2C256-7PQ208I  
0.5mm  
0.5mm  
0.5mm  
65.0  
37.2  
36.9  
15.0  
7.2  
Chip Scale Package  
Thin Quad Flat Pack  
8mm x 8mm  
106  
118  
I
I
I
20mm x 20mm  
9.7  
Plastic Quad Flat  
Pack  
28mm x 28mm 173  
XC2C256-7FT256I  
1.0mm  
34.6  
6.1  
Fine Pitch Thin BGA  
17mm x 17mm 184  
I
17  
Preliminary Product Specification  
R
XC2C256 CoolRunner-II CPLD  
Commercia  
l (C)  
Pin/Ball  
Spacing (C/Watt) (C/Watt)  
θJA  
θJC  
10.9  
15.0  
7.2  
Package Body  
Dimensions  
Industrial  
(I)(1)  
Part Number  
Package Type  
I/O  
XC2C256-7VQG100I  
0.5mm  
0.5mm  
0.5mm  
0.5mm  
1.0mm  
43.1  
65.0  
37.2  
36.9  
34.6  
Very Thin Quad Flat  
Pack; Pb-free  
14mm x 14mm  
80  
I
I
I
I
I
XC2C256-7CPG132I  
XC2C256-7TQG144I  
XC2C256-7PQG208I  
XC2C256-7FTG256I  
Notes:  
Chip Scale Package;  
Pb-free  
8mm x 8mm  
106  
118  
Thin Quad Flat Pack;  
Pb-free  
20mm x 20mm  
9.7  
Plastic Quad Flat  
Pack; Pb-free  
28mm x 28mm 173  
17mm x 17mm 184  
6.1  
Fine Pitch Thin BGA;  
Pb-free  
1. C = Commercial (TA = 0°C to +70°C); I = Industrial (TA = –40°C to +85°C).  
Pb-  
XC2C128 -6 TQ  
G
144  
C
Free Example:  
Standard Example: XC2C128 -6 TQ 144  
C
Device  
Device  
Speed Grade  
Package Type  
Speed Grade  
Package Type  
Number of Pins  
Temperature Range  
-Free  
Pb  
Number of Pins  
Temperature Range  
Device Part Marking  
R
Device Type  
Package  
XC2Cxxx  
TQ144  
This line not  
related to device  
part number  
Speed  
7C  
Operating Range  
Part marking for non-chip scale package  
Figure 5: Sample Package with Part Marking  
Note: Due to the small size of chip scale packages, the complete ordering part number cannot be included on the package  
marking. Part marking on chip scale packages by line are:  
Line 1 = X (Xilinx logo) then truncated part number  
Line 2 = Not related to device part number  
Line 3 = Not related to device part number  
1. Line 4 = Package code, speed, operating temperature,  
three digits not related to device part number. Package  
codes: C5 = CP132, C6 = CPG132.  
DS094 (v2.7) March 7, 2005  
Preliminary Product Specification  
R
XC2C256 CoolRunner-II CPLD  
(1)  
(1)  
(1)  
(1)  
1
2
3
4
5
6
7
8
GND  
I/O  
I/O  
I/O  
I/O  
I/O  
GND  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
GND  
I/O  
I/O  
I/O  
I/O  
VCC  
I/O  
75  
74  
73  
72  
71  
70  
69  
68  
67  
66  
65  
64  
63  
62  
61  
60  
59  
58  
57  
56  
55  
54  
53  
52  
51  
I/O  
I/O  
I/O  
I/O  
V
AUX  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
VQ100  
Top View  
VCCIO1  
GND  
I/O  
I/O  
I/O  
I/O  
(2)  
I/O  
(2)  
I/O  
(4)  
I/O  
VCCIO1  
GND  
(1) - Global Output Enable  
(2) - Global Clock  
(3) - Global Set/Reset  
(4) - Clock Divide Reset  
(5) - Data Gate  
Figure 6: VQ100 Very Thin Quad Flat Pack  
19  
Preliminary Product Specification  
R
XC2C256 CoolRunner-II CPLD  
VCCIO1  
I/O  
VCCIO1  
I/O  
VCC  
GND  
I/O  
I/O(5)  
I/O(2)  
I/O(4)  
I/O  
I/O  
I/O  
GND  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
GND  
TDI  
I/O  
I/O  
I/O  
I/O  
I/O  
GND  
I/O  
I/O  
I/O  
I/O  
P
N
M
L
TMS  
TCK  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O(2)  
GND  
I/O  
I/O  
I/O  
I/O  
I/O(2)  
VCC  
K
J
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
VCCIO1  
I/O  
I/O  
I/O  
GND  
GND  
H
G
F
CP132  
Bottom View  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
VCCIO1  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
GND  
E
D
C
B
A
I/O  
I/O  
I/O  
I/O  
I/O  
VAUX  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O(1)  
I/O(1) VCCIO2  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O(1)  
VCC  
GND  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
TDO  
GND  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
GND  
VCCIO2  
I/O  
I/O(1)  
I/O(3)  
VCCIO2  
(1) - Global Output Enable  
(2) - Global Clock  
(3) - Global Set/Reset  
(4) - Clock Divide Reset  
(5) - DataGATE Enable  
Figure 7: CP132 Chip Scale Package  
DS094 (v2.7) March 7, 2005  
Preliminary Product Specification  
R
XC2C256 CoolRunner-II CPLD  
V
I/O  
I/O  
CC  
(1)  
(1)  
1
2
3
4
5
6
7
8
GND  
108  
I/O  
107  
106  
105  
104  
I/O  
I/O  
I/O  
I/O  
I/O  
(1)  
(1)  
I/O  
I/O  
I/O  
103  
I/O  
I/O  
I/O  
GND  
I/O  
I/O  
I/O  
I/O  
I/O  
V
I/O  
I/O  
GND  
GND  
I/O  
V
102  
101  
100  
99  
98  
97  
96  
95  
94  
93  
92  
91  
90  
89  
88  
87  
86  
85  
84  
83  
82  
81  
80  
79  
78  
77  
76  
75  
74  
73  
AUX  
I/O  
9
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
CCIO1  
TQ144  
Top View  
I/O  
I/O  
I/O  
V
CC  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
V
CCIO1  
I/O  
GND  
(2)  
I/O  
I/O  
(2)  
I/O  
I/O  
I/O  
(4)  
I/O  
GND  
V
CCIO1  
(1) - Global Output Enable  
(2) - Global Clock  
(3) - Global Set/Reset  
(4) - Clock Divide Reset  
(5) - DataGATE Enable  
Figure 8: TQ144 Thin Quad Flat Pack  
21  
Preliminary Product Specification  
R
XC2C256 CoolRunner-II CPLD  
VCC  
I/O  
I/O(1)  
I/O  
I/O(1)  
I/O  
I/O(1)  
I/O  
I/O(1)  
I/O  
VAUX  
I/O  
GND  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
1
2
3
4
5
6
7
8
GND  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
GND  
I/O  
I/O  
156  
155  
154  
153  
152  
151  
150  
149  
148  
147  
146  
145  
144  
143  
142  
141  
140  
139  
138  
137  
136  
135  
134  
133  
132  
131  
130  
129  
128  
127  
126  
125  
124  
123  
122  
121  
120  
119  
118  
117  
116  
115  
114  
113  
112  
111  
110  
109  
108  
107  
106  
105  
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
51  
52  
I/O  
I/O  
I/O  
I/O  
I/O  
GND  
I/O  
VCCIO2  
I/O  
VCCIO2  
VCCIO1  
I/O  
GND  
GND  
I/O  
I/O  
I/O  
I/O  
VCC  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
PQ208  
Top View  
I/O  
VCCIO1  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
GND  
I/O  
I/O(2)  
I/O  
I/O(2)  
I/O  
I/O  
I/O  
I/O  
I/O(4)  
GND  
I/O  
VCCIO1  
(1) - Global Output Enable  
(2) - Global Clock  
(3) - Global Set/Reset  
(4) - Clock Divide Reset  
(5) - DataGATE Enable  
Figure 9: PQ208 Quad Flat Package  
DS094 (v2.7) March 7, 2005  
Preliminary Product Specification  
R
XC2C256 CoolRunner-II CPLD  
TDO  
I/O  
I/O  
I/O  
I/O  
I/O  
NC  
I/O  
I/O  
I/O  
NC  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
NC  
I/O  
I/O  
NC  
I/O  
I/O  
I/O  
NC  
I/O  
I/O  
A
B
C
D
E
F
I/O  
I/O  
I/O  
I/O(3)  
I/O  
I/O  
I/O(1)  
I/O  
I/O  
I/O  
I/O  
NC  
I/O  
I/O  
I/O  
I/O  
I/O  
NC  
I/O  
I/O  
I/O  
I/O  
I/O  
VCC  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
NC  
NC  
NC  
VCC  
I/O(1)  
I/O  
I/O(1)  
I/O(1)  
I/O  
NC  
NC  
NC  
VCCIO2  
VCCIO2 VCCIO2 VCCIO2 GND  
VAUX  
I/O  
GND  
GND  
GND  
I/O  
I/O  
I/O  
I/O  
I/O  
NC  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
NC  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
NC  
I/O  
I/O  
NC  
I/O  
I/O  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND VCCIO2  
GND VCCIO2  
GND VCCIO1  
GND VCCIO1  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
NC  
I/O  
I/O  
I/O  
I/O  
G
H
J
VCCIO2  
VCCIO1  
VCCIO1  
GND  
GND  
I/O  
GND  
VCC  
I/O  
K
L
VCCIO1  
VCCIO1 VCCIO1 VCCIO1 GND  
NC  
I/O  
I/O  
I/O  
I/O  
NC  
I/O  
I/O  
I/O  
I/O  
I/O(2)  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
NC  
I/O  
I/O  
I/O  
I/O  
NC  
I/O  
TMS  
TCK  
I/O  
I/O  
I/O  
NC  
TDI  
NC  
NC  
I/O  
NC  
I/O  
NC  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O(2)  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
M
N
P
R
T
I/O(4)  
I/O  
I/O(2)  
I/O  
VCC  
I/O  
I/O(5)  
NC  
I/O  
I/O  
FT256 Bottom View  
(1) - Global Output Enable  
(2) - Global Clock  
(3) - Global Set/Reset  
(4) - Clock Divide Reset  
(5) - DataGATE Enable  
Figure 10: FT256 Fine Pitch Thin BGA  
Additional Information  
CoolRunner-II Data Sheets and Application Notes  
Device Packages  
23  
Preliminary Product Specification  
R
XC2C256 CoolRunner-II CPLD  
Revision History  
The following table shows the revision history for this document.  
Date  
Version  
1.0  
Revision  
05/09/02  
05/13/02  
10/31/02  
03/17/03  
04/02/03  
01/26/04  
02/26/04  
08/03/04  
08/19/04  
10/01/04  
03/07/05  
Initial Xilinx release.  
1.1  
Updated AC Electrical Characteristics and added new parameters.  
Corrected package user I/O, added Voltage Referenced DC tables.  
Added Characterization numbers for product release and device part marking  
Updated TSOL max from 260 to 220. Changed ICCSB units from mA to µA.  
Updated Device Part Marking. Updated links and Tsol.  
1.2  
2.0  
2.1  
2.2  
2.3  
Corrected Theta JC value on XC2C256-7TQ144.  
2.4  
Pb-free documentation  
2.5  
Changes to ICCSB maximum specifications in DC Electrical Characteristics table, on page 3.  
Add Asynchronous Preset/Reset Pulse Width specification to AC Electrical Characteristics.  
Removed -5 speed grade. Changes to Table 1, I/O Standards.  
2.6  
2.7  
DS094 (v2.7) March 7, 2005  
Preliminary Product Specification  
配单直通车
XC2C256-7VQ100C产品参数
型号:XC2C256-7VQ100C
是否无铅: 含铅
是否Rohs认证: 不符合
生命周期:Active
IHS 制造商:XILINX INC
零件包装代码:QFP
包装说明:TFQFP, TQFP100,.63SQ
针数:100
Reach Compliance Code:not_compliant
ECCN代码:EAR99
HTS代码:8542.39.00.01
Factory Lead Time:12 weeks
风险等级:1.69
Is Samacsys:N
其他特性:REAL DIGITAL DESIGN TECHNOLOGY
系统内可编程:YES
JESD-30 代码:S-PQFP-G100
JESD-609代码:e0
JTAG BST:YES
长度:14 mm
湿度敏感等级:3
专用输入次数:
I/O 线路数量:80
宏单元数:256
端子数量:100
最高工作温度:70 °C
最低工作温度:
组织:0 DEDICATED INPUTS, 80 I/O
输出函数:MACROCELL
封装主体材料:PLASTIC/EPOXY
封装代码:TFQFP
封装等效代码:TQFP100,.63SQ
封装形状:SQUARE
封装形式:FLATPACK, THIN PROFILE, FINE PITCH
峰值回流温度(摄氏度):225
电源:1.5/3.3,1.8 V
可编程逻辑类型:FLASH PLD
传播延迟:7.5 ns
认证状态:Not Qualified
座面最大高度:1.2 mm
子类别:Programmable Logic Devices
最大供电电压:1.9 V
最小供电电压:1.7 V
标称供电电压:1.8 V
表面贴装:YES
技术:CMOS
温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn85Pb15)
端子形式:GULL WING
端子节距:0.5 mm
端子位置:QUAD
处于峰值回流温度下的最长时间:30
宽度:14 mm
Base Number Matches:1
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