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Virtex-4 FPGA Data Sheet:

DC and Switching Characteristics

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DS302 (v3.7) September 9, 2009

Product Specification

Virtex-4 FPGA Electrical Characteristics

Virtex®-4 FPGAs are available in -12, -11, and -10 speed

grades, with -12 having the highest performance.

This Virtex-4 FPGA Data Sheet is part of an overall set of

documentation on the Virtex-4 family of FPGAs that is avail-

able on the Xilinx website:

Virtex-4 FPGA DC and AC characteristics are specified for

both commercial and industrial grades. Except the operat-

ing temperature range or unless otherwise noted, all the DC

and AC electrical parameters are the same for a particular

speed grade (that is, the timing characteristics of a -10

speed grade industrial device are the same as for a -10

speed grade commercial device). However, only selected

speed grades and/or devices might be available in the

industrial range.

•

Virtex-4 Family Overview, DS112

Virtex-4 FPGA User Guide, UG070

Virtex-4 FPGA Configuration Guide, UG071

XtremeDSP for Virtex-4 FPGAs User Guide, UG073

Virtex-4 FPGA Packaging and Pinout Specification,

UG075

•

Virtex-4 FPGA PCB Designer’s Guide, UG072

Virtex-4 RocketIO™ Multi-Gigabit Transceiver User

All supply voltage and junction temperature specifications

are representative of worst-case conditions. The parame-

ters included are common to popular designs and typical

applications.

Guide, UG076

•

Virtex-4 FPGA Embedded Tri-Mode Ethernet MAC

User Guide, UG074

PowerPC® 405 Processor Block Reference Guide,

UG018

All specifications are subject to change without notice.

Virtex-4 FPGA DC Characteristics

Table 1: Absolute Maximum Ratings

Symbol

V_CCINT

V_CCAUX

V_CCO

Description

Internal supply voltage relative to GND

Units

–0.5 to 1.32

–0.5 to 3.0

–0.5 to 3.75

–0.5 to 4.05

–0.3 to 3.75

V

Auxiliary supply voltage relative to GND

Output drivers supply voltage relative to GND

Key memory battery backup supply

Input reference voltage

V_BATT

V_REF

I/O input voltage relative to GND

(all user and dedicated I/Os)

–0.75 to 4.05

V

–0.95 to 4.4

(Commercial Temperature)

–0.85 to 4.3

(Industrial Temperature)

I/O input voltage relative to GND

(restricted to maximum of 100 user I/Os)^(3,4)

V_IN

2.5V or below I/O input voltage relative to GND

(user and dedicated I/Os)

–0.75 to V_CCO+0.5

Current applied to an I/O pin, powered or unpowered

100

200

mA

I

IN

Total current applied to all I/O pins, powered or unpowered

countries. The PowerPC name and logo are registered trademarks of IBM Corp. and used under license. PCI, PCI Express, PCIe, and PCI-X are trademarks of PCI-SIG. All other

trademarks are the property of their respective owners.

DS302 (v3.7) September 9, 2009

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Product Specification

1

Virtex-4 FPGA Data Sheet: DC and Switching Characteristics

Table 1: Absolute Maximum Ratings (Continued)

Symbol

Description

Units

Voltage applied to 3-state 3.3V output

(all user and dedicated I/Os)

–0.75 to 4.05

V

–0.95 to 4.4

Voltage applied to 3-state 3.3V output

V_TS

(Commercial Temperature)

V

(restricted to maximum of 100 user I/Os)^(3,4)

–0.85 to 4.3

(Industrial Temperature)

2.5V or below I/O input voltage relative to GND

(user and dedicated I/Os)

–0.75 to V_CCO+0.5

–0.5 to 1.32

V

Receive auxiliary supply voltage relative to analog ground, GNDA

(RocketIO pins)

AVCCAUXRX

AVCCAUXTX

AVCCAUXMGT

Transmit auxiliary supply voltage relative to analog ground, GNDA

(RocketIO pins)

–0.5 to 1.32

Management auxiliary supply voltage relative to analog ground, GNDA

(RocketIO pins)

–0.5 to 3.0

V_TRX

V_TTX

T_STG

T_SOL

T_J

Terminal receive supply voltage relative to GND

Terminal transmit supply voltage relative to GND

Storage temperature (ambient)

–0.5 to 3.0

–0.5 to 1.65

–65 to 150

+220

V

°C

Maximum soldering temperature⁽²⁾

Maximum junction temperature⁽²⁾

+125

Notes:

1. Stresses beyond those listed under Absolute Maximum Ratings might cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to

Absolute Maximum Ratings conditions for extended periods of time might affect device reliability.

2. For soldering guidelines and thermal considerations, see the Virtex-4 Packaging and Pinout Specification on the Xilinx website.

3. When using more than 100 3.3V I/Os, refer to the Virtex-4 FPGA User Guide, Chapter 6, “3.3V I/O Design Guidelines.”

4. For more flexibility in specific designs, a maximum of 100 user I/Os can be stressed beyond the normal spec for no more than 20% of a data period.

There are no bank restrictions.

Table 2: Recommended Operating Conditions

Symbol

Description

Min

1.14

Max

1.26

2.625

3.45

Units

Internal supply voltage relative to GND, T_J= 0°C to +85°C

Internal supply voltage relative to GND, T_J= –40°C to +100°C

Auxiliary supply voltage relative to GND, T_J= 0°C to +85° C

Auxiliary supply voltage relative to GND, T_J= –40° C to +100°C

Supply voltage relative to GND, T_J= 0°C to +85°C

Supply voltage relative to GND, T_J= –40°C to +100°C

3.3V supply voltage relative to GND, T_J= 0°C to +85°C

3.3V supply voltage relative to GND, T_J= –40° C to +100° C

Commercial

Industrial

V

V_CCINT

1.14

Commercial

Industrial

2.375

1.14

V_CCAUX

Commercial

Industrial

(1,3,4,5)

V_CCO

1.14

Commercial GND – 0.20

Industrial GND – 0.20

2.5V and below supply voltage relative to GND,

T_J= 0°C to +85° C

V_IN

Commercial GND – 0.20 V_CCO+ 0.2

V

2.5V and below supply voltage relative to GND,

T_J= –40° C to +100° C

Industrial

GND – 0.20 V_CCO+ 0.2

Commercial

Industrial

10

mA

V

Maximum current through any pin in a powered or unpowered

bank when forward biasing the clamp diode.

I_IN

Battery voltage relative to GND, T_J= 0°C to +85°C

Battery voltage relative to GND, T_J= –40°C to +100°C

Commercial

Industrial

1.0

3.6

(2)

V_BATT

V

DS302 (v3.7) September 9, 2009

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Product Specification

2

Virtex-4 FPGA Data Sheet: DC and Switching Characteristics

Table 2: Recommended Operating Conditions (Continued)

Symbol Description

Min

1.14

2.375

0.25

1.14

Max

1.26

2.625

2.5

Units

Commercial

Industrial

V

AVCCAUXRX⁽⁶⁾Auxiliary receive supply voltage relative to GNDA

AVCCAUXTX⁽⁶⁾Auxiliary transmit supply voltage relative to GNDA

Commercial

Industrial

Commercial

Industrial

AVCCAUXMGT Auxiliary management supply voltage relative to GNDA

Commercial

Industrial

(7)

V_TRX

Terminal receive supply voltage relative to GND

Terminal transmit supply voltage relative to GND

2.5

Commercial

Industrial

1.575

V_TTX

Notes:

1. Configuration data is retained even if V_CCOdrops to 0V.

2. _BATTis required only when using bitstream encryption. If battery is not used, connect V_BATTto either ground or V_CCAUX

V

.

3. For 3.3V I/O operation, refer to the Virtex-4 FPGA User Guide.

4. Includes V_CCOof 1.2V, 1.5V, 1.8V, 2.5V, and 3.3V

5. The configuration output supply voltage V_{CC_CONFIG}is also known as V_{CCO_0}

6. IMPORTANT! All unused RocketIO transceivers must be connected to power and GND. When using RocketIO transceivers, refer to the power filtering

section of the Virtex-4 RocketIO Multi-Gigabit Transceiver User Guide. Unused transceivers must be powered by an appropriate voltage level source.

Passive filtering must meet the requirements discussed in the Virtex-4 RocketIO Multi-Gigabit Transceiver User Guide.

7. Internal AC coupling is enabled.

Table 3: DC Characteristics Over Recommended Operating Conditions

Data Rate

Symbol

Description

Data retention V_CCINTvoltage

(Gb/s)

Min Typ Max

Units

V_DRINT

0.9

V

(below which configuration data might be lost)

Data retention V_CCAUXvoltage

(below which configuration data might be lost)

V_DRI

2.0

V

I_REF

I_L

V_REFcurrent per pin

10

µA

pF

Input or output leakage current per pin (sample-tested)

Input capacitance (sample-tested)

C_IN

Pad pull-up (when selected) @ V_IN= 0V, V_CCO= 3.3V

Pad pull-up (when selected) @ V_IN= 0V, V_CCO= 3.0V

Pad pull-up (when selected) @ V_IN= 0V, V_CCO= 2.5V

Pad pull-up (when selected) @ V_IN= 0V, V_CCO= 1.8V

Pad pull-up (when selected) @ V_IN= 0V, V_CCO= 1.5V

Pad pull-down (when selected) @ V_IN= V_CCO

Battery supply current

5

200

125

120

60

µA

nA

mA

(1)

I_RPU

40

(1)

I_RPD

100

427

485

446

382

351

432

(1)

I_BATT

75

6.5

5.0

292

302

291

279

263

314

4.25

(2)

I_CCAUXRX

Operating AVCCAUXRX supply current

3.125

1.25/2.5

1.25 Digital RX

DS302 (v3.7) September 9, 2009

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Product Specification

3

Virtex-4 FPGA Data Sheet: DC and Switching Characteristics

Table 3: DC Characteristics Over Recommended Operating Conditions (Continued)

Data Rate

(Gb/s)

Symbol

Description

Operating AVCCAUXTX supply current

Operating AVCCAUXMGT supply current

Min Typ Max

Units

mA

6.5

5.0

170

180

173

165

157

151

3

339

355

330

307

298

295

5

mA

4.25

3.125

2.5

mA

(2)

I_CCAUXTX

mA

1.25

mA

(2)

I_CCAUXMGT

mA

Operating I_TTXsupply current when transmitter is AC coupled

or V_TTX= V_TRX

(2)

I_TTX

100

12

210

24

mA

Operating I_TRXsupply current when receiver is AC coupled or

V_TTX= V_TRX

(2,3)

I_TRX

n

P_CPU

r

Temperature diode ideality factor

Power dissipation of PowerPC 405 processor block

Series resistance

1.02

0.45

2

n

mW/MHz

Ω

Notes:

1. Values are specified at nominal voltage, 25°C.

2. Typical I_CCnumbers given per tile with both MGTs operating with default settings. Maximum I_CCnumbers given per tile with both MGTs operating with

maximum amplitude and emphasis settings.

3. Varies with AC / DC coupling.

Table 4: Quiescent Supply Current

Symbol

Description

Quiescent V_CCINTsupply current

Device

Typ⁽¹⁾

46

Max

Units

mA

Note (6)

I_CCINTQ

XC4VLX15

XC4VLX25

XC4VLX40

XC4VLX60

XC4VLX80

XC4VLX100

XC4VLX160

XC4VLX200

XC4VSX25

XC4VSX35

XC4VSX55

XC4VFX12

XC4VFX20

XC4VFX40

XC4VFX60

XC4VFX100

XC4VFX140

77

121

167

220

292

384

489

94

140

271

47

71

139

203

311

442

DS302 (v3.7) September 9, 2009

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Product Specification

4

Virtex-4 FPGA Data Sheet: DC and Switching Characteristics

Table 4: Quiescent Supply Current (Continued)

Symbol

Description

Quiescent V_CCOsupply current

Device

Typ⁽¹⁾

1.25

1.5

1.75

2.5

1.25

1.5

1.25

1.5

1.75

2.5

31

Max

Units

mA

Note (6)

154

I_CCOQ

XC4VLX15

XC4VLX25

XC4VLX40

XC4VLX60

XC4VLX80

XC4VLX100

XC4VLX160

XC4VLX200

XC4VSX25

XC4VSX35

XC4VSX55

XC4VFX12

XC4VFX20

XC4VFX40

XC4VFX60

XC4VFX100

XC4VFX140

XC4VLX15

XC4VLX25

XC4VLX40

XC4VLX60

XC4VLX80

XC4VLX100

XC4VLX160

XC4VLX200

XC4VSX25

XC4VSX35

XC4VSX55

XC4VFX12

XC4VFX20

XC4VFX40

XC4VFX60

XC4VFX100

XC4VFX140

XC4VFX20

XC4VFX60

XC4VFX100

I_CCAUXQ

Quiescent V_CCAUXsupply current

36

43

74

83

95

133

150

62

70

91

31

35

69

80

98

143

25

(4)

I_CCAUXRX

Quiescent AVCCAUXRX supply current

35

154

50

154

DS302 (v3.7) September 9, 2009

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Product Specification

5

Virtex-4 FPGA Data Sheet: DC and Switching Characteristics

Table 4: Quiescent Supply Current (Continued)

Symbol

Description

Device

Typ⁽¹⁾

Max

44

2

Units

mA

(4)

I_CCAUXTX

XC4VFX20

XC4VFX60

XC4VFX100

XC4VFX20

XC4VFX60

XC4VFX100

XC4VFX20

XC4VFX60

XC4VFX100

XC4VFX20

XC4VFX60

XC4VFX100

10

15

20

1

Quiescent AVCCAUXTX supply current

(4,5)

I_TTX

Quiescent V

supply current

TTX

TRX

1

2

1

2

(4,5)

I_TRX

1

2

1

2

1

2

(4)

I_AUXMGT

Quiescent V_AUXMGTsupply current

1

2

1

2

1

2

Notes:

1. Typical values are specified at nominal voltage, 25°C.

2. Typical values are for blank configured devices with no output current loads, no active input pull-up resistors, all I/O pins are 3-state and floating.

3. If DCI or differential signaling is used, more accurate quiescent current estimates can be obtained by using the Power Estimator or XPower tool.

4. Given for entire die. Powered and unconfigured.

5. Unconnected (if channel is driven to voltage).

6. Use the XPower Estimator (XPE) tool to calculate maximum static power for specific process, voltage, and temperature conditions.

DS302 (v3.7) September 9, 2009

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Product Specification

6

Virtex-4 FPGA Data Sheet: DC and Switching Characteristics

Power-On Power Supply Requirements

Xilinx® FPGAs require a certain amount of supply current

during power-on to insure proper device initialization. The

actual current consumed depends on the power-on ramp

rate of the power supply.

Table 5 shows the minimum current required by Virtex-4

devices for proper power-on and configuration.

If the current minimums shown in Table 5 are met, the

device powers on properly after all three supplies have

passed through their power-on reset threshold voltages.

The power supplies can be turned on in any sequence,

though the specifications shown in Table 5 are for the rec-

Once initialized and configured, use the XPower tool to esti-

mate current drain on these supplies.

ommended power-on sequence of V

, V

.

CCINT CCAUX

CCO

Xilinx does not specify the current for other power-on

sequences.

Table 5: Power-On Current for Virtex-4 Devices

I

CCOMIN

CCINTMIN

CCAUXMIN

(1)

(2)

(1)

(2)

(1)

(2)

Device

XC4VLX15

XC4VLX25

XC4VLX40

XC4VLX60

XC4VLX80

XC4VLX100

XC4VLX160

XC4VLX200

XC4VSX25

XC4VSX35

XC4VSX55

XC4VFX12

XC4VFX20

XC4VFX40

XC4VFX60

XC4VFX100

XC4VFX140

Notes:

Typ

110

Max

750

Typ

Max

Typ

Max

Units

mA

60

100

125

150

300

350

425

600

150

200

300

100

250

350

500

825

50

75

160

250

300

400

500

700

850

175

250

400

111

151

244

339

511

702

1350

1500

1925

2550

3200

3700

3850

725

85

100

105

250

275

300

400

105

150

225

75

110

225

280

335

500

110

165

225

56

75

150

200

250

75

1350

2225

750

100

150

50

1100

1650

2250

3300

4250

56

75

125

225

275

300

375

167

222

278

500

125

150

200

250

1. Typical values are specified at nominal voltage, 25°C.

2. Maximum values are specified under worst-case process, voltage, and temperature conditions.

Table 6: Power Supply Ramp Time

Symbol

Description

Internal supply voltage relative to GND

Output drivers supply voltage relative to GND

Auxiliary supply voltage relative to GND

Ramp Time

0.20 to 50.0

Units

ms

V

CCINT

CCO

ms

CCAUX

DS302 (v3.7) September 9, 2009

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Product Specification

7

Virtex-4 FPGA Data Sheet: DC and Switching Characteristics

SelectIO™ DC Input and Output Levels

Values for V and V are recommended input voltages.

The selected standards are tested at a minimum V

with

CCO

IL

IH

Values for I

and I

are guaranteed over the recom-

the respective V and V

voltage levels shown. Other

OL

OH

OL

OH

mended operating conditions at the V

and V

test

standards are sample tested.

OL

OH

points. Only selected standards are tested. These are cho-

sen to ensure that all standards meet their specifications.

Table 7: SelectIO DC Input and Output Levels

V

I

OH

IL

IH

OL

OH

OL

IOSTANDARD

Attribute

V, Min

V, Max

V, Min

V, Max

V, Min

mA

LVTTL

–0.2

0.8

2.0

3.45

0.4

2.4

Note(3) Note(3)

LVCMOS33,

LVDCI33

–0.2

–0.3

0.8

2.0

1.7

3.45

0.4

V

– 0.4

Note(3) Note(3)

CCO

LVCMOS25,

LVDCI25

0.7

V

+ 0.3

– 0.4

Note(3) Note(3)

CCO

LVCMOS18,

LVDCI18

35% V

65% V

+ 0.3

V

– 0.45 Note(4) Note(4)

CCO

LVCMOS15,

LVDCI15

65% V

CCO

(5)

PCI33_3

–0.2

–0.3

30% V

35% V

50% V

V

10% V

90% V

1.5

36

32

8

–0.5

N/A

–8

CCO

(5)

PCI66_3

10% V

CCO

(5)

PCI-X

CCO

GTLP

GTL

V

– 0.1

– 0.05

– 0.1

V

+ 0.1

+ 0.05

+ 0.1

–

0.6

0.4

N/A

REF

V

–

REF

(2)

HSTL I

V

+ 0.3

V

– 0.4

REF

CCO

(2)

HSTL II

V

– 0.4

16

24

48

–16

–8

(2)

HSTL III

V

(2)

HSTL IV

–8

50%

(2)

DIFF HSTL II

–0.3

V

+ 0.3

0.4

V

– 0.4

–

CCO

V

– 0.1

– 0.15

V

+ 0.1

CCO

SSTL2 I

SSTL2 II

–0.3

V

+ 0.15

V

+ 0.3

V

– 0.61

– 0.81

V

+ 0.61

+ 0.81

8.1

–8.1

REF

CCO

TT

16.2

–16.2

50%

DIFF SSTL2 II

–0.3

V

+ 0.3

0.5

V

– 0.5

–

CCO

V

– 0.15

V

+ 0.15

CCO

SSTL18 I

SSTL18 II

–0.3

V

– 0.125

V

+ 0.125

V

+ 0.3

V

– 0.47

– 0.60

V

+ 0.47

+ 0.60

6.7

–6.7

REF

CCO

TT

V

13.4

–13.4

REF

50%

DIFF SSTL18 II

–0.3

V

+ 0.3

0.4

V

– 0.4

–

CCO

V

– 0.125

V

+ 0.125

CCO

Notes:

1. Tested according to relevant specifications.

2. Applies to both 1.5V and 1.8V HSTL.

3. LVCMOS using drive strengths of 2, 4, 6, 8, 12, 16, or 24 mA.

4. LVCMOS using drive strengths of 2, 4, 6, 8, 12, or 16 mA.

5. For more information on PCI33_3, PCI66_3, and PCI-X, refer to the Virtex-4 FPGA User Guide, SelectIO Resources, Chapter 6.

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Product Specification

8

Virtex-4 FPGA Data Sheet: DC and Switching Characteristics

LDT DC Specifications (LDT_25)

Table 8: LDT DC Specifications

Symbol

DC Parameter

Supply Voltage

Conditions

Min

2.38

495

–15

495

–15

200

–15

440

–15

Typ

2.5

Max

2.63

715

15

Units

V

CCO

(1,2)

V

Differential Output Voltage

R = 100Ω across Q and Q signals

600

mV

OD

T

Δ V

Change in V Magnitude

OD

V

Output Common Mode Voltage

Change in V Magnitude

R = 100Ω across Q and Q signals

600

715

15

OCM

T

Δ V

OCM

V

Input Differential Voltage

1000

15

ID

Δ V

Change in V Magnitude

ID

V

Input Common Mode Voltage

780

15

ICM

Δ V

Change in V

Magnitude

ICM

Notes:

1. Recommended input maximum voltage not to exceed V_CC0+ 0.2V.

2. Recommended input minimum voltage not to go below –0.5V.

LVDS DC Specifications (LVDS_25)

Table 9: LVDS DC Specifications

Symbol

DC Parameter

Supply Voltage

Conditions

Min

Typ

Max

2.63

Units

V

2.38

2.5

V

CCO

V

Output High Voltage for Q and Q

Output Low Voltage for Q and Q

R = 100Ω across Q and Q signals

1.602

OH

T

V

R = 100Ω across Q and Q signals

0.898

247

OL

T

(1,2)

Differential Output Voltage

V

R = 100Ω across Q and Q signals

350

454

mV

V

ODIFF

T

(Q – Q), Q = High (Q – Q), Q = High

Output Common-Mode Voltage

V

R = 100Ω across Q and Q signals

1.125 1.250 1.375

OCM

T

Differential Input Voltage (Q – Q),

Q = High (Q – Q), Q = High

V

100

0.3

350

1.2

600

2.2

mV

V

IDIFF

V

Input Common-Mode Voltage

ICM

Notes:

1. Recommended input maximum voltage not to exceed V_CC0+ 0.2V.

2. Recommended input minimum voltage not to go below –0.5V.

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9

Virtex-4 FPGA Data Sheet: DC and Switching Characteristics

Extended LVDS DC Specifications (LVDSEXT_25)

Table 10: Extended LVDS DC Specifications

Symbol DC Parameter

Supply Voltage

Conditions

Min

2.38

–

Typ

2.5

–

Max

2.63

1.785

–

Units

V

CCO

V

Output High Voltage for Q and Q

Output Low Voltage for Q and Q

R = 100Ω across Q and Q signals

OH

T

V

R = 100Ω across Q and Q signals

0.715

–

OL

T

Differential Output Voltage (Q – Q),

Q = High (Q – Q), Q = High

V

R = 100Ω across Q and Q signals

440

–

820

mV

V

ODIFF

T

V

Output Common-Mode Voltage

R = 100Ω across Q and Q signals

1.125 1.250 1.375

OCM

IDIFF

T

Differential Input Voltage^(1,2)

(Q – Q), Q = High (Q – Q), Q = High

V

Common-mode input voltage = 1.25V

Differential input voltage = 350 mV

100

0.3

–

1000

2.2

mV

V

Input Common-Mode Voltage

1.2

ICM

Notes:

1. Recommended input maximum voltage not to exceed V_CC0+ 0.2V.

2. Recommended input minimum voltage not to go below –0.5V.

LVPECL DC Specifications (LVPECL_25)

These values are valid when driving a 100Ωdifferential load

only, i.e., a 100Ω resistor between the two receiver pins.

mon-mode ranges. Table 11 summarizes the DC output

specifications of LVPECL. For more information on using

LVPECL, see the Virtex-4 FPGA User Guide: Chapter 6,

SelectIO Resources.

The V levels are 200 mV below standard LVPECL levels

OH

and are compatible with devices tolerant of lower com-

Table 11: LVPECL DC Specifications

Symbol

V_OH

DC Parameter

Output High Voltage

Min

V_CC– 1.025

V_CC– 1.81

0.6

Typ

1.545

0.795

Max

V_CC– 0.88

V_CC– 1.62

2.2

Units

V

V_OL

Output Low Voltage

V_ICM

Input Common-Mode Voltage

Differential Input Voltage^(1,2)

V_IDIFF

0.100

1.5

Notes:

1. Recommended input maximum voltage not to exceed V_CC0+ 0.2V.

2. Recommended input minimum voltage not to go below –0.5V.

DS302 (v3.7) September 9, 2009

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Product Specification

10

Virtex-4 FPGA Data Sheet: DC and Switching Characteristics

RocketIO DC Input and Output Levels

Table 12 summarizes the DC input and output specifica-

tions of the Virtex-4 FPGA RocketIO Multi-Gigabit Serial

Transceivers. Figure 1 shows the single-ended output volt-

age swing. Figure 2 shows the peak-to-peak differential out-

put voltage. Consult the Virtex-4 RocketIO Multi-Gigabit

Transceiver User Guide for further details.

Table 12: RocketIO DC Specifications

DC Parameter

Peak-to-Peak Differential Input Voltage

Single-Ended Input Range

Symbol

DV_IN

Conditions

Internal AC Coupled

Min Typ

Max

2400

Units

mV

110

0

SE_VIN

V_TRX

mV

100

V_TRX– 100

mV

Common Mode Input Voltage Range

V_ICM

Bypassed Internal AC

Coupled ⁽¹⁾

800

mV

Single-Ended Output Voltage Swing^{(2, 3)}

Common Mode Output Voltage Range⁽³⁾

Peak-to-Peak Differential Output Voltage^{(2, 3)}

Signal detect threshold

V_OUT

V_TCM

450

725

mV

1000

DV_PPOUT

900 1050

TBD

1400

RXOOB_VDPPRX

TXOOB_VDPPTX

Electrical idle amplitude

65

mV

RocketIO MGT Clock DC Input Levels

Peak-to-Peak Differential Input Voltage

Differential Input Resistance

V_IDIFF

R_IN

2 x | V_MGTCLKP– V_MGTCKLN

|

100

71

600

105

2000

124

mV

Ω

Notes:

1. The maximum V_TRXis 1.26V when bypassing the internal AC coupled V_ICM. V_TRXmust be less than or equal to AVCCAUXRX.

2. The output swing and pre-emphasis levels are selected using the attributes discussed in Chapter 4: PMA Analog Considerations in the Virtex-4

RocketIO Multi-Gigabit Transceiver User Guide for details.

V_TTXis 1.5 5%; different amplitudes possible with adjusted DAC values.

3.

+V

0

TXP

TXN

DV_OUT

DS302_02_031708

Figure 1: Single-Ended Output Voltage Swing

+V

DV_PPOUT

0

–V

TXP–TXN

DS302_03_031708

Figure 2: Peak-to-Peak Differential Output Voltage

DS302 (v3.7) September 9, 2009

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Product Specification

11

Virtex-4 FPGA Data Sheet: DC and Switching Characteristics

Interface Performance Characteristics

Table 13: Interface Performance

Speed Grade

Description

Networking Applications

-12

-11

-10

SFI-4.1 (SDR LVDS Interface)⁽¹⁾

710 MHz

1 Gb/s

710 MHz

1 Gb/s

645 MHz

800 Mb/s

SPI-4.2 (DDR LVDS Interface)

Memory Interfaces

DDR2 SDRAM (High-Performance SERDES Design)⁽²⁾

DDR2 SDRAM (Low-Latency Direct Clocking Design)⁽³⁾

QDRII SRAM (Low-Latency Direct Clocking Design)⁽⁴⁾

DDR SDRAM (Low-Latency Direct Clocking Design)⁽⁵⁾

RLDRAM II (Low-Latency Direct Clocking Design)⁽⁶⁾

600 Mb/s

420 Mb/s

550 Mb/s

344 Mb/s

470 Mb/s

533 Mb/s

410 Mb/s

500 Mb/s

336 Mb/s

470 Mb/s

500 Mb/s

400 Mb/s

330 Mb/s

400 Mb/s

Notes:

1. Input clocks above 622 MHz require AC coupling.

2. Performance defined using design implementation described in application note XAPP721, High-Performance DDR2 SDRAM Interface Data

Capture Using ISERDES and OSERDES.

3. Performance defined using design implementation described in application note XAPP702, DDR2 Controller Using Virtex-4 Devices.

4. Performance defined using design implementation described in application note XAPP703, QDR II SRAM Interface for Virtex-4 Devices.

5. Performance defined using design implementation described in application note XAPP709, DDR SDRAM Controller Using Virtex-4 FPGA Devices.

6. Performance defined using design implementation described in application note XAPP710, Synthesizable CIO DDR RLDRAM II Controller for

Virtex-4 FPGAs.

Switching Characteristics

Switching characteristics are specified on a per-speed-

grade basis and can be designated as Advance, Prelimi-

nary, or Production. Each designation is defined as follows:

Table 14: Virtex-4 Device Speed Grade Designations

Speed Grade Designations

Device

Advance

Preliminary Production

-12, -11, -10

-11, -10

Advance

XC4VLX15

XC4VLX25

XC4VLX40

XC4VLX60

XC4VLX80

XC4VLX100

XC4VLX160

XC4VLX200

XC4VSX25

XC4VSX35

XC4VSX55

XC4VFX12

XC4VFX20

XC4VFX40

XC4VFX60

XC4VFX100

XC4VFX140

These specifications are based on simulations only and are

typically available soon after device design specifications

are frozen. Although speed grades with this designation are

considered relatively stable and conservative, some

under-reporting might still occur.

Preliminary

These specifications are based on complete ES (engineer-

ing sample) silicon characterization. Devices and speed

grades with this designation are intended to give a better

indication of the expected performance of production sili-

con. The probability of under-reporting delays is greatly

reduced as compared to Advance data.

-12, -11, -10

-11, -10

Production

These specifications are released once enough production

silicon of a particular device family member has been char-

acterized to provide full correlation between specifications

and devices over numerous production lots. There is no

under-reporting of delays, and customers receive formal

notification of any subsequent changes. Typically, the slow-

est speed grades transition to Production before faster

speed grades.

Table 14 correlates the current status of each Virtex-4

device with a corresponding speed specification version

1.68 designation.

DS302 (v3.7) September 9, 2009

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Product Specification

12

Virtex-4 FPGA Data Sheet: DC and Switching Characteristics

Since individual family members are produced at different

times, the migration from one category to another depends

completely on the status of the fabrication process for each

device.

All specifications are always representative of worst-case

supply voltage and junction temperature conditions.

Testing of Switching Characteristics

All devices are 100% functionally tested. Internal timing

parameters are derived from measuring internal test pat-

terns. Listed below are representative values. For more

specific, more precise, and worst-case guaranteed data,

use the values reported by the static timing analyzer (TRCE

in the Xilinx Development System) and back-annotate to the

simulation net list. Unless otherwise noted, values apply to

all Virtex-4 devices.

PowerPC Switching Characteristics

Consult the PowerPC 405 Processor Block Reference Guide for further information.

Table 15: PowerPC 405 Processor Clocks Absolute AC Characteristics

Speed Grade

-12

-11

-10

Description

Characteristics when APU Not Used

CPMC405CLOCK frequency^(1,4)

CPMDCRCLK⁽³⁾

Min

Max

Min

Max

Min

Max

Units

0

450

NA

0

400

NA

0

350

NA

MHz

CPMFCMCLK⁽³⁾

NA

0

NA

0

NA

0

JTAGC405TCK frequency⁽²⁾

PLBCLK⁽³⁾

225

450

200

400

175

350

0

BRAMDSOCMCLK⁽³⁾

BRAMISOCMCLK⁽³⁾

0

Characteristics when APU Used

CPMC405CLOCK frequency^(1,4)

CPMDCRCLK⁽³⁾

0

333

0

275

0

233

MHz

CPMFCMCLK⁽³⁾

333

275

233

JTAGC405TCK frequency⁽²⁾

PLBCLK⁽³⁾

166.5

333

137.5

275

116.5

233

BRAMDSOCMCLK⁽³⁾

BRAMISOCMCLK⁽³⁾

333

275

233

333

275

233

Notes:

1. Worst-case DCM output clock jitter is included in these specifications.

2. The theoretical maximum frequency of this clock is one-half the CPMC405CLOCK. However, the achievable maximum is system dependent, and will

be much less.

3. The theoretical maximum frequency of these clocks is equal to the CPMC405CLOCK. Integer clock ratios are required for the CPMC405CLOCK and

BRAMDSOCMCLK, CPMC405CLOCK and BRAMISOCMCLK, CPMC405CLOCK and CPMDCRCLK, CPMC405CLOCK and CPMFCMCLK, and

CPMC405CLOCK and PLBCLK. The integer ratios can be different for each interface. However, the achievable maximum is system dependent.

4. Maximum operating frequency of CPMC405CLOCK is specified with the input pin TIEC405DISOPERANDFWD connected to a logic 1.

DS302 (v3.7) September 9, 2009

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Product Specification

13

Virtex-4 FPGA Data Sheet: DC and Switching Characteristics

Speed Grade

Table 16: Processor Block Switching Characteristics

Description

Symbol

-12

-11

-10

Units

Setup and Hold Relative to Clock (CPMC405CLOCK)

T

_PPCDCK_CORECKI/

_PPCCKD_CORECKI

0.60

0.20

0.65

0.20

0.74

0.23

Clock and Power Management control inputs

Reset control inputs

ns, Min

T_PPCDCK_RSTCHIP/

T_PPCCKD_RSTCHIP

0.60

0.20

0.65

0.20

0.74

0.23

T_PPCDCK_EXBUSHAK/

T_PPCCKD_EXBUSHAK

0.60

0.20

0.65

0.20

0.74

0.23

Debug control inputs

T_PPCDCK_TRCDIS/

T_PPCCKD_TRCDIS

0.60

0.20

0.65

0.20

0.74

0.23

Trace control inputs

T_PPCDCK_CINPIRQ/

T

1.04

0.20

1.15

0.20

1.40

0.23

External Interrupt Controller control inputs

_PPCCKD_CINPIRQ

Clock to Out

Clock and Power Management control outputs

Reset control outputs

Debug control outputs

Trace control outputs

Clock

T

_PPCCKO_CORESLP

1.35

1.44

1.34

1.52

1.51

1.59

1.48

1.68

1.74

1.83

1.70

1.83

ns, Max

T_PPCCKO_RSTCHIP

T_PPCCKO_DBGLDAPU

T_PPCCKO_TRCCYCLE

CPMC405CLOCK minimum pulse width, High T_CPWH

CPMC405CLOCK minimum pulse width, Low T_CPWL

1.11

1.25

1.43

ns, Min

Table 17: Processor Block PLB Switching Characteristics

Speed Grade

-11

Description

Symbol

-12

-10

Units

Setup and Hold Relative to Clock (PLBCLK)

T

_PPCDCK_ICUBUSY/

0.60

0.20

0.66

0.20

0.76

0.23

Processor Local Bus (ICU/DCU) control inputs

Processor Local Bus (ICU/DCU) data inputs

ns, Min

T_PPCCKD_ICUBUSY

T_PPCDCK_ICURDDB/

T_PPCCKD_ICURDDB

0.90

0.20

1.00

0.20

1.15

0.23

Clock to Out

Processor Local Bus (ICU/DCU) control outputs

Processor Local Bus (ICU/DCU) address bus outputs

Processor Local Bus (ICU/DCU) data bus outputs

T_PPCCKO_DCUABORT

T_PPCCKO_ICUABUS

1.61

1.66

2.08

1.78

1.85

2.24

2.05

2.13

2.57

ns, Max

T_PPCCKO_DCUWRDBUS

Table 18: Processor Block JTAG Switching Characteristics

Speed Grade

Description

Symbol

-12

-11

-10

Units

Setup and Hold Relative to Clock (JTAGC405TCK)

T_PPCDCK_JTGTDI

_PPCCKD_JTGTDI

1.16

0.20

1.29

0.20

1.48

0.23

JTAG control inputs

JTAG reset input

ns, Min

T

T_PPCDCK_JTGTRSTN

T_PPCCKD_JTGTRSTN

0.60

0.20

0.65

0.20

0.74

0.23

Clock to Out

JTAG control outputs

T

_PPCCKO_JTGTDO

1.68

1.79

2.14

ns, Max

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Product Specification

14

Virtex-4 FPGA Data Sheet: DC and Switching Characteristics

Table 19: PowerPC 405 Data-Side On-Chip Memory Switching Characteristics

Speed Grade

-11

Description

Symbol

-12

-10

Units

Setup and Hold Relative to Clock (BRAMDSOCMCLK)

T_PPCDCK_DSOCMRDDB

_PPCCKD_DSOCMRDDB

0.60

0.20

0.65

0.20

0.74

0.23

Data-Side On-Chip Memory data bus inputs

ns, Min

T

Clock to Out

Data-Side On-Chip Memory control outputs

Data-Side On-Chip Memory address bus outputs

Data-Side On-Chip Memory data bus outputs

T_PPCCKO_BRAMBWR

_PPCCKO_BRAMABUS

T_PPCCKO_IBRAMWRDBUS01

2.07

1.61

2.30

1.79

2.65

2.06

ns, Max

T

Table 20: PowerPC 405 Instruction-Side On-Chip Memory Switching Characteristics

Speed Grade

-11

Description

Symbol

-12

-10

Units

Setup and Hold Relative to Clock (BRAMISOCMCLK)

T_PPCDCK_ISOCMRDDB

T_PPCCKD_ISOCMRDDB

0.74

0.20

0.82

0.20

0.94

0.23

Instruction-Side On-Chip Memory data bus inputs

ns, Min

Clock to Out

Instruction-Side On-Chip Memory control outputs

Instruction-Side On-Chip Memory address bus outputs

Instruction-Side On-Chip Memory data bus outputs

T_PPCCKO_IBRAMEN

3.04

1.67

3.37

1.85

1.86

3.88

2.13

2.14

ns, Max

T

_PPCCKO_IBRAMRDABUS

T_PPCCKO_IBRAMWRDBUS

Table 21: Processor Block DCR Bus Switching Characteristics

Speed Grade

-11

Description

Symbol

-12

-10

Units

Setup and Hold Relative to Clock (CPMDCRCLOCK)

T_PPCDCK_EXDCRACK

T_PPCCKD_EXDCRACK

0.12

0.15

0.13

0.17

0.15

0.19

Device Control Register Bus control inputs

Device Control Register Bus data inputs

ns, Min

T_PPCDCK_EXDCRDBUSI

T_PPCCKD_EXDCRDBUSI

0.57

0.16

0.57

0.16

1.02

0.27

Clock to Out

Device Control Register Bus control outputs

Device Control Register Bus address bus outputs

Device Control Register Bus data bus outputs

T

_PPCCKO_EXDCRRD

T_PPCCKO_EXDCRABUS

_PPCCKO_EXDCRDBUSO

1.20

1.28

1.31

1.35

1.45

1.54

1.66

1.67

ns, Max

T

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Product Specification

15

Virtex-4 FPGA Data Sheet: DC and Switching Characteristics

Table 22: Processor Block APU Interface Switching Characteristics

Speed Grade

-11

Description

Symbol

-12

-10

Units

Setup and Hold Relative to Clock (CPMDFCMCLOCK)

T

_PPCDCK_DCDCREN

0.33

0.20

0.36

0.20

0.42

0.23

APU bus control inputs

APU bus data inputs

ns, Min

T_PPCCKD_DCDCREN

T_PPCDCK_RESULT

T_PPCCKD_RESULT

0.61

0.20

0.67

0.20

0.78

0.23

Clock to Out

APU bus control outputs

APU bus data outputs

T_PPCCKO_APUFCMDEC

T_PPCCKO_RADATA

1.53

1.75

2.00

ns, Max

RocketIO Switching Characteristics

Consult the Virtex-4 RocketIO Multi-Gigabit Transceiver User Guide for further information.

Table 23: Maximum RocketIO Transceiver Performance

Speed Grade

Description

-12

-11

-10

3.125

Units

RocketIO Transceiver

6.5

Gb/s

Table 24: RocketIO Reference Clock Switching Characteristics

Description

Symbol

Conditions

Min

106

Typ

Max

Units

-10 Speed Grade

400

MHz

Reference Clock frequency range⁽¹⁾

F_GCLK

CLK

-11/-12 Speed Grades

644

MHz

All Speed Grades

GREFCLK Reference Clock frequency range⁽¹⁾F_GREFCLKCLK

106

320

+350

400

55

MHz

ppm

ps

Reference Clock frequency tolerance

Reference Clock rise time

F_GTOL

T_RCLK

T_FCLK

T_DCREF

T_GJTT

CLK

–350

20% – 80%

CLK

Reference Clock fall time

ps

Reference Clock duty cycle

Reference Clock total jitter, peak-peak⁽²⁾

45

30

%

CLK

40

ps

Initial lock of the PLL from

startup (programmable)

Clock recovery frequency acquisition time

T_LOCK

1

ms

Spread Spectrum Clocking⁽³⁾

0% to –0.5%

33

kHz

Notes:

1. MGTCLK input can be used for all serial bit rates. GREFCLK can be used for serial bit rates up to 1 Gb/s.

2. Measured at the package pin. For serial rates equal to or above 1 Gb/s, MGTCLK must be used. UI = Unit Interval.

3. Tested with synchronous reference clock.

T_RCLK

80%

20%

T_FCLK

DS302_04_031708

Figure 3: Reference Clock Timing Parameters

DS302 (v3.7) September 9, 2009

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Product Specification

16

Virtex-4 FPGA Data Sheet: DC and Switching Characteristics

Table 25: RocketIO Receiver Switching Characteristics

Description

Serial data rate, -10

Serial data rate, -11

Symbol

F_GRX

Conditions

Min

Typ

Max

3.125

6.5

Units

Gb/s

0.622

F_GRX

XAUI Receive Jitter Tolerance (8B/10B CJPAT)⁽²⁾

Rate (Gb/s) Mode⁽³⁾

Frequency

Receive Deterministic Jitter Tolerance

Receive Total Jitter Tolerance

T_DJTOL

3.125

Rate (Gb/s)

6.5⁽⁵⁾

ACDR

Mode⁽³⁾

ACDR

DCDR

ACDR

DCDR

0.37

0.65

8.5

(6)

T_TJTOL

f = 22.1 kHz

f = 1.875 MHz

f = 20 MHz

Pattern

PRBS7

UI⁽¹⁾

(7)

Receive Sinusoidal Jitter Tolerance

T_SJTOL

0.10

General Receive Jitter Tolerance

0.65

0.60

0.55

0.50

0.40

0.65

0.50

0.55

0.35

0.55

250

60

5.0⁽⁵⁾

PRBS7

4.25⁽⁵⁾

3.125

2.5

PRBS7

(2,4)

Receive deterministic jitter tolerance

T_DJTOL

PRBS7

1.25

PRBS7

1.25

PRBS7

1.25

PRBS31

PRBS7

0.622

6.5⁽⁹⁾

5.0⁽⁹⁾

UI⁽¹⁾

PRBS7

4.25⁽⁹⁾

3.125⁽⁸⁾

2.5⁽⁸⁾

1.25⁽⁸⁾

0.622⁽⁸⁾

PRBS7

Sinusoidal jitter tolerance

T_SJTOL

PRBS7

PRBS31

RXUSRCLK frequency

T_RX

T_RX2

For slower speed grades = MaxDataRate/32

MHz

%

RXUSRCLK2 frequency

RXUSRCLK duty cycle

T_RXDC

T_RX2DC

T_ISKEW

V_EYE

40

RXUSRCLK2 duty cycle

60

%

Differential input skew

20

ps

Differential receive input sensitivity⁽²⁾

On-chip AC coupling corner frequency

Signal detect response time

Input capacitance at the Die

Excess capacitance at the solder ball

110

mV

RXSIGDET_Responsetime

30

ns

fF

C_DIE

C_BALL

Notes:

1. UI = Unit Interval

6. Sum of DJ, random jitter (RJ) of at least 0.55 UI, and sinusoidal jitter

as defined by mask in IEEE Std 802.3ae-2002, Figure 47-5.

7. SJ in addition to 0.55 UI of DJ +RJ.

2. Using receiver equalization setting of 111 (14 dB).

3. ACDR = Analog CDR and DCDR = Digital CDR.

4. Deterministic jitter (DJ) is composed of 75% ISI + 25% high frequency

sinusoidal jitter (SJ).

8. Jitter frequency = 5 MHz.

9. Jitter frequency = 10 MHz.

5. Deterministic Jitter (DJ) composed of ISI + 0.10 UI of high frequency SJ +

0.15 UI of RJ.

DS302 (v3.7) September 9, 2009

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Product Specification

17

Virtex-4 FPGA Data Sheet: DC and Switching Characteristics

Table 26: RocketIO Transmitter Switching Characteristics

Description

Serial data rate, -10

Symbol

F_GTX

Conditions

Min

Typ

Max

3.125

6.5

Units

Gb/s

0.622

Serial data rate, -11

F_GTX

Data

Rate (Gb/s)

0.50

0.35

0.30

0.45

0.30

0.25

0.40

0.25

0.21

0.28

0.14

0.25

0.18

0.12

0.10

0.06

0.08

0.06

0.04

TJ

RJ

DJ

TJ

PRBS7

PRBS31

6.5

RJ

DJ

TJ

5.0

4.25

3.125

2.5

RJ

DJ

TJ

TX Jitter Generation⁽³⁾

RJ

DJ

TJ

UI⁽¹⁾

RJ

DJ

TJ

RJ

DJ

TJ

1.25

0.622

RJ

DJ

T_RTX

T_FTX

TX rise time⁽²⁾

TX fall time⁽²⁾

20% – 80%

90

ps

20% – 80%

For slower speed grades =

MaxDataRate/32

TXUSRCLK frequency

250

MHz

TXUSRCLK2 frequency

TXUSRCLK duty cycle

TXUSRCLK2 duty cycle

Differential output skew

Electrical idle transition time

250

60

MHz

%

T_TXDC

T_TX2DC

40

60

%

T_ISKEW

12

15

20

ps

TXOOB_Transition

ns

Notes:

1. UI = Unit Interval.

2. Default attributes, measured at 2.5 Gb/s.

3. Peak-to-Peak values measured relative to 1e-12 Error rate. Default attributes. TX feedback divider (TXPLLNDIVSEL) = 10.

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Product Specification

18

Virtex-4 FPGA Data Sheet: DC and Switching Characteristics

IOB Pad Input/Output/3-State Switching Characteristics

Table 27 summarizes the values of standard-specific data

input delay adjustments, output delays terminating at pads

(based on standard and 3-state delays.

T

is described as the delay from the T pin to the IOB

IOTP

pad through the output buffer of an IOB pad, when 3-state is

disabled. The delay varies depending on the SelectIO capa-

bility of the output buffer.

T

is described as the delay from IOB pad through the

IOPI

input buffer to the I-pin of an IOB pad. The delay varies

depending on the capability of the SelectIO input buffer.

Table 28 summarizes the value of T

. T

is

IOTPHZ

described as the delay from the T pin to the IOB pad

through the output buffer of an IOB pad, when 3-state is

enabled (i.e., a high impedance state).

T

is described as the delay from the O pin to the IOB

IOOP

pad through the output buffer of an IOB pad. The delay var-

ies depending on the capability of the SelectIO output

buffer.

(1,2)

Table 27: IOB Switching Characteristics

T

IOTP

IOPI

IOOP

IOSTANDARD

Attribute

Speed Grade

-11

Speed Grade

-11

Speed Grade

-11

Units

(1)

-12

1.00

1.01

1.00

-10

1.28

1.30

1.28

-12

1.61

1.65

1.58

1.99

1.59

-10

1.85

1.91

1.82

2.34

1.83

-12

1.61

1.65

1.58

1.99

1.59

-10

1.85

1.91

1.82

2.34

1.83

LVDS_25

1.15

1.71

ns

RSDS_25

LVDSEXT_25

LDT_25

1.15

1.71

1.16

1.75

1.15

1.68

BLVDS_25

ULVDS_25

1.15

2.15

1.15

1.68

PCI33_3

(PCI, 33 MHz, 3.3V)

0.76

0.87

0.97

2.52

2.22

2.76

2.46

3.02

2.72

2.52

2.22

2.76

2.46

3.02

2.72

ns

PCI66_3

(PCI, 66 MHz, 3.3V)

PCI-X

0.76

1.28

1.31

1.28

1.26

1.31

0.76

0.87

1.47

1.51

1.47

1.44

1.51

0.87

0.97

1.63

1.68

1.64

1.60

1.68

0.97

2.19

1.75

2.00

1.83

1.90

1.75

1.89

1.85

1.80

1.77

2.06

1.85

5.66

4.10

4.00

2.21

1.87

2.16

1.96

2.04

1.87

2.03

1.98

1.93

1.89

2.23

1.98

6.37

4.57

4.46

2.25

2.03

2.35

2.13

2.22

2.03

2.21

2.16

2.09

2.06

2.43

2.16

7.03

5.04

4.91

2.19

1.75

2.00

1.83

1.90

1.75

1.89

1.85

1.80

1.77

2.06

1.85

5.66

4.10

4.00

2.21

1.87

2.16

1.96

2.04

1.87

2.03

1.98

1.93

1.89

2.23

1.98

6.37

4.57

4.46

2.25

2.03

2.35

2.13

2.22

2.03

2.21

2.16

2.09

2.06

2.43

2.16

7.03

5.04

4.91

ns

GTL

GTLP

HSTL_I

HSTL_II

HSTL_III

HSTL_IV

HSTL_I _18

HSTL_II _18

HSTL_III _18

HSTL_IV_18

SSTL2_I

SSTL2_II

LVTTL, Slow, 2 mA

LVTTL, Slow, 4 mA

LVTTL, Slow, 6 mA

LVTTL, Slow, 8 mA

DS302 (v3.7) September 9, 2009

www.xilinx.com

Product Specification

19

Virtex-4 FPGA Data Sheet: DC and Switching Characteristics

(1,2)

Table 27: IOB Switching Characteristics

(Continued)

T

IOTP

IOPI

IOOP

IOSTANDARD

Attribute

Speed Grade

-11

Speed Grade

-11

Speed Grade

-11

Units

(1)

-12

0.76

0.69

-10

0.97

0.88

-12

3.26

2.87

2.60

3.96

2.87

2.51

2.34

2.09

1.88

6.98

4.92

4.07

3.25

2.83

2.11

5.98

3.55

2.93

2.09

1.93

1.79

4.77

4.09

3.53

2.90

2.75

2.33

3.20

2.66

2.36

2.13

2.06

-10

3.96

3.46

3.12

4.86

3.46

3.00

2.79

2.47

2.20

8.73

6.09

5.00

3.95

3.42

2.49

7.44

4.33

3.55

2.46

2.27

2.08

5.89

5.02

4.31

3.50

3.31

2.77

3.89

3.19

2.81

2.52

2.43

-12

3.26

2.87

2.60

3.96

2.87

2.51

2.34

2.09

1.88

6.98

4.92

4.07

3.25

2.83

2.11

5.98

3.55

2.93

2.09

1.93

1.79

4.77

4.09

3.53

2.90

2.75

2.33

3.20

2.66

2.36

2.13

2.06

-10

3.96

3.46

3.12

4.86

3.46

3.00

2.79

2.47

2.20

8.73

6.09

5.00

3.95

3.42

2.49

7.44

4.33

3.55

2.46

2.27

2.08

5.89

5.02

4.31

3.50

3.31

2.77

3.89

3.19

2.81

2.52

2.43

LVTTL, Slow, 12 mA

0.87

0.80

3.61

3.16

2.85

4.41

3.16

2.74

2.55

2.26

2.02

7.88

5.52

4.54

3.59

3.11

2.28

6.73

3.93

3.23

2.25

2.08

1.91

5.34

4.56

3.92

3.19

3.02

2.54

3.54

2.92

2.57

2.31

2.23

3.61

3.16

2.85

4.41

3.16

2.74

2.55

2.26

2.02

7.88

5.52

4.54

3.59

3.11

2.28

6.73

3.93

3.23

2.25

2.08

1.91

5.34

4.56

3.92

3.19

2.02

2.54

3.54

2.92

2.57

2.31

2.23

ns

LVTTL, Slow, 16 mA

LVTTL, Slow, 24 mA

LVTTL, Fast, 2 mA

LVTTL, Fast, 4 mA

LVTTL, Fast, 6 mA

LVTTL, Fast, 8 mA

LVTTL, Fast, 12 mA

LVTTL, Fast, 16 mA

LVTTL, Fast, 24 mA

LVCMOS33, Slow, 2 mA

LVCMOS33, Slow, 4 mA

LVCMOS33, Slow, 6 mA

LVCMOS33, Slow, 8 mA

LVCMOS33, Slow, 12 mA

LVCMOS33, Slow, 16 mA

LVCMOS33, Slow, 24 mA

LVCMOS33, Fast, 2 mA

LVCMOS33, Fast, 4 mA

LVCMOS33, Fast, 6 mA

LVCMOS33, Fast, 8 mA

LVCMOS33, Fast, 12 mA

LVCMOS33, Fast, 16 mA

LVCMOS33, Fast, 24 mA

LVCMOS25, Slow, 2 mA

LVCMOS25, Slow, 4 mA

LVCMOS25, Slow, 6 mA

LVCMOS25, Slow, 8 mA

LVCMOS25, Slow, 12 mA

LVCMOS25, Slow, 16 mA

LVCMOS25, Slow, 24 mA

LVCMOS25, Fast, 2 mA

LVCMOS25, Fast, 4 mA

LVCMOS25, Fast, 6 mA

LVCMOS25, Fast, 8 mA

LVCMOS25, Fast, 12 mA

DS302 (v3.7) September 9, 2009

www.xilinx.com

Product Specification

20

Virtex-4 FPGA Data Sheet: DC and Switching Characteristics

(1,2)

Table 27: IOB Switching Characteristics

(Continued)

T

IOTP

IOPI

IOOP

IOSTANDARD

Attribute

Speed Grade

-11

Speed Grade

-11

Speed Grade

-11

Units

(1)

-12

0.69

0.97

1.05

0.76

0.69

0.97

1.05

0.69

0.97

1.05

1.18

0.96

1.28

-10

0.88

1.25

1.34

0.97

0.88

1.25

1.34

0.88

1.25

1.34

1.51

1.23

1.64

-12

1.89

1.83

4.77

3.56

3.29

3.10

3.09

2.94

3.20

2.52

2.29

2.13

2.01

1.94

5.33

4.21

3.49

3.11

2.92

3.42

2.76

2.46

2.28

2.12

2.06

2.61

2.52

2.47

2.45

1.93

1.95

2.18

1.75

2.00

-10

2.21

2.13

5.89

4.35

4.00

3.76

3.74

3.55

3.89

3.02

2.72

2.52

2.36

2.27

6.61

4.88

4.26

3.77

3.53

4.17

3.32

2.94

2.71

2.50

2.43

3.13

3.02

2.95

2.93

2.27

2.28

2.58

2.03

2.35

-12

1.89

1.83

4.77

3.56

3.29

3.10

3.09

2.94

3.20

2.52

2.29

2.13

2.01

1.94

5.33

4.21

3.49

3.11

2.92

3.42

2.76

2.46

2.28

2.12

2.06

2.61

2.52

2.47

2.45

1.93

1.95

2.18

1.75

2.00

-10

2.21

2.13

5.89

4.35

4.00

3.76

3.74

3.55

3.89

3.02

2.72

2.52

2.36

2.27

6.61

4.88

4.26

3.77

3.53

4.17

3.32

2.94

2.71

2.50

2.43

3.13

3.02

2.95

2.93

2.27

2.28

2.58

2.03

2.35

LVCMOS25, Fast, 16 mA

LVCMOS25, Fast, 24 mA

LVCMOS18, Slow, 2 mA

LVCMOS18, Slow, 4 mA

LVCMOS18, Slow, 6 mA

LVCMOS18, Slow, 8 mA

LVCMOS18, Slow, 12 mA

LVCMOS18, Slow, 16 mA

LVCMOS18, Fast, 2 mA

LVCMOS18, Fast, 4 mA

LVCMOS18, Fast, 6 mA

LVCMOS18, Fast, 8 mA

LVCMOS18, Fast, 12 mA

LVCMOS18, Fast, 16 mA

LVCMOS15, Slow, 2 mA

LVCMOS15, Slow, 4 mA

LVCMOS15, Slow, 6 mA

LVCMOS15, Slow, 8 mA

LVCMOS15, Slow, 12 mA

LVCMOS15, Slow, 16 mA

LVCMOS15, Fast, 2 mA

LVCMOS15, Fast, 4 mA

LVCMOS15, Fast, 6 mA

LVCMOS15, Fast, 8 mA

LVCMOS15, Fast, 12 mA

LVCMOS15, Fast, 16 mA

LVDCI_33

0.80

1.12

1.20

0.87

0.80

1.12

1.20

0.80

1.12

1.20

1.36

1.11

1.47

2.03

1.96

5.34

3.95

3.64

3.42

3.41

3.24

3.54

2.75

2.49

2.31

2.17

2.09

5.99

4.70

3.87

3.43

3.21

3.79

3.03

2.69

2.48

2.29

2.23

2.86

2.76

2.69

2.68

2.08

2.09

2.36

1.87

2.16

2.03

1.96

5.34

3.95

3.64

3.42

3.41

3.24

3.54

2.75

2.49

2.31

2.17

2.09

5.99

4.70

3.87

3.43

3.21

3.79

3.03

2.69

2.48

2.29

2.23

2.86

2.76

2.69

2.68

2.08

2.09

2.36

1.87

2.16

ns

LVDCI_25

LVDCI_18

LVDCI_15

LVDCI_DV2_25

LVDCI_DV2_18

LVDCI_DV2_15

GTL_DCI⁽³⁾

GTLP_DCI⁽³⁾

HSTL_I_DCI⁽³⁾

DS302 (v3.7) September 9, 2009

www.xilinx.com

Product Specification

21

Virtex-4 FPGA Data Sheet: DC and Switching Characteristics

(1,2)

Table 27: IOB Switching Characteristics

(Continued)

T

IOTP

IOPI

IOOP

IOSTANDARD

Attribute

Speed Grade

-11

Speed Grade

-11

Speed Grade

-11

Units

(1)

-12

1.28

1.26

1.31

1.38

1.31

-10

1.64

1.60

1.68

1.77

1.68

-12

1.83

1.90

1.75

1.89

1.85

1.80

1.77

2.09

2.07

1.52

2.15

1.92

1.97

1.87

-10

2.13

2.22

2.03

2.21

2.16

2.09

2.06

2.46

2.45

1.74

2.54

2.24

2.32

2.18

-12

1.83

1.90

1.75

1.89

1.85

1.80

1.77

2.09

2.07

1.52

2.15

1.92

1.97

1.87

-10

2.13

2.22

2.03

2.21

2.16

2.09

2.06

2.46

2.45

1.74

2.54

2.24

2.32

2.18

HSTL_II_DCI⁽³⁾

1.47

1.96

ns

HSTL_III_DCI⁽³⁾

HSTL_IV_DCI⁽³⁾

HSTL_I_DCI_18⁽³⁾

HSTL_II_DCI_18⁽³⁾

HSTL_III_DCI_18⁽³⁾

HSTL_IV_DCI_18⁽³⁾

SSTL2_I_DCI⁽³⁾

SSTL2_II_DCI⁽³⁾

LVPECL_25

1.47

2.04

1.47

1.87

1.44

2.03

1.44

1.98

1.44

1.93

1.44

1.89

1.51

2.25

1.51

2.24

1.59

1.61

SSTL18_I

1.51

2.33

SSTL18_II

1.51

2.06

SSTL18_I_DCI⁽³⁾

SSTL18_II_DCI⁽³⁾

Notes:

1.51

2.12

1.51

2.00

1. The I/O standard is selected in the Xilinx ISE® software tool using the IOSTANDARD attribute.

2. All I/O timing specifications are measured with V_CCOat –5% from nominal.

3. The values of the DCI reference resistors must be within a 20Ω–100Ω range. Refer to UG070, Virtex-4 FPGA User Guide, for detailed information.

Table 28: IOB 3-state ON Output Switching Characteristics (T

)

IOTPHZ

Speed Grade

Symbol

Description

-12

-11

-10

Units

T_IOTPHZ

T input to Pad high-impedance

0.88

1.01

1.12

ns

Ethernet MAC Switching Characteristics

Consult UG074: Virtex-4 FPGA Embedded Tri-mode Ethernet MAC User Guide for further information.

Table 29: Maximum Ethernet MAC Performance

Speed Grade

Description

Ethernet MAC Maximum Performance

-12

-11

-10

Units

10/100/1000

Mb/s

DS302 (v3.7) September 9, 2009

www.xilinx.com

Product Specification

22

Virtex-4 FPGA Data Sheet: DC and Switching Characteristics

I/O Standard Adjustment Measurement Methodology

Input Delay Measurements

Table 30 shows the test setup parameters used for measuring input delay.

Table 30: Input Delay Measurement Methodology

I/O Standard

Attribute

V

(1,4,5)

V

REF

(1,3,5)

MEAS

(1,2)

Description

LVTTL (Low-Voltage Transistor-Transistor Logic)

LVCMOS (Low-Voltage CMOS), 3.3V

LVCMOS, 2.5V

V

L

H

LVTTL

0

3.0

1.4

–

LVCMOS33

LVCMOS25

LVCMOS18

LVCMOS15

3.3

2.5

1.8

1.5

1.65

1.25

0.9

LVCMOS, 1.8V

LVCMOS, 1.5V

0.75

PCI (Peripheral Component Interface),

33 MHz, 3.3V

PCI33_3

Per PCI™ Specification

–

PCI, 66 MHz, 3.3V

PCI66_3

PCIX

Per PCI Specification

–

PCI-X, 133 MHz, 3.3V

GTL (Gunning Transceiver Logic)

GTL Plus

Per PCI-X™ Specification

GTL

V_REF– 0.2

V_REF+ 0.2

V_REF

0.80

1.0

GTLP

V

_REF– 0.2

HSTL (High-Speed Transceiver Logic),

Class I & II

HSTL_I, HSTL_II

V_REF– 0.5

V_REF+ 0.5

V_REF

0.75

HSTL, Class III & IV

HSTL_III, HSTL_IV

V_REF– 0.5

V_REF+ 0.5

V_REF

0.90

HSTL, Class I & II, 1.8V

HSTL_I_18, HSTL_II_18

HSTL_III_18,

HSTL_IV_18

HSTL, Class III & IV, 1.8V

V_REF– 0.5

V_REF+ 0.5

V_REF

1.08

1.5

SSTL (Stub Terminated Transceiver Logic),

Class I & II, 3.3V

SSTL3_I, SSTL3_II

V_REF– 1.00

V_REF+ 1.00

SSTL, Class I & II, 2.5V

SSTL, Class I & II, 1.8V

SSTL2_I, SSTL2_II

V_REF– 0.75

V_REF– 0.5

V_REF+ 0.75

V_REF+ 0.5

V_REF

1.25

0.90

SSTL18_I, SSTL18_II

V_REF

(0.2xV_CCO

–

V_REF

(0.2 xV_CCO

+

AGP

Spec

AGP-2X/AGP (Accelerated Graphics Port)

AGP

V_REF

)

LVDS (Low-Voltage Differential Signaling), 2.5V

LVDSEXT (LVDS Extended Mode), 2.5V

ULVDS (Ultra LVDS), 2.5V

LVDS_25

1.2 – 0.125

0.6 – 0.125

1.2 + 0.125

0.6 + 0.125

1.2

0.6

LVDSEXT_25

ULVDS_25

LDT_25

LDT (HyperTransport), 2.5V

Notes:

1. Input delay measurement methodology parameters for LVDCI and HSLVDCI are the same as for LVCMOS standards of the same voltage.

Parameters for all other DCI standards are the same as for the corresponding non-DCI standards.

2. Input waveform switches between V_Land V_H.

3. Measurements are made at typical, minimum, and maximum V_REFvalues. Reported delays reflect worst case of these measurements. V_REFvalues

listed are typical.

4. Input voltage level from which measurement starts.

5. This is an input voltage reference that bears no relation to the V_REF/ V_MEASparameters found in IBIS models and/or noted in Figure 4.

DS302 (v3.7) September 9, 2009

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Product Specification

23

Virtex-4 FPGA Data Sheet: DC and Switching Characteristics

Output Delay Measurements

Output delays are measured using a Tektronix P6245

TDS500/600 probe (< 1 pF) across approximately 4 inches

of FR4 microstrip trace. Standard termination was used for

all testing. The propagation delay of the 4 inch trace is char-

acterized separately and subtracted from the final measure-

ment, and is therefore not included in the generalized test

setup shown in Figure 4.

Measurements and test conditions are reflected in the IBIS

models except where the IBIS format precludes it. Parame-

ters V

, R

, C

, and V

fully describe the test

REF

MEAS

conditions for each I/O standard. The most accurate predic-

tion of propagation delay in any given application can be

obtained through IBIS simulation, using the following

method:

1. Simulate the output driver of choice into the generalized

test setup, using values from Table 31.

V_REF

2. Record the time to V

.

MEAS

3. Simulate the output driver of choice into the actual PCB

trace and load, using the appropriate IBIS model or

capacitance value to represent the load.

R_REF

FPGA Output

4. Record the time to V

.

MEAS

V_MEAS

5. Compare the results of steps 2 and 4. The increase or

decrease in delay yields the actual worst-case

(voltage level when taking

delay measurement)

C_REF

propagation delay (clock-to-input) of the PCB trace.

(probe capacitance)

DS302_05_031708

Figure 4: Generalized Test Setup

Table 31: Output Delay Measurement Methodology

(1)

I/O Standard

Attribute

R

C

V

REF

(V)

REF

MEAS

(V)

Description

LVTTL (Low-Voltage Transistor-Transistor Logic)

LVCMOS (Low-Voltage CMOS), 3.3V

LVCMOS, 2.5V

(Ω)

1M

25

50

25

50

25

50

25

50

(pF)

LVTTL (all)

0

1.4

0

LVCMOS33

0

1.65

1.25

0.9

0

LVCMOS25

0

LVCMOS, 1.8V

LVCMOS18

0

LVCMOS, 1.5V

LVCMOS15

0

0.75

0.94

2.03

0.94

2.03

0.94

2.03

0.8

0

LVCMOS, 1.2V

LVCMOS12

0

PCI33_3 (rising edge)

PCI33_3 (falling edge)

PCI66_3 (rising edge)

PCI66_3 (falling edge)

PCIX (rising edge)

PCIX (falling edge

GTL

10⁽²⁾

10⁽³⁾

0

PCI (Peripheral Component Interface), 33 MHz, 3.3V

PCI, 66 MHz, 3.3V

3.3

0

3.3

PCI-X, 133 MHz, 3.3V

3.3

1.2

GTL (Gunning Transceiver Logic)

GTL Plus

GTLP

0

1.0

1.5

HSTL (High-Speed Transceiver Logic), Class I

HSTL, Class II

HSTL_I

0

V_REF

0.9

0.75

1.5

HSTL_II

0

HSTL, Class III

HSTL_III

0

HSTL, Class IV

HSTL_IV

0

0.9

1.5

HSTL, Class I, 1.8V

HSTL, Class II, 1.8V

HSTL, Class III, 1.8V

HSTL_I_18

0

V_REF

1.1

0.9

HSTL_II_18

HSTL_III_18

0

0.9

0

1.8

DS302 (v3.7) September 9, 2009

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Product Specification

24

Virtex-4 FPGA Data Sheet: DC and Switching Characteristics

Table 31: Output Delay Measurement Methodology (Continued)

(1)

REF

(pF)

I/O Standard

Attribute

R

C

V

REF

MEAS

(V)

Description

(Ω)

25

50

25

50

25

50

1M

50

(V)

1.8

0.9

1.25

1.2

0

HSTL, Class IV, 1.8V

HSTL_IV_18

0

1.1

SSTL (Stub Series Terminated Logic), Class I, 1.8V

SSTL, Class II, 1.8V

SSTL18_I

SSTL18_II

SSTL2_I

V_REF

1.2

SSTL, Class I, 2.5V

SSTL, Class II, 2.5V

SSTL2_II

LVDS_25

LVDSEXT_25

BLVDS_25

LDT_25

LVDS (Low-Voltage Differential Signaling), 2.5V

LVDSEXT (LVDS Extended Mode), 2.5V

BLVDS (Bus LVDS), 2.5V

LDT (HyperTransport), 2.5V

V_REF

0.6

LVPECL (Low-Voltage Positive Emitter-Coupled Logic),

2.5V

LVPECL_25

1M

0

0.90

1.65

0

LVDCI/HSLVDCI

(Low-Voltage Digitally Controlled Impedance), 3.3V

LVDCI_33, HSLVDCI_33

LVDCI/HSLVDCI, 2.5V

LVDCI/HSLVDCI, 1.8V

LVDCI/HSLVDCI, 1.5V

LVDCI_25, HSLVDCI_25

LVDCI_18, HSLVDCI_18

LVDCI_15, HSLVDCI_15

1M

1M &nb

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