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  • 北京元坤伟业科技有限公司

         该会员已使用本站17年以上

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  • 深圳市意好科技有限公司

     该会员已使用本站15年以上
  • XC4VLX25-11FFG668C 三甲现货
  • 数量1320 
  • 厂家XILINX 
  • 封装FBGA 
  • 批号24+ 
  • 原装认证,现货供应!实力商家
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  • HECC GROUP CO.,LIMITED

     该会员已使用本站17年以上
  • XC4VLX25-11FFG668C 三甲现货
  • 数量953 
  • 厂家XILINX 
  • 封装BGA 
  • 批号24+ 
  • 渠道商,有出厂合格证,原包原盒正规报关!
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  • 集好芯城

     该会员已使用本站13年以上
  • XC4VLX25-11FFG668C 现货库存
  • 数量2756 
  • 厂家XILINX(赛灵思) 
  • 封装 
  • 批号22+ 
  • 原装原厂现货
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  • 深圳市毅创腾电子科技有限公司

     该会员已使用本站16年以上
  • XC4VLX25-11FFG668C 现货库存
  • 数量1200 
  • 厂家XILINX代理主营品牌 
  • 封装BGA 
  • 批号22+ 
  • Xilinx代理旗下分销!原装正品!
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    QQ:2355507169QQ:2355507169 复制
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  • HECC GROUP CO.,LIMITED

     该会员已使用本站17年以上
  • XC4VLX25-11FFG668C 现货库存
  • 数量1960 
  • 厂家XILINX 
  • 封装BGA 
  • 批号24+ 
  • 假一罚百,有原厂COC!深圳部分存货,北美、新加坡可发货
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  • 深圳市毅创弘电子科技有限公司

     该会员已使用本站8年以上
  • XC4VLX25-11FFG668C 现货库存
  • 数量68800 
  • 厂家Xilinx 
  • 封装668-BBGAFCBGA 
  • 批号最新批次 
  • XILINX专营全新进口原装正品现货
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  • 0755-23600446 QQ:2881277219
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  • 深圳市意好科技有限公司

     该会员已使用本站15年以上
  • XC4VLX25-11FFG668C 现货库存
  • 数量1560 
  • 厂家XILINX 
  • 封装 
  • 批号24+ 
  • 代理商
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  • 深圳市宗天技术开发有限公司

     该会员已使用本站10年以上
  • XC4VLX25-11FFG668C 现货库存
  • 数量28600 
  • 厂家11+ 
  • 封装
  • 批号21+ 
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  • 深圳市芯脉实业有限公司

     该会员已使用本站11年以上
  • XC4VLX25-11FFG668C 现货库存
  • 数量5980 
  • 厂家XILINX 
  • 封装BGA 
  • 批号22+ 
  • 新到现货、一手货源、当天发货、bom配单
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  • 深圳市斌腾达科技有限公司

     该会员已使用本站9年以上
  • XC4VLX25-11FFG668C 优势库存
  • 数量850 
  • 厂家XILINX 
  • 封装BGA 
  • 批号19+/20+ 
  • 100%进口原装!长期供应!绝对优势价格(诚信经营
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  • 深圳市迈锐达科技有限公司

     该会员已使用本站14年以上
  • XC4VLX25-11FFG668C 热卖库存
  • 数量391 
  • 厂家XILINX 
  • 封装BGA 
  • 批号1042+ 
  • 真实库存!绝对原装!
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    QQ:1181043992QQ:1181043992 复制
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  • 深圳市拓森弘电子有限公司

     该会员已使用本站1年以上
  • XC4VLX25-11FFG668C
  • 数量5300 
  • 厂家XILINX(赛灵思) 
  • 封装FCBGA-668(27x27) 
  • 批号21+ 
  • 全新原装正品,库存现货实报
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  • 深圳市芯福林电子有限公司

     该会员已使用本站15年以上
  • XC4VLX25-11FFG668C
  • 数量65000 
  • 厂家XILINX(赛灵思) 
  • 封装FCBGA-668(27x27) 
  • 批号23+ 
  • 真实库存全新原装正品!代理此型号
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  • 0755-23605827 QQ:2881495753
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  • 深圳市芯福林电子有限公司

     该会员已使用本站15年以上
  • XC4VLX25-11FFG668C
  • 数量1600 
  • 厂家XILINX 
  • 封装FBGA668 
  • 批号新年份 
  • 真实库存全新原装正品!代理此型号!
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  • 深圳市旺能芯科技有限公司

     该会员已使用本站4年以上
  • XC4VLX25-11FFG668C
  • 数量26000 
  • 厂家XILINX 
  • 封装FCBGA-668(27x27) 
  • 批号21+ 
  • 深圳全新原装库存现货
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  • 深圳市龙腾新业科技有限公司

     该会员已使用本站17年以上
  • XC4VLX25-11FFG668C
  • 数量2756 
  • 厂家XILINX(赛灵思) 
  • 封装 
  • 批号24+ 
  • 原装原厂现货
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  • 0755-84509636 QQ:562765057QQ:370820820
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  • 深圳市恒益昌科技有限公司

     该会员已使用本站6年以上
  • XC4VLX25-11FFG668C
  • 数量450 
  • 厂家XILINX 
  • 封装BGA 
  • 批号23+ 
  • 原装正品长期供货
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  • 0755-82723761 QQ:3336148967QQ:974337758
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  • 深圳市华科泰电子商行

     该会员已使用本站13年以上
  • XC4VLX25-11FFG668C
  • 数量6800 
  • 厂家XILINX 
  • 封装BGA 
  • 批号07+无铅 
  • 绝对原装现货特价
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  • 深圳市和诚半导体有限公司

     该会员已使用本站11年以上
  • XC4VLX25-11FFG668C
  • 数量5600 
  • 厂家XILINX 
  • 封装FBGA668 
  • 批号23+ 
  • 只做原装正品,深圳现货
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    QQ:1977615742QQ:1977615742 复制
  • 18929336553 QQ:2276916927QQ:1977615742
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  • 深圳市得捷芯城科技有限公司

     该会员已使用本站11年以上
  • XC4VLX25-11FFG668C
  • 数量
  • 厂家XILINX(赛灵思) 
  • 封装FCBGA-668 
  • 批号23+ 
  • 优势代理渠道,原装正品,可全系列订货开增值税票
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  • 首天国际(深圳)科技有限公司

     该会员已使用本站16年以上
  • XC4VLX25-11FFG668C
  • 数量1280 
  • 厂家XILINX 
  • 封装BGA 
  • 批号2024+ 
  • 百分百原装正品,现货库存
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    QQ:1318502189QQ:1318502189 复制
  • 0755-82807802 QQ:528164397QQ:1318502189
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  • 深圳市恒佳微电子有限公司

     该会员已使用本站12年以上
  • XC4VLX25-11FFG668C
  • 数量
  • 厂家464 
  • 封装BGA 
  • 批号 
  • 正品原装 支持最低价
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  • 755-82533156 QQ:864187665QQ:1807086236
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  • 深圳市西源信息科技有限公司

     该会员已使用本站9年以上
  • XC4VLX25-11FFG668C
  • 数量8800 
  • 厂家XILINX 
  • 封装FCBGA-668(27x27) 
  • 批号最新批号 
  • 原装现货零成本有接受价格就出
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    QQ:408391813QQ:408391813 复制
  • 0755-84876394 QQ:3533288158QQ:408391813
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  • 北京首天国际有限公司

     该会员已使用本站16年以上
  • XC4VLX25-11FFG668CS2
  • 数量406 
  • 厂家XILINX 
  • 封装原厂封装 
  • 批号2024+ 
  • 百分百原装正品,现货库存
  • QQ:528164397QQ:528164397 复制
    QQ:1318502189QQ:1318502189 复制
  • 010-62565447 QQ:528164397QQ:1318502189
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  • 深圳市雅维特电子有限公司

     该会员已使用本站15年以上
  • XC4VLX25-11FFG668C
  • 数量8000 
  • 厂家Xilinx Inc 
  • 封装深圳原装现货0755-83975781 
  • 批号BGA 
  • QQ:767621813QQ:767621813 复制
    QQ:1152937841QQ:1152937841 复制
  • 0755-83975781 QQ:767621813QQ:1152937841
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  • 深圳市晶美隆科技有限公司

     该会员已使用本站14年以上
  • XC4VLX25-11FFG668C
  • 数量18530 
  • 厂家XILINX 
  • 封装BGA 
  • 批号23+ 
  • 全新原装正品现货热卖
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  • 柒号芯城电子商务(深圳)有限公司

     该会员已使用本站13年以上
  • XC4VLX25-11FFG668C
  • 数量700000 
  • 厂家XILINX 
  • 封装FCBGA-668(27X27) 
  • 批号2023+ 
  • 柒号芯城跟原厂的距离只有0.07公分
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  • 深圳市宏世佳电子科技有限公司

     该会员已使用本站13年以上
  • XC4VLX25-11FFG668C
  • 数量3145 
  • 厂家XILINX 
  • 封装BGA 
  • 批号2023+ 
  • 全新原厂原装产品、公司现货销售
  • QQ:2881894392QQ:2881894392 复制
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  • 深圳市宏捷佳电子科技有限公司

     该会员已使用本站6年以上
  • XC4VLX25-11FFG668C
  • 数量6500 
  • 厂家XILINX 
  • 封装BGA 
  • 批号24+ 
  • 全新原装★真实库存★含13点增值税票!
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  • 深圳市宏世佳电子科技有限公司

     该会员已使用本站13年以上
  • XC4VLX25-11FFG668C
  • 数量3785 
  • 厂家Xilinx 
  • 封装668-BBGA,FCBGA 
  • 批号2023+ 
  • 全新原厂原装产品、公司现货销售
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  • 深圳市西昂特科技有限公司

     该会员已使用本站13年以上
  • XC4VLX25-11FFG668C
  • 数量1000 
  • 厂家专注XILINX 
  • 封装BGA668 
  • 批号2001+ 
  • 代理渠道,原装现货
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  • 深圳市积美福电子科技有限公司

     该会员已使用本站4年以上
  • XC4VLX25-11FFG668C
  • 数量1560 
  • 厂家XILINX/赛灵思 
  • 封装BGA 
  • 批号21+ 
  • 只做原装正品,深圳现货库存
  • QQ:647176908QQ:647176908 复制
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  • 深圳市华芯盛世科技有限公司

     该会员已使用本站13年以上
  • XC4VLX25-11FFG668C
  • 数量865000 
  • 厂家XILINX/赛灵思 
  • 封装BGA 
  • 批号最新批号 
  • 一级代理,原装特价现货!
  • QQ:2881475757QQ:2881475757 复制
  • 0755-83225692 QQ:2881475757
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  • HECC GROUP CO.,LIMITED

     该会员已使用本站17年以上
  • XC4VLX25-11FFG668C
  • 数量1960 
  • 厂家XILINX 
  • 封装BGA 
  • 批号2021+ 
  • 原装假一赔十!可提供正规渠道证明!
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  • 深圳市富科达科技有限公司

     该会员已使用本站13年以上
  • XC4VLX25-11FFG668C
  • 数量50000 
  • 厂家XILINX 
  • 封装BGA 
  • 批号21+ 
  • 原装现货
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  • 深圳市华斯顿电子科技有限公司

     该会员已使用本站16年以上
  • XC4VLX25-11FFG668C
  • 数量7233 
  • 厂家XILINX 
  • 封装BGA668 
  • 批号2023+ 
  • 绝对原装正品全新进口深圳现货
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  • 深圳市毅创腾电子科技有限公司

     该会员已使用本站16年以上
  • XC4VLX25-11FFG668C
  • 数量3000 
  • 厂家XILINX 
  • 封装BGA 
  • 批号22+ 
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  • 深圳市晶美隆科技有限公司

     该会员已使用本站14年以上
  • XC4VLX25-11FFG668C
  • 数量1481 
  • 厂家xilinx 
  • 封装BGA 
  • 批号23+ 
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  • 深圳市恒达亿科技有限公司

     该会员已使用本站12年以上
  • XC4VLX25-11FFG668C
  • 数量3000 
  • 厂家XILINX 
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产品型号XC4VLX25-11FFG668C的概述

XC4VLX25-11FFG668C芯片概述 XC4VLX25-11FFG668C是一款由Xilinx公司生产的FPGA(现场可编程门阵列)芯片,属于Virtex-4系列。这个系列的FPGA以其高性能、灵活性以及支持多种应用而广受欢迎。XC4VLX25具有丰富的逻辑资源和高度的集成度,适用于各类复杂的计算和数据处理任务,特别是在数字信号处理、通信、军事以及工业控制等领域。 作为一款运行在较高频率下的FPGA,XC4VLX25能在多个任务间切换,具有高强度的并行处理能力。此外,该芯片支持多种IO标准,能够与多种外部设备和接口进行有效连接。它的配置和编程相对简单,开发者可利用Xilinx提供的ISE或Vivado工具进行设计和调试。 XC4VLX25-11FFG668C详细参数 - 逻辑单元: 25,000 - 查找表 (LUT): 每个逻辑单元可实现4-input LUT - 寄存器: ...

产品型号XC4VLX25-11FFG668IS2的Datasheet PDF文件预览

`
0
R
Virtex-4 Family Overview  
0
0
DS112 (v3.1) August 30, 2010  
Product Specification  
General Description  
Combining Advanced Silicon Modular Block (ASMBL™) architecture with a wide variety of flexible features, the Virtex®-4  
family from Xilinx greatly enhances programmable logic design capabilities, making it a powerful alternative to ASIC  
technology. Virtex-4 FPGAs comprise three platform families—LX, FX, and SX—offering multiple feature choices and  
combinations to address all complex applications. The wide array of Virtex-4 FPGA hard-IP core blocks includes the  
PowerPC® processors (with a new APU interface), tri-mode Ethernet MACs, 622 Mb/s to 6.5 Gb/s serial transceivers,  
dedicated DSP slices, high-speed clock management circuitry, and source-synchronous interface blocks. The basic Virtex-4  
FPGA building blocks are enhancements of those found in the popular Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and  
Virtex-II Pro X product families, so previous-generation designs are upward compatible. Virtex-4 devices are produced on a  
state-of-the-art 90 nm copper process using 300 mm (12-inch) wafer technology.  
Summary of Virtex-4 Family Features  
Three Families — LX/SX/FX  
SelectIO™ Technology  
-
-
Virtex-4 LX: High-performance logic applications solution  
Virtex-4 SX: High-performance solution for digital signal  
processing (DSP) applications  
Virtex-4 FX: High-performance, full-featured solution for  
embedded platform applications  
-
-
-
-
1.5V to 3.3V I/O operation  
Built-in ChipSync™ source-synchronous technology  
Digitally controlled impedance (DCI) active termination  
Fine grained I/O banking (configuration in one bank)  
-
Flexible Logic Resources  
Xesium™ Clock Technology  
Secure Chip AES Bitstream Encryption  
90 nm Copper CMOS Process  
1.2V Core Voltage  
Flip-Chip Packaging including Pb-Free Package  
Choices  
-
-
-
Digital clock manager (DCM) blocks  
Additional phase-matched clock dividers (PMCD)  
Differential global clocks  
XtremeDSP™ Slice  
-
-
-
18 x 18, two’s complement, signed Multiplier  
Optional pipeline stages  
Built-in Accumulator (48-bit) and Adder/Subtracter  
RocketIO™ 622 Mb/s to 6.5 Gb/s Multi-Gigabit  
Transceiver (MGT) [FX only]  
Smart RAM Memory Hierarchy  
-
IBM PowerPC RISC Processor Core [FX only]  
Distributed RAM  
-
Dual-port 18-Kbit RAM blocks  
-
-
PowerPC 405 (PPC405) Core  
Auxiliary Processor Unit Interface (User Coprocessor)  
·
·
Optional pipeline stages  
Optional programmable FIFO logic automatically  
remaps RAM signals as FIFO signals  
Multiple Tri-Mode Ethernet MACs [FX only]  
-
High-speed memory interface supports DDR and DDR-2  
SDRAM, QDR-II, and RLDRAM-II.  
Table 1: Virtex-4 FPGA Family Members  
(1)  
Block RAM  
Max  
Configurable Logic Blocks (CLBs)  
Max  
PowerPC  
Processor Ethernet Transceiver  
RocketIO  
Total Max  
I/O User  
Banks I/O  
(3)  
Array  
Logic  
Cells  
Distributed XtremeDSP 18 Kb  
Slices RAM (Kb)  
Block  
Slices(2) Blocks RAM (Kb)  
Blocks  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
MACs  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
Blocks  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
Device  
DCMs PMCDs  
Row x Col  
32  
48  
64  
64  
80  
96  
96  
96  
XC4VLX15  
XC4VLX25  
XC4VLX40  
XC4VLX60  
XC4VLX80  
64 x 24  
96 x 28  
13,824 6,144  
24,192 10,752  
96  
168  
288  
416  
560  
768  
1056  
1392  
48  
72  
864  
4
8
0
4
4
4
8
8
8
8
9
320  
448  
640  
640  
768  
960  
960  
960  
1,296  
1,728  
2,880  
3,600  
4,320  
5,184  
6,048  
11  
13  
13  
15  
17  
17  
17  
128 x 36 41,472 18,432  
128 x 52 59,904 26,624  
160 x 56 80,640 35,840  
96  
8
160  
200  
240  
288  
336  
8
12  
12  
12  
12  
XC4VLX100 192 x 64 110,592 49,152  
XC4VLX160 192 x 88 152,064 67,584  
XC4VLX200 192 x 116 200,448 89,088  
© Copyright 2004–2010 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and  
other countries. The PowerPC name and logo are registered trademarks of IBM Corp. and used under license. All other trademarks are the property of their respective owners.  
DS112 (v3.1) August 30, 2010  
www.xilinx.com  
Product Specification  
1
R
Virtex-4 Family Overview  
Table 1: Virtex-4 FPGA Family Members (Continued)  
(1)  
Block RAM  
Max  
Configurable Logic Blocks (CLBs)  
Max  
PowerPC  
Processor Ethernet Transceiver  
Blocks  
RocketIO  
Total Max  
I/O User  
Banks I/O  
(3)  
Array  
Logic  
Cells  
Distributed XtremeDSP 18 Kb  
Slices RAM (Kb)  
Block  
Slices(2) Blocks RAM (Kb)  
MACs  
N/A  
N/A  
N/A  
2
Blocks  
N/A  
N/A  
N/A  
N/A  
8
Device  
DCMs PMCDs  
Row x Col  
128  
192  
512  
32  
XC4VSX25  
XC4VSX35  
XC4VSX55  
XC4VFX12  
XC4VFX20  
XC4VFX40  
XC4VFX60  
64 x 40  
96 x 40  
23,040 10,240  
34,560 15,360  
160  
240  
384  
86  
128  
192  
320  
36  
2,304  
3,456  
5,760  
648  
4
8
0
4
4
0
0
4
8
8
8
N/A  
N/A  
N/A  
1
9
320  
448  
640  
320  
320  
448  
576  
768  
896  
11  
13  
9
128 x 48 55,296 24,576  
8
64 x 24  
64 x 36  
96 x 52  
12,312 5,472  
19,224 8,544  
41,904 18,624  
4
32  
134  
291  
395  
659  
987  
68  
1,224  
2,592  
4,176  
6,768  
9,936  
4
1
2
9
48  
144  
232  
376  
552  
8
2
4
12  
11  
13  
15  
17  
128  
160  
192  
128 x 52 56,880 25,280  
12  
12  
20  
2
4
16  
XC4VFX100 160 x 68 94,896 42,176  
XC4VFX140 192 x 84 142,128 63,168  
Notes:  
2
4
20  
2
4
24  
1.  
2.  
3.  
One CLB = Four Slices = Maximum of 64 bits.  
Each XtremeDSP slice contains one 18 x 18 multiplier, an adder, and an accumulator  
Some of the row/column array is used by the processors in the FX devices.  
System Blocks Common to All Virtex-4 Families  
Xesium Clock Technology  
500 MHz XtremeDSP Slices  
Dedicated 18-bit x 18-bit multiplier,  
multiply-accumulator, or multiply-adder blocks  
Optional pipeline stages for enhanced performance  
Optional 48-bit accumulator for multiply accumulate  
(MACC) operation  
Integrated adder for complex-multiply or multiply-add  
operation  
Cascadeable Multiply or MACC  
Up to twenty Digital Clock Manager (DCM) modules  
-
-
-
Precision clock deskew and phase shift  
Flexible frequency synthesis  
Dual operating modes to ease performance trade-off  
decisions  
-
-
-
-
-
-
Improved maximum input/output frequency  
Improved phase shifting resolution  
Reduced output jitter  
Low-power operation  
Enhanced phase detectors  
Up to 100% speed improvement over previous  
generation devices.  
Wide phase shift range  
Companion Phase-Matched Clock Divider (PMCD)  
blocks  
Differential clocking structure for optimized low-jitter  
clocking and precise duty cycle  
500 MHz Integrated Block Memory  
Up to 10 Mb of integrated block memory  
Optional pipeline stages for higher performance  
Multi-rate FIFO support logic  
32 Global Clock networks  
Regional I/O and Local clocks  
-
-
-
Full and Empty Flag support  
Fully programmable AF and AE Flags  
Synchronous/ Asynchronous Operation  
Dual-port architecture  
Independent read and write port width selection (RAM  
only)  
18 Kbit blocks (memory and parity/sideband memory  
support)  
Configurations from 16K x 1 to 512 x 36  
(4K x 4 to 512 x 36 for FIFO operation)  
Byte-write capability (connection to PPC405, etc.)  
Dedicated cascade routing to form 32K x 1 memory  
without using FPGA routing  
Flexible Logic Resources  
Up to 40% speed improvement over previous  
generation devices  
Up to 200,000 logic cells including:  
-
Up to 178,176 internal registers with clock enable  
(XC4VLX200)  
-
-
Up to 178,176 look-up tables (LUTs)  
Logic expanding multiplexers and I/O registers  
Cascadable variable shift registers or distributed  
memory capability  
Up to 100% speed improvement over previous  
generation devices.  
DS112 (v3.1) August 30, 2010  
www.xilinx.com  
Product Specification  
2
R
Virtex-4 Family Overview  
SelectIO Technology  
Digitally Controlled Impedance (DCI)  
Active I/O Termination  
Up to 960 user I/Os  
Wide selections of I/O standards from 1.5V to 3.3V  
Extremely high-performance  
Optional series or parallel termination  
Temperature compensation  
-
-
600 Mb/s HSTL & SSTL (on all single-ended I/O)  
1 Gb/s LVDS (on all differential I/O pairs)  
Configuration  
True differential termination  
Selected low-capacitance I/Os for improved signal  
integrity  
Same edge capture at input and output I/Os  
Memory interface support for DDR and DDR-2  
SDRAM, QDR-II, and RLDRAM-II.  
256-bit AES bitstream decryption provides intellectual  
property (IP) security  
Improved bitstream error detection/correction capability  
Fast SelectMAP configuration  
JTAG support  
Readback capability  
90 nm Copper CMOS Process  
1.2V Core Voltage  
ChipSync Technology  
Integrated with SelectIO technology to simplify  
source-synchronous interfaces  
Per-bit deskew capability built in all I/O blocks (variable  
input delay line)  
Dedicated I/O and regional clocking resources (pin and  
trees)  
Flip-Chip Packaging  
Pb-Free packages available with production devices.  
Built in data serializer/deserializer logic in all I/O and  
clock dividers  
Memory/Networking/Telecommunication interfaces up  
to 1 Gb/s+ DDR  
System Blocks Specific to the Virtex-4 FX Family  
Auxiliary Processor Unit (APU) Interface for direct  
connection from PPC405 to coprocessors in fabric  
RocketIO Multi-Gigabit Transceiver (MGT)  
Full-duplex serial transceiver (MGT) capable of  
622 Mb/s to 6.5 Gb/s baud rates  
-
-
-
-
APU can run at different clock rates  
Supports autonomous instructions: no pipeline stalls  
32-bit instruction and 64-bit data  
8B/10B, 64B/66B, user-defined FPGA logic, or no data  
encoding/decoding  
4-cycle cache line transfer  
Channel bonding support  
CRC generation and checking  
Tri-Mode Ethernet Media Access Controller  
Programmable TX pre-emphasis or pre-equalization  
Programmable RX continuous time equalization  
Programmable RX decision feedback equalization  
On-chip RX AC coupling  
RX signal detect and loss of signal indicator  
TX driver electrical idle mode  
IEEE 802.3 compliant  
Operates at 10, 100, and 1,000 Mb/s  
Supports tri-mode auto-detect  
Receive address filter  
Fully monolithic 1000Base-X solution with RocketIO  
MGT  
Implements SGMII through RocketIO MGT to external  
PHY device  
Supports multiple PHY (MII, GMII, etc.) interfaces  
through an I/O resource  
Receive and transmit statistics available through  
separate interfaces  
Separate host and client interfaces  
Support for jumbo frames  
User dynamic reconfiguration using secondary  
configuration bus  
PowerPC 405 Processor RISC Core  
Embedded PowerPC 405 processor (PPC405) core  
-
-
-
-
-
Up to 450 MHz operation  
Five-stage data path pipeline  
16 KB instruction cache  
16 KB data cache  
Enhanced instruction and data on-chip memory  
(OCM) controllers  
Flexible, user-configurable host interface  
-
Additional frequency ratio options between  
PPC405 and Processor Local Bus  
DS112 (v3.1) August 30, 2010  
www.xilinx.com  
Product Specification  
3
R
Virtex-4 Family Overview  
Architectural Description: Virtex-4 FPGA Array Overview  
Virtex-4 devices are user-programmable gate arrays with  
various configurable elements and embedded cores opti-  
mized for high-density and high-performance system  
designs. Virtex-4 devices implement the following function-  
ality:  
Digital Clock Manager (DCM) blocks provide  
self-calibrating, fully digital solutions for clock  
distribution delay compensation, clock  
multiplication/division, and coarse-/fine-grained clock  
phase shifting.  
I/O blocks provide the interface between package pins  
and the internal configurable logic. Most popular and  
leading-edge I/O standards are supported by  
programmable I/O blocks (IOBs). The IOBs are  
enhanced for source-synchronous applications.  
Source-synchronous optimizations include per-bit  
deskew, data serializer/deserializer, clock dividers, and  
dedicated local clocking resources.  
Additionally, FX devices support the following embedded  
system functionality:  
Integrated high-speed serial transceivers enable data  
rates up to 6.5 Gb/s per channel.  
Embedded IBM PowerPC 405 Processor RISC CPU  
(up to 450 MHz) with the auxiliary processor unit  
interface  
10/100/1000 Ethernet media-access control (EMAC)  
cores.  
Configurable Logic Blocks (CLBs), the basic logic  
elements for Xilinx FPGAs, provide combinatorial and  
synchronous logic as well as distributed memory and  
SRL16 shift register capability.  
Block RAM modules provide flexible 18Kbit true  
dual-port RAM, that are cascadable to form larger  
memory blocks. In addition, Virtex-4 FPGA block RAMs  
contain optional programmable FIFO logic for  
increased device utilization.  
The general routing matrix (GRM) provides an array of rout-  
ing switches between each component. Each programma-  
ble element is tied to a switch matrix, allowing multiple  
connections to the general routing matrix. The overall pro-  
grammable interconnection is hierarchical and designed to  
support high-speed designs.  
All programmable elements, including the routing  
resources, are controlled by values stored in static memory  
cells. These values are loaded in the memory cells during  
configuration and can be reloaded to change the functions  
of the programmable elements.  
Cascadable embedded XtremeDSP slices with 18-bit x  
18-bit dedicated multipliers, integrated Adder, and  
48-bit accumulator.  
Virtex-4 FPGA Features  
This section briefly describes the features of the Virtex-4 family of FPGAs.  
HSTL 1.5V and 1.8V (Class I, II, III, and IV)  
SSTL 1.8V and 2.5V (Class I and II)  
Input/Output (SelectIO) Blocks  
IOBs are programmable and can be categorized as follows:  
The DCI I/O feature can be configured to provide on-chip  
termination for each single-ended I/O standard and some  
differential I/O standards.  
Programmable single-ended or differential (LVDS)  
operation  
Input block with an optional single data rate (SDR) or  
double data rate (DDR) register  
Output block with an optional SDR or DDR register  
Bidirectional block  
Per-bit deskew circuitry  
The IOB elements also support the following differential sig-  
naling I/O standards:  
LVDS and Extended LVDS (2.5V only)  
BLVDS (Bus LVDS)  
ULVDS  
Hypertransport™  
Differential HSTL 1.5V and 1.8V (Class II)  
Differential SSTL 1.8V and 2.5V (Class II)  
Dedicated I/O and regional clocking resources  
Built in data serializer/deserializer  
The IOB registers are either edge-triggered D-type flip-flops  
or level-sensitive latches.  
Two adjacent pads are used for each differential pair. Two or  
four IOB blocks connect to one switch matrix to access the  
routing resources.  
IOBs support the following single-ended standards:  
LVTTL  
LVCMOS (3.3V, 2.5V, 1.8V, and 1.5V)  
PCI (33 and 66 MHz)  
PCI-X  
Per-bit deskew circuitry allows for programmable signal  
delay internal to the FPGA. Per-bit deskew flexibly provides  
fine-grained increments of delay to carefully produce a  
GTL and GTLP  
DS112 (v3.1) August 30, 2010  
www.xilinx.com  
Product Specification  
4
R
Virtex-4 Family Overview  
range of signal delays. This is especially useful for synchro-  
nizing signal edges in source synchronous interfaces.  
XtremeDSP Slices  
The XtremeDSP slices contain a dedicated 18 x 18-bit 2’s  
complement signed multiplier, adder logic, and a 48-bit  
accumulator. Each multiplier or accumulator can be used  
independently. These blocks are designed to implement  
extremely efficient and high-speed DSP applications.  
General purpose I/O in select locations (four per bank) are  
designed to be “regional clock capable” I/O by adding spe-  
cial hardware connections for I/O in the same locality. These  
regional clock inputs are distributed within a limited region  
to minimize clock skew between IOBs. Regional I/O clock-  
ing supplements the global clocking resources.  
The block DSP feature in Virtex-4 devices are further dis-  
cussed in XtremeDSP Design Considerations.  
Data serializer/deserializer capability is added to every I/O  
to support source synchronous interfaces. A serial-to-paral-  
lel converter with associated clock divider is included in the  
input path, and a parallel-to-serial converter in the output  
path.  
Global Clocking  
The DCM and global-clock multiplexer buffers provide a  
complete solution for designing high-speed clock networks.  
Up to twenty DCM blocks are available. To generate  
deskewed internal or external clocks, each DCM can be  
used to eliminate clock distribution delay. The DCM also  
provides 90°, 180°, and 270° phase-shifted versions of the  
output clocks. Fine-grained phase shifting offers higher res-  
olution phase adjustment with fraction of the clock period  
increments. Flexible frequency synthesis provides a clock  
output frequency equal to a fractional or integer multiple of  
the input clock frequency.  
An in-depth guide to the Virtex-4 FPGA IOB is discussed in  
the Virtex-4 FPGA User Guide.  
Configurable Logic Blocks (CLBs)  
A CLB resource is made up of four slices. Each slice is  
equivalent and contains:  
Two function generators (F & G)  
Two storage elements  
Arithmetic logic gates  
Large multiplexers  
Fast carry look-ahead chain  
Virtex-4 devices have 32 global-clock MUX buffers. The  
clock tree is designed to be differential. Differential clocking  
helps reduce jitter and duty cycle distortion.  
The function generators F & G are configurable as 4-input  
look-up tables (LUTs). Two slices in a CLB can have their  
LUTs configured as 16-bit shift registers, or as 16-bit distrib-  
uted RAM. In addition, the two storage elements are either  
edge-triggered D-type flip-flops or level sensitive latches.  
Each CLB has internal fast interconnect and connects to a  
switch matrix to access general routing resources.  
Routing Resources  
All components in Virtex-4 devices use the same intercon-  
nect scheme and the same access to the global routing  
matrix. Timing models are shared, greatly improving the  
predictability of the performance for high-speed designs.  
Boundary-Scan  
The Virtex-4 FPGA CLBs are further discussed in the  
Virtex-4 FPGA User Guide.  
Boundary-Scan instructions and associated data registers  
support a standard methodology for accessing and config-  
uring Virtex-4 devices, complying with IEEE standards  
1149.1 and 1532.  
Block RAM  
The block RAM resources are 18 Kb true dual-port RAM  
blocks, programmable from 16K x 1 to 512 x 36, in various  
depth and width configurations. Each port is totally synchro-  
nous and independent, offering three “read-during-write”  
modes. Block RAM is cascadable to implement large  
embedded storage blocks. Additionally, back-end pipeline  
registers, clock control circuitry, built-in FIFO support, and  
byte write enable are new features supported in the Virtex-4  
FPGA.  
Configuration  
Virtex-4 devices are configured by loading the bitstream into  
internal configuration memory using one of the following  
modes:  
Slave-serial mode  
Master-serial mode  
Slave SelectMAP mode  
Master SelectMAP mode  
Boundary-Scan mode (IEEE-1532)  
The block RAM feature in Virtex-4 devices is further dis-  
cussed in the Virtex-4 FPGA User Guide.  
Optional 256-bit AES decryption is supported on-chip (with  
software bitstream encryption) providing Intellectual Prop-  
erty security.  
DS112 (v3.1) August 30, 2010  
www.xilinx.com  
Product Specification  
5
R
Virtex-4 Family Overview  
Virtex-4 FX Family  
This section briefly describes blocks available only in FX devices.  
RocketIO Multi-Gigabit Transceiver  
One or Two PowerPC 405 Processor Cores  
32-bit Harvard Architecture  
5-Stage Execution Pipeline  
Integrated 16KB Level 1 Instruction Cache and 16KB  
Level 1 Data Cache  
Integrated Level 1 Cache Parity Generation and  
Checking  
CoreConnect™ Bus Architecture  
Efficient, high-performance on-chip memory (OCM)  
interface to block RAM  
PLB Synchronization Logic (Enables Non-Integer  
CPU-to-PLB Clock Ratios)  
Auxiliary Processor Unit (APU) Interface and Integrated  
APU Controller  
8 – 24 Channels RocketIO Multi-Gigabit Serial Transceivers  
(MGTs) capable of running 622 Mb/s – 6.5 Gb/s  
Full Clock and Data Recovery  
32-bit or 40-bit datapath support  
Optional 8B/10B, 64B/66B, or FPGA-based  
encode/decode  
Integrated FIFO/Elastic Buffer  
Support for Channel Bonding  
Embedded 32-bit CRC generation/checking  
Integrated Comma-detect or programmable A1/A2,  
A1A1/A2A2 detection  
Programmable pre-emphasis (AKA transmitter  
equalization)  
-
-
Optimized FPGA-based Coprocessor connection  
Automatic decode of PowerPC floating-point instructions  
— allows custom instructions (decode for up to eight  
instructions)  
Programmable receiver equalization  
Embedded support for:  
-
-
Out of Band (OOB) Signalling: Serial ATA  
Beaconing and Electrical Idle: PCI-Express™  
-
Extremely efficient microcontroller-style interfacing  
On-chip bypassable AC coupling for receiver  
Two or Four Tri-Mode (10/100/1000 Mb/s) Ethernet Media Access Control (MAC) Cores  
IEEE 802.3-2000 Compliant  
MII/GMII Interface or SGMII (when used with RocketIO  
Transceivers)  
Half- or Full-Duplex  
Supports Jumbo Frames  
1000Base-X PCS/PMA: When used with RocketIO  
MGT can provide complete 1000Base-X  
implementation on-chip  
Can Operate Independent of PowerPC processor  
Industry leading connectivity and networking IP cores  
include the electronics industry's first Advanced Switching  
product, leading-edge PCI Express, Serial RapidIO, Fibre  
Channel, and 10Gb Ethernet cores that include Virtex-4  
FPGA RocketIO multi-gigabit serial interfaces. The Xilinx  
SPI-4.2 IP core utilizes the Virtex-4 FPGA embedded  
ChipSync technology to implement dynamic phase align-  
ment for high-performance source-synchronous operation.  
Intellectual Property Cores  
Xilinx offers IP cores for commonly used complex functions  
including DSP, bus interfaces, processors, and processor  
peripherals. Using Xilinx LogiCORE™ products and cores  
from third party AllianceCORE participants, customers can  
shorten development time, reduce design risk, and obtain  
superior performance for their designs. Additionally, our  
CORE Generator™ system allows customers to implement  
IP cores into Virtex-4 FPGAs with predictable and repeat-  
able performance. It offers a simple user interface to gener-  
ate parameter-based cores optimized for our FPGAs.  
MicroBlaze™ processor 32-bit core provides the industry's  
fastest soft processing solution for building complex sys-  
tems for the networking, telecommunication, data communi-  
cation, embedded and consumer markets. The MicroBlaze  
processor features a RISC architecture with Harvard-style  
separate 32-bit instruction and data busses running at full  
speed to execute programs and access data from both  
on-chip and external memory. A standard set of peripherals  
are also CoreConnect™ enabled to offer MicroBlaze pro-  
cessor designers compatibility and reuse.  
The System Generator for DSP tool allows system archi-  
tects to quickly model and implement DSP functions using  
handcrafted IP, and features an interface to third-party sys-  
tem level DSP design tools. System Generator for DSP  
implements many of the high-performance DSP cores sup-  
porting Virtex-4 FPGAs including the Xilinx Forward Error  
Correction  
Solution  
with  
Interleaver/De-interleaver,  
All IP cores for Virtex-4 FPGAs are found on the Xilinx IP  
Center Internet portal presenting the latest intellectual prop-  
erty cores and reference designs via Smart Search for  
faster access.  
Reed-Solomon encoder/decoders, and Viterbi decoders.  
These are ideal for creating highly-flexible, concatenated  
codecs to support the communications market.  
DS112 (v3.1) August 30, 2010  
www.xilinx.com  
Product Specification  
6
R
Virtex-4 Family Overview  
Application Notes and Reference Designs  
Application notes and reference designs written specifically for the Virtex-4 family are available on the Xilinx web site at  
http://www.xilinx.com/support/documentation/virtex-4.htm.  
Virtex-4 Device and Package Combinations and Maximum I/Os  
Table 2: Virtex-4 Device and Package Combinations and Maximum Available I/Os  
SF363  
SFG363  
FF668  
FFG668  
FF672  
FFG672  
FF676  
FFG676  
FF1148  
FFG1148  
FF1152  
FFG1152  
FF1513  
FFG1513  
FF1517  
FFG1517  
Package(1,2)  
Size  
Device  
17 x 17  
27 x 27  
27 x 27  
27 x 27  
35 x 35  
35 x 35  
40 x 40  
40 x 40  
MGTs  
I/O  
240  
240  
MGTs  
I/O  
320  
448  
448  
448  
MGTs  
I/O  
MGTs  
N/A  
I/O  
MGTs  
I/O  
MGTs  
I/O  
MGTs  
I/O  
MGTs  
I/O  
XC4VLX15  
XC4VLX25  
XC4VLX40  
XC4VLX60  
XC4VLX80  
XC4VLX100  
XC4VLX160  
XC4VLX200  
XC4VSX25  
XC4VSX35  
XC4VSX55  
XC4VFX12  
XC4VFX20  
XC4VFX40  
XC4VFX60  
XC4VFX100  
XC4VFX140  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
320  
N/A  
N/A  
N/A  
N/A  
N/A  
640  
640  
768  
768  
768  
N/A  
N/A  
N/A  
960  
960  
960  
N/A  
N/A  
320  
448  
N/A  
640  
N/A  
240  
N/A  
320  
8
320  
352  
352  
12  
12  
12  
16  
20  
448  
576  
576  
20  
24  
768  
768  
Notes:  
1. All packages are also available in Pb-Free versions (SFG/FFG).  
2. Pinouts on all packages (except SF363/SFG363 and FF668/FFG668) are configured using the new, improved SparseChevron pin  
layout for superior signal integrity.  
Virtex-4 FPGA Ordering Information  
Virtex-4 FPGA ordering information shown in Figure 1 applies to all packages including Pb-Free.  
Example: XC4VLX25-10FFG668CS2  
Step Identification Version(1)  
Device Type  
Speed Grade  
Temperature Range:  
(-10, -11, -12(2))  
C = Commercial (TJ = 0°C to +85°C)  
I = Industrial(2) (TJ = 40°C to +100°C)  
Number of Pins  
Pb-Free  
Package Type  
Notes:  
1) The step identification version is optional and is not specified unless  
a particular device stepping is required. Refer to the Virtex-4 Data  
Sheet (DS302) for additional information on step ordering codes.  
2) -12 devices not available in Industrial grade.  
DS112_01_112806  
Figure 1: Virtex-4 FPGA Ordering Information  
DS112 (v3.1) August 30, 2010  
www.xilinx.com  
Product Specification  
7
R
Virtex-4 Family Overview  
Virtex-4 Documentation  
Complete and up-to-date documentation of the Virtex-4  
family of FPGAs is available on the Xilinx web site. In addi-  
tion to the most recent Virtex-4 Family Overview, the follow-  
ing files are also available for download:  
Virtex-4 FPGA Configuration Guide  
This all-encompassing configuration guide includes chap-  
ters on configuration interfaces (serial and SelectMAP), bit-  
stream encryption, Boundary-Scan and JTAG configuration,  
and reconfiguration techniques.  
Virtex-4 FPGA Data Sheet: DC and Switching  
Characteristics  
Virtex-4 FPGA Packaging and Pinout Specification  
This data sheet contains the DC and Switching Characteris-  
tic specifications for the Virtex-4 family.  
This specification includes the tables for device/package  
combinations and maximum I/Os, pin definitions, pinout  
tables, pinout diagrams, mechanical drawings, and thermal  
specifications.  
Virtex-4 FPGA User Guide  
This guide includes chapters on:  
Virtex-4 FPGA PCB Designer’s Guide  
Clocking Resources  
This guide describes PCB guidelines for the Virtex-4 family.  
It covers SelectIO signaling, RocketIO signaling, power dis-  
tribution systems, PCB breakout, and parts placement.  
Digital Clock Manager (DCM)  
Phase-Matched Clock Dividers (PMCD)  
Block RAM and FIFO memory  
Configurable Logic Blocks (CLBs)  
SelectIO Resources  
Virtex-4 RocketIO Multi-Gigabit Transceiver User Guide  
This guide describes the RocketIO Multi-Gigabit Transceiv-  
ers available in the Virtex-4 FX family.  
SelectIO Logic Resources  
Advanced SelectIO Logic Resources  
Virtex-4 FPGA Embedded Tri-Mode Ethernet MAC User  
Guide  
XtremeDSP for Virtex-4 FPGAs User Guide  
This guide describes the Embedded Tri-Mode Ethernet  
Media Access Controller available in the Virtex-4 FX family.  
This guide describes the DSP48 slice and includes refer-  
ence designs for using DSP48 math functions and various  
FIR filters.  
PowerPC 405 Processor Block Reference Guide  
This guide is updated to include the PowerPC 405 proces-  
sor block available in the Virtex-4 FX family.  
Revision History  
The following table shows the revision history for this document.  
Date  
Version  
1.0  
Revision  
08/02/04  
09/10/04  
12/08/04  
Initial Xilinx release. Printed Handbook version.  
Typographical edits.  
1.1  
1.2  
Removed System Monitor and ADC references.  
Edited Ethernet MAC section.  
03/26/05  
1.3  
Removed legacy CLB reference and typographical edits.  
Edited serial transceiver sections.  
In Table 2 added FFG Pb-Free packages.  
06/17/05  
02/10/06  
1.4  
1.5  
Added note to Table 2 for SparseChevron pinouts.  
Removed FCRAM-II support.  
Added note 3 to Table 1.  
Revised the CLB numbers for XC4VFX40 devices in Table 1.  
Added stepping to order information example in Figure 1.  
10/10/06  
01/23/07  
1.6  
2.0  
Changed maximum transceiver rate to 6.5 Gb/s.  
Removed FF1760 package from Table 2.  
Revision number jumped to 2.0 to correlate to data sheet (DS302) major revision.  
Table 1: Corrected typo: XC4VFX40 number of slices = 18,624.  
Table 2: Added column for FF676 package. Rewrote table footnotes.  
DS112 (v3.1) August 30, 2010  
www.xilinx.com  
Product Specification  
8
R
Virtex-4 Family Overview  
Date  
Version  
Revision  
03/12/07  
2.1  
Table 2: Corrected to remove FF676 package offerings in XC4VLX40, XC4VLX60,  
XC4VSX25, XC4VSX35, and XC4VFX12 devices.  
09/28/07  
08/30/10  
3.0  
3.1  
All Virtex-4 devices released to Production status. See DS302, Virtex-4 Data Sheet, for full  
particulars. No changes in this document from previous revision.  
See XCN09028, Product Discontinuation Notice Virtex-4 LX25 FPGA FF(G)676 Devices for  
detailed product revisions. In Table 2, removed XC4VLX25 devices in the FF676/FFG676  
package column.  
DS112 (v3.1) August 30, 2010  
www.xilinx.com  
Product Specification  
9
配单直通车
XC4VLX25-11FFG668CS2产品参数
型号:XC4VLX25-11FFG668CS2
是否Rohs认证: 符合
生命周期:Obsolete
IHS 制造商:XILINX INC
包装说明:BGA, BGA668,26X26,40
Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01
风险等级:5.8
最大时钟频率:1205 MHz
JESD-30 代码:S-PBGA-B668
JESD-609代码:e1
湿度敏感等级:4
输入次数:448
逻辑单元数量:24192
输出次数:448
端子数量:668
封装主体材料:PLASTIC/EPOXY
封装代码:BGA
封装等效代码:BGA668,26X26,40
封装形状:SQUARE
封装形式:GRID ARRAY
电源:1.2,1.2/3.3,2.5 V
可编程逻辑类型:FIELD PROGRAMMABLE GATE ARRAY
认证状态:Not Qualified
子类别:Field Programmable Gate Arrays
表面贴装:YES
技术:CMOS
端子面层:Tin/Silver/Copper (Sn95.5Ag4.0Cu0.5)
端子形式:BALL
端子节距:1 mm
端子位置:BOTTOM
Base Number Matches:1
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