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  • 北京元坤伟业科技有限公司

         该会员已使用本站17年以上

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  • HECC GROUP CO.,LIMITED

     该会员已使用本站17年以上
  • XC5VLX330-1FFG1760C 三甲现货
  • 数量830 
  • 厂家XILINX 
  • 封装BGA 
  • 批号24+ 
  • 渠道商,有出厂合格证,原包原盒正规报关!
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  • 深圳市意好科技有限公司

     该会员已使用本站15年以上
  • XC5VLX330-1FFG1760C 三甲现货
  • 数量780 
  • 厂家XILINX 
  • 封装BGA 
  • 批号24+ 
  • 原装认证,现货供应!实力商家
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  • 0755-88608316 QQ:2853107358QQ:2853107357
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  • 集好芯城

     该会员已使用本站13年以上
  • XC5VLX330-1FFG1760C 现货库存
  • 数量2115 
  • 厂家XILINX(赛灵思) 
  • 封装 
  • 批号22+ 
  • 原装原厂现货
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  • 深圳市毅创腾电子科技有限公司

     该会员已使用本站16年以上
  • XC5VLX330-1FFG1760C 现货库存
  • 数量8600 
  • 厂家XILINX代理主营品牌 
  • 封装BGA 
  • 批号22+ 
  • XILINX代理旗下专业分销!原装正品!
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  • 深圳市芯脉实业有限公司

     该会员已使用本站11年以上
  • XC5VLX330-1FFG1760C 现货库存
  • 数量5980 
  • 厂家XILINX 
  • 封装BGA 
  • 批号22+ 
  • 新到现货、一手货源、当天发货、bom配单
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  • 075584507705 QQ:2881512844
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  • 深圳市华康联电子科技有限公司

     该会员已使用本站10年以上
  • XC5VLX330-1FFG1760C 现货库存
  • 数量1500 
  • 厂家XILINX 
  • 封装BGA 
  • 批号20+ 
  • “华康联”专营军工、宇航级IC原装进口现货
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  • 18684627096 QQ:2284863921
  • XC5VLX330-1FFG1760C【特价现货】图
  • 齐创科技(上海北京青岛)有限公司

     该会员已使用本站14年以上
  • XC5VLX330-1FFG1760C【特价现货】 现货库存
  • 数量1600 
  • 厂家XILINX代理 
  • 封装BGA 
  • 批号24+热销 
  • 中国区代理全新原装正品进口
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  • 021-62153656 QQ:2394092314QQ:792179102
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  • 深圳市意好科技有限公司

     该会员已使用本站15年以上
  • XC5VLX330-1FFG1760C 现货库存
  • 数量3780 
  • 厂家XILINX 
  • 封装 
  • 批号24+ 
  • 代理商
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  • 深圳市毅创弘电子科技有限公司

     该会员已使用本站8年以上
  • XC5VLX330-1FFG1760C 现货库存
  • 数量68800 
  • 厂家Xilinx 
  • 封装1760-BBGAFCBGA 
  • 批号最新批次 
  • Xilinx专业分销商原装假一罚十
  • QQ:2881277219QQ:2881277219 复制
  • 0755-23600446 QQ:2881277219
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  • HECC GROUP CO.,LIMITED

     该会员已使用本站17年以上
  • XC5VLX330-1FFG1760C 现货库存
  • 数量1920 
  • 厂家XILINX 
  • 封装BGA 
  • 批号24+ 
  • 假一罚百,有原厂COC!深圳部分存货,北美、新加坡可发货
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  • 深圳市旺能芯科技有限公司

     该会员已使用本站4年以上
  • XC5VLX330-1FFG1760C 现货库存
  • 数量2600 
  • 厂家XILINX/赛灵思 
  • 封装BGA 
  • 批号21+ 
  • 深圳全新原装库存现货
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  • 13602549709 QQ:2881495751
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  • 深圳市恒意创鑫电子有限公司

     该会员已使用本站10年以上
  • XC5VLX330-1FFG1760C 现货库存
  • 数量233 
  • 厂家XILINX/赛灵思 
  • 封装BGA 
  • 批号21+ 
  • 全新原装现货,支持实单
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  • 深圳市宗天技术开发有限公司

     该会员已使用本站10年以上
  • XC5VLX330-1FFG1760C 现货库存
  • 数量800 
  • 厂家XILINX 
  • 封装BGA 
  • 批号21+ 
  • 宗天技术 原装现货/实单价优
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  • 深圳市华康联电子科技有限公司

     该会员已使用本站10年以上
  • XC5VLX330-1FFG1760C 热卖库存
  • 数量1500 
  • 厂家XILINX 
  • 封装BGA 
  • 批号20+ 
  • “华康联”专营军工、宇航级IC原装进口现货
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  • 18684627096 QQ:2284863921
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  • 深圳市华斯顿电子科技有限公司

     该会员已使用本站16年以上
  • XC5VLX330-1FFG1760C
  • 数量23762 
  • 厂家XILINX 
  • 封装1760FCBGA 
  • 批号2023+ 
  • 绝对原装正品全新进口深圳现货
  • QQ:1002316308QQ:1002316308 复制
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  • 深圳分公司0755-83777708“进口原装正品专供” QQ:1002316308QQ:515102657
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  • 深圳市和诚半导体有限公司

     该会员已使用本站11年以上
  • XC5VLX330-1FFG1760C
  • 数量5600 
  • 厂家XILINX 
  • 封装BGA 
  • 批号23+ 
  • 只做原装正品,深圳现货
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    QQ:1977615742QQ:1977615742 复制
  • 18929336553 QQ:2276916927QQ:1977615742
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  • 集好芯城

     该会员已使用本站13年以上
  • XC5VLX330-1FFG1760C
  • 数量18151 
  • 厂家XILINX/赛灵思 
  • 封装FCBGA1760 
  • 批号最新批次 
  • 原装原厂 现货现卖
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    QQ:3008092965QQ:3008092965 复制
  • 0755-83239307 QQ:3008092965QQ:3008092965
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  • 深圳市得捷芯城科技有限公司

     该会员已使用本站11年以上
  • XC5VLX330-1FFG1760C
  • 数量3270 
  • 厂家XILINX/赛灵思 
  • 封装NA/ 
  • 批号23+ 
  • 原装现货,当天可交货,原型号开票
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    QQ:3007947087QQ:3007947087 复制
  • 0755-82546830 QQ:3007977934QQ:3007947087
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  • 上海熠富电子科技有限公司

     该会员已使用本站15年以上
  • XC5VLX330-1FFG1760C
  • 数量9000 
  • 厂家XILINX 
  • 封装N/A 
  • 批号2024 
  • 上海原装现货库存,欢迎查询!
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    QQ:2300949663QQ:2300949663 复制
  • 15821228847 QQ:2719079875QQ:2300949663
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  • 深圳市毅创腾电子科技有限公司

     该会员已使用本站16年以上
  • XC5VLX330-1FFG1760C
  • 数量210 
  • 厂家XILINX 
  • 封装BGA钢面 
  • 批号22+ 
  • ★只做原装★正品现货★原盒原标★
  • QQ:2355507162QQ:2355507162 复制
    QQ:2355507165QQ:2355507165 复制
  • 86-755-83616256 QQ:2355507162QQ:2355507165
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  • 深圳市硅诺电子科技有限公司

     该会员已使用本站8年以上
  • XC5VLX330-1FFG1760C
  • 数量41977 
  • 厂家XILINX 
  • 封装BGA 
  • 批号17+ 
  • 原厂指定分销商,有意请来电或QQ洽谈
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  • 深圳市恒佳微电子有限公司

     该会员已使用本站12年以上
  • XC5VLX330-1FFG1760C
  • 数量
  • 厂家244 
  • 封装BGA 
  • 批号 
  • 正品原装 支持最低价
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  • 755-82533156 QQ:864187665QQ:1807086236
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  • 首天国际(深圳)科技有限公司

     该会员已使用本站16年以上
  • XC5VLX330-1FFG1760C
  • 数量1280 
  • 厂家XILINX 
  • 封装BGA 
  • 批号2024+ 
  • 百分百原装正品,现货库存
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    QQ:1318502189QQ:1318502189 复制
  • 0755-82807802 QQ:528164397QQ:1318502189
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  • 北京杰创宏达电子有限公司

     该会员已使用本站12年以上
  • XC5VLX330-1FFG1760C
  • 数量1600 
  • 厂家XILINX 
  • 封装FPGA 
  • 批号2024+ 
  • 授权代理商
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  • 010-61190909 QQ:2355548602QQ:2355548609
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  • 深圳市恒益昌科技有限公司

     该会员已使用本站6年以上
  • XC5VLX330-1FFG1760C
  • 数量450 
  • 厂家XILINX 
  • 封装BGA 
  • 批号23+ 
  • 原装正品长期供货
  • QQ:3336148967QQ:3336148967 复制
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  • 0755-82723761 QQ:3336148967QQ:974337758
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  • 深圳市羿芯诚电子有限公司

     该会员已使用本站7年以上
  • XC5VLX330-1FFG1760C
  • 数量5600 
  • 厂家XILINX/赛灵思 
  • 封装BGA 
  • 批号21+ 
  • 羿芯诚只做原装 原厂渠道 价格优势
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  • 深圳市积美福电子科技有限公司

     该会员已使用本站4年以上
  • XC5VLX330-1FFG1760C
  • 数量8000 
  • 厂家XILINX/赛灵思 
  • 封装FCBGA1760 
  • 批号21+ 
  • 自己原包装现货 实单?|原装?| 现货
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  • 深圳市恒嘉威智能科技有限公司

     该会员已使用本站7年以上
  • XC5VLX330-1FFG1760C
  • 数量15000 
  • 厂家XILINX 
  • 封装BGA1760 
  • 批号21+ 
  • 原装正品价格绝对优势
  • QQ:1036846627QQ:1036846627 复制
    QQ:2274045202QQ:2274045202 复制
  • -0755-23942980 QQ:1036846627QQ:2274045202
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  • 深圳市芯脉实业有限公司

     该会员已使用本站11年以上
  • XC5VLX330-1FFG1760C
  • 数量5980 
  • 厂家XILINX 
  • 封装BGA 
  • 批号22+ 
  • 新到现货、一手货源、当天发货、bom配单
  • QQ:2881512844QQ:2881512844 复制
  • 075584507705 QQ:2881512844
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  • 深圳市得捷芯城科技有限公司

     该会员已使用本站11年以上
  • XC5VLX330-1FFG1760C
  • 数量7181 
  • 厂家XILINX/赛灵思 
  • 封装FPBGA1760 
  • 批号23+ 
  • 原厂可订货,技术支持,直接渠道。可签保供合同
  • QQ:3007947087QQ:3007947087 复制
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  • 深圳市双微电子科技有限公司

     该会员已使用本站10年以上
  • XC5VLX330-1FFG1760C
  • 数量421 
  • 厂家XILINX 
  • 封装BGA 
  • 批号20+ 
  • 询货请加QQ 全新原装 现货库存
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  • 深圳市西昂特科技有限公司

     该会员已使用本站13年以上
  • XC5VLX330-1FFG1760C
  • 数量1000 
  • 厂家专注XILINX 
  • 封装BGA1760 
  • 批号2001+ 
  • 代理渠道,原装现货
  • QQ:2881291855QQ:2881291855 复制
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  • 0755-82524647 QQ:2881291855QQ:1158574719
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  • HECC GROUP CO.,LIMITED

     该会员已使用本站17年以上
  • XC5VLX330-1FFG1760C
  • 数量5700 
  • 厂家XILINX 
  • 封装BGA 
  • 批号24+ 
  • 原装假一赔十!可提供正规渠道证明!
  • QQ:3007947169QQ:3007947169 复制
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  • 755-83950895 QQ:3007947169QQ:3007947210
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  • HECC GROUP CO.,LIMITED

     该会员已使用本站17年以上
  • XC5VLX330-1FFG1760C
  • 数量5700 
  • 厂家XILINX 
  • 封装BGA 
  • 批号24+ 
  • 原装假一赔十!可提供正规渠道证明!
  • QQ:3003818780QQ:3003818780 复制
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  • 深圳市晶美隆科技有限公司

     该会员已使用本站14年以上
  • XC5VLX330-1FFG1760C
  • 数量2805 
  • 厂家xilinx 
  • 封装BGA 
  • 批号23+ 
  • 全新原装现货热卖
  • QQ:2885348317QQ:2885348317 复制
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  • 深圳市宏捷佳电子科技有限公司

     该会员已使用本站6年以上
  • XC5VLX330-1FFG1760C
  • 数量6500 
  • 厂家XILINX 
  • 封装BGA 
  • 批号24+ 
  • 全新原装★真实库存★含13点增值税票!
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  • 深圳市宏捷佳电子科技有限公司

     该会员已使用本站12年以上
  • XC5VLX330-1FFG1760C
  • 数量12300 
  • 厂家XILINX 
  • 封装BGA1760 
  • 批号24+ 
  • ★原装真实库存★13点税!
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  • 千层芯半导体(深圳)有限公司

     该会员已使用本站9年以上
  • XC5VLX330-1FFG1760C
  • 数量30617 
  • 厂家XILINX 
  • 封装BGA 
  • 批号2018+ 
  • 主打XILINX品牌价格绝对优势
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产品型号XC5VLX330-1FFG1760C的概述

XC5VLX330-1FFG1760C 芯片概述 XC5VLX330-1FFG1760C 是一款来自 Xilinx 公司的 FPGA(现场可编程门阵列)芯片,属于 Virtex-5 系列。该系列以其高性能而著称,适用于各种复杂的数字逻辑设计、信号处理、嵌入式系统及高带宽数据路由等场合。XC5VLX330-1FFG1760C 具备丰富的资源和灵活性,广泛应用于通信、消费电子、工业控制、网络设备等领域。 芯片详细参数 1. 性能参数 - 逻辑单元数量: 330,000 - 查找表 (LUT) 数量: 94,080 - I/O 引脚数: 576 - DSP 资源: 192 个 DSP 伪指令 - 多种工作频率: 高频率可达 550MHz - 内存资源: 16MB ### 2. 电源供应 - 工作电压: - 核心电压: 1.0V - I/O 电压: 2.5V 或 3.3V(可调) ...

产品型号XC5VLX330-1FFG1760C的Datasheet PDF文件预览

0
R
Virtex-5 Family Overview  
0
0
DS100 (v5.1) August 21, 2015  
Product Specification  
General Description  
Using the second generation ASMBL™ (Advanced Silicon Modular Block) column-based architecture, the Virtex-5 family contains five  
distinct platforms (sub-families), the most choice offered by any FPGA family. Each platform contains a different ratio of features to address  
the needs of a wide variety of advanced logic designs. In addition to the most advanced, high-performance logic fabric, Virtex-5 FPGAs  
contain many hard-IP system level blocks, including powerful 36-Kbit block RAM/FIFOs, second generation 25 x 18 DSP slices,  
SelectIO™ technology with built-in digitally-controlled impedance, ChipSync™ source-synchronous interface blocks, system monitor  
functionality, enhanced clock management tiles with integrated DCM (Digital Clock Managers) and phase-locked-loop (PLL) clock  
generators, and advanced configuration options. Additional platform dependant features include power-optimized high-speed serial  
transceiver blocks for enhanced serial connectivity, PCI Express® compliant integrated Endpoint blocks, tri-mode Ethernet MACs (Media  
Access Controllers), and high-performance PowerPC® 440 microprocessor embedded blocks. These features allow advanced logic  
designers to build the highest levels of performance and functionality into their FPGA-based systems. Built on a 65-nm state-of-the-art  
copper process technology, Virtex-5 FPGAs are a programmable alternative to custom ASIC technology. Most advanced system designs  
require the programmable strength of FPGAs. Virtex-5 FPGAs offer the best solution for addressing the needs of high-performance logic  
designers, high-performance DSP designers, and high-performance embedded systems designers with unprecedented logic, DSP,  
hard/soft microprocessor, and connectivity capabilities. The Virtex-5 LXT, SXT, TXT, and FXT platforms include advanced high-speed  
serial connectivity and link/transaction layer capability.  
Summary of Virtex-5 FPGA Features  
Five platforms LX, LXT, SXT, TXT, and FXT  
Advanced DSP48E slices  
Virtex-5 LX: High-performance general logic applications  
Virtex-5 LXT: High-performance logic with advanced serial  
connectivity  
25 x 18, two’s complement, multiplication  
Optional adder, subtracter, and accumulator  
Optional pipelining  
Optional bitwise logical functionality  
Dedicated cascade connections  
Virtex-5 SXT: High-performance signal processing  
applications with advanced serial connectivity  
Virtex-5 TXT: High-performance systems with double  
density advanced serial connectivity  
Virtex-5 FXT: High-performance embedded systems with  
advanced serial connectivity  
Flexible configuration options  
SPI and Parallel FLASH interface  
Multi-bitstream support with dedicated fallback  
reconfiguration logic  
Cross-platform compatibility  
Auto bus width detection capability  
LXT, SXT, and FXT devices are footprint compatible in the  
same package using adjustable voltage regulators  
System Monitoring capability on all devices  
On-chip/Off-chip thermal monitoring  
On-chip/Off-chip power supply monitoring  
JTAG access to all monitored quantities  
Most advanced, high-performance, optimal-utilization,  
FPGA fabric  
Real 6-input look-up table (LUT) technology  
Dual 5-LUT option  
Improved reduced-hop routing  
64-bit distributed RAM option  
SRL32/Dual SRL16 option  
Integrated Endpoint blocks for PCI Express Designs  
LXT, SXT, TXT, and FXT Platforms  
Compliant with the PCI Express Base Specification 1.1  
x1, x4, or x8 lane support per block  
Works in conjunction with RocketIO™ transceivers  
Tri-mode 10/100/1000 Mb/s Ethernet MACs  
Powerful clock management tile (CMT) clocking  
Digital Clock Manager (DCM) blocks for zero delay  
buffering, frequency synthesis, and clock phase shifting  
PLL blocks for input jitter filtering, zero delay buffering,  
frequency synthesis, and phase-matched clock division  
LXT, SXT, TXT, and FXT Platforms  
RocketIO transceivers can be used as PHY or connect to  
external PHY using many soft MII (Media Independent  
Interface) options  
RocketIO GTP transceivers 100 Mb/s to 3.75 Gb/s  
LXT and SXT Platforms  
RocketIO GTX transceivers 150 Mb/s to 6.5 Gb/s  
TXT and FXT Platforms  
PowerPC 440 Microprocessors  
36-Kbit block RAM/FIFOs  
True dual-port RAM blocks  
Enhanced optional programmable FIFO logic  
Programmable  
-
-
True dual-port widths up to x36  
Simple dual-port widths up to x72  
FXT Platform only  
RISC architecture  
Built-in optional error-correction circuitry  
Optionally program each block as two independent 18-Kbit  
blocks  
7-stage pipeline  
32-Kbyte instruction and data caches included  
Optimized processor interface structure (crossbar)  
High-performance parallel SelectIO technology  
65-nm copper CMOS process technology  
1.0V core voltage  
1.2 to 3.3V I/O Operation  
Source-synchronous interfacing using ChipSync™  
technology  
High signal-integrity flip-chip packaging available in standard  
or Pb-free package options  
Digitally-controlled impedance (DCI) active termination  
Flexible fine-grained I/O banking  
High-speed memory interface support  
© 2006–2015 Xilinx, Inc., Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, UltraScale, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Xilinx  
in the United States and other countries. PCI, PCIe, and PCI Express are trademarks of PCI-SIG and used under license. PowerPC is a trademark of IBM Corp. and is used under  
license. All other trademarks are the property of their respective owners.  
DS100 (v5.1) August 21, 2015  
www.xilinx.com  
Product Specification  
1
R
Virtex-5 Family Overview  
Table 1: Virtex-5 FPGA Family Members  
Configurable Logic Blocks (CLBs)  
Block RAM Blocks  
Max RocketIO  
Endpoint  
(6)  
PowerPC  
Processor  
Blocks  
Transceivers  
Total  
I/O  
Max  
DSP48E  
Blocks for Ethernet  
(4)  
Device  
Max  
CMTs  
User  
(2)  
(5)  
Array  
Virtex-5  
Slices  
Max  
(Kb)  
PCI  
Express  
MACs  
(3)  
(8)  
(7)  
Distributed  
RAM (Kb)  
18 Kb  
36 Kb  
Banks  
I/O  
(1)  
(Row x Col) Slices  
GTP  
GTX  
XC5VLX30  
XC5VLX50  
XC5VLX85  
XC5VLX110  
XC5VLX155  
XC5VLX220  
XC5VLX330  
XC5VLX20T  
XC5VLX30T  
XC5VLX50T  
XC5VLX85T  
80 x 30  
4,800  
7,200  
320  
480  
32  
48  
64  
96  
32  
48  
96  
1,152  
1,728  
3,456  
2
6
6
6
6
6
6
1
2
6
6
6
6
6
6
2
6
6
6
6
6
2
6
6
6
6
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
1
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
1
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
2
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
4
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
40  
13  
17  
17  
23  
23  
23  
33  
7
400  
560  
560  
800  
800  
800  
120 x 30  
120 x 54 12,960  
160 x 54 17,280  
160 x 76 24,320  
160 x 108 34,560  
240 x 108 51,840  
840  
48  
192  
256  
384  
384  
576  
52  
1,120  
1,640  
2,280  
3,420  
210  
64  
128 4,608  
192 6,912  
192 6,912  
288 10,368  
128  
128  
192  
24  
1,200  
172  
360  
480  
480  
680  
680  
680  
960  
360  
480  
640  
960  
680  
680  
360  
640  
680  
840  
960  
60 x 26  
80 x 30  
120 x 30  
3,120  
4,800  
7,200  
26  
36  
60  
936  
320  
32  
72  
1,296  
2,160  
1
4
8
12  
15  
15  
20  
20  
20  
27  
12  
15  
19  
27  
20  
20  
12  
19  
20  
24  
27  
480  
48  
120  
216  
296  
424  
424  
648  
168  
264  
488  
1
4
12  
120 x 54 12,960  
840  
48  
108 3,888  
148 5,328  
212 7,632  
212 7,632  
324 11,664  
1
4
12  
XC5VLX110T 160 x 54 17,280  
XC5VLX155T 160 x 76 24,320  
XC5VLX220T 160 x 108 34,560  
XC5VLX330T 240 x 108 51,840  
1,120  
1,640  
2,280  
3,420  
520  
64  
1
4
16  
128  
128  
192  
192  
288  
640  
1
4
16  
1
4
16  
1
4
24  
XC5VSX35T  
XC5VSX50T  
XC5VSX95T  
80 x 34  
5,440  
8,160  
84  
3,024  
1
4
8
120 x 34  
780  
132 4,752  
244 8,784  
1
4
12  
160 x 46 14,720  
1,520  
4,200  
1,500  
2,400  
380  
1
4
16  
XC5VSX240T 240 x 78 37,440  
XC5VTX150T 200 x 58 23,200  
XC5VTX240T 240 x 78 37,440  
1,056 1,032 516 18,576  
1
4
24  
80  
96  
456  
648  
136  
296  
456  
596  
912  
228 8,208  
324 11,664  
1
4
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
1
4
48  
XC5VFX30T  
XC5VFX70T  
80 x 38  
5,120  
64  
68  
2,448  
1
4
8
160 x 38 11,200  
820  
128  
256  
320  
384  
148 5,328  
228 8,208  
298 10,728  
456 16,416  
1
3
4
16  
XC5VFX100T 160 x 56 16,000  
XC5VFX130T 200 x 56 20,480  
XC5VFX200T 240 x 68 30,720  
1,240  
1,580  
2,280  
2
3
4
16  
2
3
6
20  
2
4
8
24  
Notes:  
1. Virtex-5 FPGA slices are organized differently from previous generations. Each Virtex-5 FPGA slice contains four LUTs and four flip-flops (previously  
it was two LUTs and two flip-flops.)  
2. Each DSP48E slice contains a 25 x 18 multiplier, an adder, and an accumulator.  
3. Block RAMs are fundamentally 36 Kbits in size. Each block can also be used as two independent 18-Kbit blocks.  
4. Each Clock Management Tile (CMT) contains two DCMs and one PLL.  
5. This table lists separate Ethernet MACs per device.  
6. RocketIO GTP transceivers are designed to run from 100 Mb/s to 3.75 Gb/s. RocketIO GTX transceivers are designed to run from 150 Mb/s to  
6.5 Gb/s.  
7. This number does not include RocketIO transceivers.  
8. Includes configuration Bank 0.  
2
www.xilinx.com  
DS100 (v5.1) August 21, 2015  
Product Specification  
R
Virtex-5 Family Overview  
Virtex-5 FPGA Logic  
550 MHz Integrated Block Memory  
On average, one to two speed grade improvement over  
Virtex-4 devices  
Up to 16.4 Mbits of integrated block memory  
36-Kbit blocks with optional dual 18-Kbit mode  
True dual-port RAM cells  
Independent port width selection (x1 to x72)  
Cascadable 32-bit variable shift registers or 64-bit  
distributed memory capability  
Superior routing architecture with enhanced diagonal  
routing supports block-to-block connectivity with  
minimal hops  
Up to x36 total per port for true dual port operation  
Up to x72 total per port for simple dual port operation  
(one Read port and one Write port)  
Memory bits plus parity/sideband memory support for  
x9, x18, x36, and x72 widths  
Configurations from 32K x 1 to 512 x 72  
(8K x 4 to 512 x 72 for FIFO operation)  
Up to 330,000 logic cells including:  
Up to 207,360 internal fabric flip-flops with clock enable  
(XC5VLX330)  
Up to 207,360 real 6-input look-up tables (LUTs) with  
greater than 13 million total LUT bits  
Two outputs for dual 5-LUT mode gives enhanced  
utilization  
Multirate FIFO support logic  
Full and Empty flag with fully programmable Almost Full  
and Almost Empty flags  
Logic expanding multiplexers and I/O registers  
Synchronous FIFO support without Flag uncertainty  
Optional pipeline stages for higher performance  
Byte-write capability  
550 MHz Clock Technology  
Up to six Clock Management Tiles (CMTs)  
Dedicated cascade routing to form 64K x 1 memory  
without using FPGA routing  
Integrated optional ECC for high-reliability memory  
requirements  
Special reduced-power design for 18 Kbit (and below)  
operation  
Each CMT contains two DCMs and one PLL—up to  
eighteen total clock generators  
Flexible DCM-to-PLL or PLL-to-DCM cascade  
Precision clock deskew and phase shift  
Flexible frequency synthesis  
Multiple operating modes to ease performance trade-off  
decisions  
Improved maximum input/output frequency  
Fine-grained phase shifting resolution  
Input jitter filtering  
Low-power operation  
Wide phase shift range  
550 MHz DSP48E Slices  
25 x 18 two’s complement multiplication  
Optional pipeline stages for enhanced performance  
Optional 48-bit accumulator for multiply accumulate  
(MACC) operation with optional accumulator cascade  
to 96-bits  
Differential clock tree structure for optimized low-jitter  
clocking and precise duty cycle  
32 global clock networks  
Regional, I/O, and local clocks in addition to global  
clocks  
Integrated adder for complex-multiply or multiply-add  
operation  
Optional bitwise logical operation modes  
Independent C registers per slice  
SelectIO Technology  
Up to 1,200 user I/Os  
Fully cascadable in a DSP column without external  
routing resources  
Wide selection of I/O standards from 1.2V to 3.3V  
Extremely high-performance  
ChipSync Source-Synchronous  
Interfacing Logic  
Up to 800 Mb/s HSTL and SSTL  
(on all single-ended I/Os)  
Up to 1.25 Gb/s LVDS (on all differential I/O pairs)  
Works in conjunction with SelectIO technology to  
simplify source-synchronous interfaces  
True differential termination on-chip  
Same edge capture at input and output I/Os  
Extensive memory interface support  
Per-bit deskew capability built into all I/O blocks  
(variable delay line on all inputs and outputs)  
Dedicated I/O and regional clocking resources (pins  
and trees)  
Built-in data serializer/deserializer logic with  
corresponding clock divider support in all I/O  
Networking/telecommunication interfaces up to  
1.25 Gb/s per I/O  
DS100 (v5.1) August 21, 2015  
www.xilinx.com  
Product Specification  
3
R
Virtex-5 Family Overview  
Digitally Controlled Impedance (DCI)  
Active I/O Termination  
System Monitor  
On-Chip temperature measurement ( 4°C)  
On-Chip power supply measurement ( 1%)  
Easy to use, self-contained  
Optional series or parallel termination  
Temperature and voltage compensation  
Makes board layout much easier  
No design required for basic operation  
Autonomous monitoring of all on-chip sensors  
User programmable alarm thresholds for on-chip  
sensors  
Reduces resistors  
Places termination in the ideal location, at the signal  
source or destination  
User accessible 10-bit 200kSPS ADC  
Configuration  
Automatic calibration of offset and gain error  
DNL = 0.9 LSBs maximum  
Support for platform Flash, standard SPI Flash, or  
standard parallel NOR Flash configuration  
Bitstream support with dedicated fallback  
reconfiguration logic  
256-bit AES bitstream decryption provides intellectual  
property security and prevents design copying  
Improved bitstream error detection/correction capability  
Auto bus width detection capability  
Up to 17 external analog input channels supported  
0V to 1V input range  
Monitor external sensors e.g., voltage, temperature  
General purpose analog inputs  
Full access from fabric or JTAG TAP to System Monitor  
Fully operational prior to FPGA configuration and  
during device power down (access via JTAG TAP only)  
Partial Reconfiguration via ICAP port  
65-nm Copper CMOS Process  
Advanced Flip-Chip Packaging  
1.0V Core Voltage  
Pre-engineered packaging technology for proven  
superior signal integrity  
12-layer metal provides maximum routing capability  
and accommodates hard-IP immersion  
Triple-oxide technology for proven reduced static power  
consumption  
Minimized inductive loops from signal to return  
Optimal signal-to-PWR/GND ratios  
Reduces SSO induced noise by up to 7x  
Pb-Free and standard packages  
System Blocks Specific to the LXT, SXT, TXT, and FXT Devices  
Integrated Endpoint Block for PCI Express  
Compliance  
Tri-Mode Ethernet Media Access Controller  
Designed to the IEEE 802.3-2002 specification  
Operates at 10, 100, and 1,000 Mb/s  
Supports tri-mode auto-negotiation  
Receive address filter (5 address entries)  
Fully monolithic 1000Base-X solution with RocketIO  
GTP transceivers  
Works in conjunction with RocketIO GTP transceivers  
(LXT and SXT) and GTX transceivers (TXT and FXT)  
to deliver full PCI Express Endpoint functionality with  
minimal FPGA logic utilization.  
Compliant with the PCI Express Base Specification 1.1  
PCI Express Endpoint block or Legacy PCI Express  
Endpoint block  
Supports multiple external PHY connections (RGMII,  
GMII, etc.) interfaces through soft logic and SelectIO  
resources  
x8, x4, or x1 lane width  
Power management support  
Block RAMs used for buffering  
Fully buffered transmit and receive  
Management interface to access PCI Express  
configuration space and internal configuration  
Supports the full range of maximum payload sizes  
Up to 6 x 32 bit or 3 x 64 bit BARs (or a combination of  
32 bit and 64 bit)  
Supports connection to external PHY device through  
SGMII using soft logic and RocketIO GTP transceivers  
Receive and transmit statistics available through  
separate interface  
Separate host and client interfaces  
Support for jumbo frames  
Support for VLAN  
Flexible, user-configurable host interface  
Supports IEEE 802.3ah-2004 unidirectional mode  
4
www.xilinx.com  
DS100 (v5.1) August 21, 2015  
Product Specification  
R
Virtex-5 Family Overview  
RocketIO GTP Transceivers (LXT/SXT only)  
PowerPC 440 RISC Cores (FXT only)  
Full-duplex serial transceiver capable of 100 Mb/s to  
3.75 Gb/s baud rates  
Embedded PowerPC 440 (PPC440) cores  
Up to 550 MHz operation  
Greater than 1000 DMIPS per core  
Seven-stage pipeline  
Multiple instructions per cycle  
Out-of-order execution  
32 Kbyte, 64-way set associative level 1 instruction  
cache  
8B/10B, user-defined FPGA logic, or no encoding  
options  
Channel bonding support  
CRC generation and checking  
Programmable pre-emphasis or pre-equalization for  
the transmitter  
32 Kbyte, 64-way set associative level 1 data cache  
Book E compliant  
Programmable termination and voltage swing  
Programmable equalization for the receiver  
Receiver signal detect and loss of signal indicator  
Integrated crossbar for enhanced system performance  
128-bit Processor Local Buses (PLBs)  
Integrated scatter/gather DMA controllers  
Dedicated interface for connection to DDR2 memory  
controller  
User dynamic reconfiguration using secondary  
configuration bus  
Auto-synchronization for non-integer PLB-to-CPU clock  
ratios  
Out of Band (OOB) support for Serial ATA (SATA)  
Electrical idle, beaconing, receiver detection, and PCI  
Express and SATA spread-spectrum clocking support  
Auxiliary Processor Unit (APU) Interface and Controller  
Direct connection from PPC440 embedded block to  
FPGA fabric-based coprocessors  
Less than 100 mW typical power consumption  
Built-in PRBS Generators and Checkers  
128-bit wide pipelined APU Load/Store  
Support of autonomous instructions: no pipeline stalls  
Programmable decode for custom instructions  
RocketIO GTX Transceivers (TXT/FXT only)  
Full-duplex serial transceiver capable of 150 Mb/s to  
6.5 Gb/s baud rates  
8B/10B encoding and programmable gearbox to  
support 64B/66B and 64B/67B encoding, user-defined  
FPGA logic, or no encoding options  
Channel bonding support  
CRC generation and checking  
Programmable pre-emphasis or pre-equalization for  
the transmitter  
Programmable termination and voltage swing  
Programmable continuous time equalization for the  
receiver  
Programmable decision feedback equalization for the  
receiver  
Receiver signal detect and loss of signal indicator  
User dynamic reconfiguration using secondary  
configuration bus  
OOB support (SATA)  
Electrical idle, beaconing, receiver detection, and  
PCI Express spread-spectrum clocking support  
Low-power operation at all line rates  
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Virtex-5 Family Overview  
Architectural Description  
Virtex-5 FPGA Array Overview  
Virtex-5 devices are user-programmable gate arrays with various configurable elements and embedded cores optimized for  
high-density and high-performance system designs. Virtex-5 devices implement the following functionality:  
I/O blocks provide the interface between package pins  
and the internal configurable logic. Most popular and  
leading-edge I/O standards are supported by  
programmable I/O blocks (IOBs). The IOBs can be  
connected to very flexible ChipSync logic for enhanced  
source-synchronous interfacing. Source-synchronous  
optimizations include per-bit deskew (on both input and  
output signals), data serializers/deserializers, clock  
dividers, and dedicated I/O and local clocking  
resources.  
Additionally, LXT, SXT, TXT, and FXT devices also contain:  
Integrated Endpoint blocks for PCI Express designs  
providing x1, x4, or x8 PCI Express Endpoint  
functionality. When used in conjunction with RocketIO  
transceivers, a complete PCI Express Endpoint can be  
implemented with minimal FPGA logic utilization.  
10/100/1000 Mb/s Ethernet media-access control  
blocks offer Ethernet capability.  
LXT and SXT devices contain:  
Configurable Logic Blocks (CLBs), the basic logic  
elements for Xilinx® FPGAs, provide combinatorial and  
synchronous logic as well as distributed memory and  
SRL32 shift register capability. Virtex-5 FPGA CLBs  
are based on real 6-input look-up table technology and  
provide superior capabilities and performance  
compared to previous generations of programmable  
logic.  
RocketIO GTP transceivers capable of running up to  
3.75 Gb/s. Each GTP transceiver supports full-duplex,  
clock-and-data recovery.  
TXT and FXT devices contain:  
GTX transceivers capable of running up to 6.5 Gb/s.  
Each GTX transceiver supports full-duplex, clock-and-  
data recovery.  
Block RAM modules provide flexible 36 Kbit true dual-  
port RAM that are cascadable to form larger memory  
blocks. In addition, Virtex-5 FPGA block RAMs contain  
optional programmable FIFO logic for increased device  
utilization. Each block RAM can also be configured as  
two independent 18 Kbit true dual-port RAM blocks,  
providing memory granularity for designs needing  
smaller RAM blocks.  
FXT devices contain:  
Embedded IBM PowerPC 440 RISC CPUs. Each  
PowerPC 440 CPU is capable of running up to  
550 MHz. Each PowerPC 440 CPU also has an APU  
(Auxiliary Processor Unit) interface that supports  
hardware acceleration, and an integrated cross-bar for  
high data throughput.  
Cascadable embedded DSP48E slices with 25 x 18  
two’s complement multipliers and 48-bit  
adder/subtracter/accumulator provide massively  
parallel DSP algorithm support. In addition, each  
DSP48E slice can be used to perform bitwise logical  
functions.  
The general routing matrix (GRM) provides an array of  
routing switches between each internal component. Each  
programmable element is tied to a switch matrix, allowing  
multiple connections to the general routing matrix. The  
overall programmable interconnection is hierarchical and  
designed to support high-speed designs. In Virtex-5  
devices, the routing connections are optimized to support  
CLB interconnection in the fewest number of “hops.”  
Reducing hops greatly increases post place-and-route  
(PAR) design performance.  
Clock Management Tile (CMT) blocks provide the most  
flexible, highest-performance clocking for FPGAs. Each  
CMT contains two Digital Clock Manager (DCM) blocks  
(self-calibrating, fully digital), and one PLL block (self-  
calibrating, analog) for clock distribution delay  
compensation, clock multiplication/division, coarse-  
/fine-grained clock phase shifting, and input clock jitter  
filtering.  
All programmable elements, including the routing  
resources, are controlled by values stored in static storage  
elements. These values are loaded into the FPGA during  
configuration and can be reloaded to change the functions  
of the programmable elements.  
6
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Virtex-5 Family Overview  
Virtex-5 FPGA Features  
This section briefly describes the features of the Virtex-5 family of FPGAs.  
Input/Output Blocks (SelectIO)  
IOBs are programmable and can be categorized as follows:  
Data serializer/deserializer capability is added to every I/O  
to support source-synchronous interfaces. A serial-to-  
parallel converter with associated clock divider is included  
in the input path, and a parallel-to-serial converter in the  
output path.  
Programmable single-ended or differential (LVDS)  
operation  
Input block with an optional single data rate (SDR) or  
double data rate (DDR) register  
Output block with an optional SDR or DDR register  
Bidirectional block  
Per-bit deskew circuitry  
Dedicated I/O and regional clocking resources  
Built-in data serializer/deserializer  
An in-depth guide to the Virtex-5 FPGA IOB is found in the  
Virtex-5 FPGA Tri-Mode Ethernet MAC User Guide.  
Configurable Logic Blocks (CLBs)  
A Virtex-5 FPGA CLB resource is made up of two slices.  
Each slice is equivalent and contains:  
The IOB registers are either edge-triggered D-type flip-flops  
or level-sensitive latches.  
Four function generators  
Four storage elements  
Arithmetic logic gates  
Large multiplexers  
IOBs support the following single-ended standards:  
LVTTL  
LVCMOS (3.3V, 2.5V, 1.8V, 1.5V, and 1.2V)  
PCI (33 and 66 MHz)  
PCI-X  
GTL and GTLP  
HSTL 1.5V and 1.8V (Class I, II, III, and IV)  
HSTL 1.2V (Class 1)  
Fast carry look-ahead chain  
The function generators are configurable as 6-input LUTs or  
dual-output 5-input LUTs. SLICEMs in some CLBs can be  
configured to operate as 32-bit shift registers (or 16-bit x 2  
shift registers) or as 64-bit distributed RAM. In addition, the  
four storage elements can be configured as either  
SSTL 1.8V and 2.5V (Class I and II)  
edge-triggered D-type flip-flops or level sensitive latches.  
Each CLB has internal fast interconnect and connects to a  
switch matrix to access general routing resources.  
The Digitally Controlled Impedance (DCI) I/O feature can be  
configured to provide on-chip termination for each  
single-ended I/O standard and some differential I/O  
standards.  
The Virtex-5 FPGA CLBs are further discussed in the  
Virtex-5 FPGA User Guide.  
The IOB elements also support the following differential  
signaling I/O standards:  
Block RAM  
LVDS and Extended LVDS (2.5V only)  
BLVDS (Bus LVDS)  
ULVDS  
The 36 Kbit true dual-port RAM block resources are  
programmable from 32K x 1 to 512 x 72, in various depth  
and width configurations. In addition, each 36-Kbit block  
can also be configured to operate as two, independent 18-  
Kbit dual-port RAM blocks.  
Hypertransport™  
Differential HSTL 1.5V and 1.8V (Class I and II)  
Differential SSTL 1.8V and 2.5V (Class I and II)  
RSDS (2.5V point-to-point)  
Each port is totally synchronous and independent, offering  
three “read-during-write” modes. Block RAM is cascadable  
to implement large embedded storage blocks. Additionally,  
back-end pipeline registers, clock control circuitry, built-in  
FIFO support, ECC, and byte write enable features are also  
provided as options.  
Two adjacent pads are used for each differential pair. Two or  
four IOB blocks connect to one switch matrix to access the  
routing resources.  
Per-bit deskew circuitry allows for programmable signal  
delay internal to the FPGA. Per-bit deskew flexibly provides  
fine-grained increments of delay to carefully produce a  
range of signal delays. This is especially useful for  
synchronizing signal edges in source-synchronous  
interfaces.  
The block RAM feature in Virtex-5 devices is further  
discussed in the Virtex-5 FPGA User Guide.  
General purpose I/O in select locations (eight per bank) are  
designed to be “regional clock capable” I/O by adding  
special hardware connections for I/O in the same locality.  
These regional clock inputs are distributed within a limited  
region to minimize clock skew between IOBs. Regional I/O  
clocking supplements the global clocking resources.  
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Virtex-5 Family Overview  
Global Clocking  
Configuration  
The CMTs and global-clock multiplexer buffers provide a  
complete solution for designing high-speed clock networks.  
Virtex-5 devices are configured by loading the bitstream into  
internal configuration memory using one of the following  
modes:  
Each CMT contains two DCMs and one PLL. The DCMs  
and PLLs can be used independently or extensively  
cascaded. Up to six CMT blocks are available, providing up  
to eighteen total clock generator elements.  
Slave-serial mode  
Master-serial mode  
Slave SelectMAP mode  
Master SelectMAP mode  
Boundary-Scan mode (IEEE-1532 and -1149)  
SPI mode (Serial Peripheral Interface standard Flash)  
BPI-up/BPI-down modes (Byte-wide Peripheral  
interface standard x8 or x16 NOR Flash)  
Each DCM provides familiar clock generation capability. To  
generate deskewed internal or external clocks, each DCM  
can be used to eliminate clock distribution delay. The DCM  
also provides 90°, 180°, and 270° phase-shifted versions of  
the output clocks. Fine-grained phase shifting offers higher-  
resolution phase adjustment with fraction of the clock period  
increments. Flexible frequency synthesis provides a clock  
output frequency equal to a fractional or integer multiple of  
the input clock frequency.  
In addition, Virtex-5 devices also support the following  
configuration options:  
256-bit AES bitstream decryption for IP protection  
Multi-bitstream management (MBM) for cold/warm boot  
support  
To augment the DCM capability, Virtex-5 FPGA CMTs also  
contain a PLL. This block provides reference clock jitter  
filtering and further frequency synthesis options.  
Parallel configuration bus width auto-detection  
Parallel daisy chain  
Configuration CRC and ECC support for the most  
robust, flexible device integrity checking  
Virtex-5 devices have 32 global-clock MUX buffers. The  
clock tree is designed to be differential. Differential clocking  
helps reduce jitter and duty cycle distortion.  
Virtex-5 device configuration is further discussed in the  
Virtex-5 FPGA Configuration Guide.  
DSP48E Slices  
DSP48E slice resources contain a 25 x 18 two’s  
complement multiplier and a 48-bit  
System Monitor  
FPGAs are an important building block in high  
availability/reliability infrastructure. Therefore, there is need  
to better monitor the on-chip physical environment of the  
FPGA and its immediate surroundings within the system.  
For the first time, the Virtex-5 family System Monitor  
facilitates easier monitoring of the FPGA and its external  
environment. Every member of the Virtex-5 family contains  
a System Monitor block. The System Monitor is built around  
a 10-bit 200kSPS ADC (Analog-to-Digital Converter). This  
ADC is used to digitize a number of on-chip sensors to  
provide information about the physical environment within  
the FPGA. On-chip sensors include a temperature sensor  
and power supply sensors. Access to the external  
environment is provided via a number of external analog  
input channels. These analog inputs are general purpose  
and can be used to digitize a wide variety of voltage signal  
types. Support for unipolar, bipolar, and true differential  
input schemes is provided. There is full access to the on-  
chip sensors and external channels via the JTAG TAP,  
allowing the existing JTAG infrastructure on the PC board to  
be used for analog test and advanced diagnostics during  
development or after deployment in the field. The System  
Monitor is fully operational after power up and before  
configuration of the FPGA. System Monitor does not require  
an explicit instantiation in a design to gain access to its  
basic functionality. This allows the System Monitor to be  
used even at a late stage in the design cycle.  
adder/subtacter/accumulator. Each DSP48E slice also  
contains extensive cascade capability to efficiently  
implement high-speed DSP algorithms.  
The Virtex-5 FPGA DSP48E slice features are further  
discussed in Virtex-5 FPGA XtremeDSP Design  
Considerations.  
Routing Resources  
All components in Virtex-5 devices use the same  
interconnect scheme and the same access to the global  
routing matrix. In addition, the CLB-to-CLB routing is  
designed to offer a complete set of connectivity in as few  
hops as possible. Timing models are shared, greatly  
improving the predictability of the performance for high-  
speed designs.  
Boundary Scan  
Boundary-Scan instructions and associated data registers  
support a standard methodology for accessing and  
configuring Virtex-5 devices, complying with IEEE  
standards 1149.1 and 1532.  
The Virtex-5 FPGA System Monitor is further discussed in  
theVirtex-5 FPGA System Monitor User Guide.  
8
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Virtex-5 Family Overview  
Virtex-5 LXT, SXT, TXT, and FXT Platform Features  
This section briefly describes blocks available only in LXT, SXT, TXT, and FXT devices.  
Tri-Mode (10/100/1000 Mb/s) Ethernet MACs  
Integrated Endpoint Blocks for PCI Express  
Virtex-5 LXT, SXT, TXT, and FXT devices contain up to eight  
embedded Ethernet MACs, two per Ethernet MAC block.  
The blocks have the following characteristics:  
Virtex-5 LXT, SXT, TXT, and FXT devices contain up to four  
integrated Endpoint blocks. These blocks implement  
Transaction Layer, Data Link Layer, and Physical Layer  
functions to provide complete PCI Express Endpoint  
functionality with minimal FPGA logic utilization. The blocks  
have the following characteristics:  
Designed to the IEEE 802.3-2002 specification  
UNH-compliance tested  
RGMII/GMII Interface with SelectIO or SGMII interface  
when used with RocketIO transceivers  
Half or full duplex  
Compliant with the PCI Express Base Specification 1.1  
Works in conjunction with RocketIO transceivers to  
provide complete endpoint functionality  
Supports Jumbo frames  
1000 Base-X PCS/PMA: When used with RocketIO  
GTP transceiver, can provide complete 1000 Base-X  
implementation on-chip  
1, 4, or 8 lane support per block  
DCR-bus connection to microprocessors  
Virtex-5 LXT and SXT Platform Features  
This section briefly describes blocks available only in LXT and SXT devices.  
RocketIO GTP Transceivers  
4 - 24 channel RocketIO GTP transceivers capable of  
running 100 Mb/s to 3.75 Gb/s.  
Programmable transmitter output swing  
Programmable receiver equalization  
Programmable receiver termination  
Embedded support for:  
Full clock and data recovery  
8/16-bit or 10/20-bit datapath support  
Optional 8B/10B or FPGA-based encode/decode  
Integrated FIFO/elastic buffer  
Channel bonding and clock correction support  
Embedded 32-bit CRC generation/checking  
Integrated comma-detect or A1/A2 detection  
Programmable pre-emphasis (AKA transmitter  
equalization)  
Out of Band (OOB) signalling: Serial ATA  
Beaconing, electrical idle, and PCI Express receiver  
detection  
Built-in PRBS generator/checker  
Virtex-5 FPGA RocketIO GTP transceivers are further  
discussed in the Virtex-5 FPGA RocketIO GTP Transceiver  
User Guide.  
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Virtex-5 Family Overview  
Virtex-5 TXT and FXT Platform Features  
This section describes blocks only available in TXT and FXT devices.  
RocketIO GTX Serial Transceivers  
(TXT/FXT)  
8 - 48 channels RocketIO serial transceivers capable of  
running 150 Mb/s to 6.5 Gb/s  
One or Two PowerPC 440 Processor Cores  
(FXT only)  
Superscalar RISC architecture  
32-bit Book E compliant  
7-Stage execution pipeline  
Full Clock and Data Recovery  
Multiple instructions per cycle  
Out-of-order execution  
Integrated 32 KB Level 1 Instruction Cache and 32KB  
Level 1 Data Cache (64-way set associative)  
CoreConnect™ Bus Architecture  
Cross-bar connection for optimized processor  
bandwidth  
8/16/32-bit or 10/20/40-bit datapath support  
Optional 8B/10B encoding, gearbox for programmable  
64B/66B or 64B/67B encoding, or FPGA-based  
encode/decode  
Integrated FIFO/Elastic Buffer  
Channel bonding and clock correction support  
Dual embedded 32-bit CRC generation/checking  
Integrated programmable character detection  
Programmable de-emphasis (AKA transmitter  
equalization)  
PLB Synchronization Logic (Enables non-integer CPU-  
to-PLB clock ratios)  
Auxiliary Processor Unit (APU) interface with an  
integrated APU controller  
Programmable transmitter output swings  
Programmable receiver equalization  
Programmable receiver termination  
Embedded support for:  
Optimized FPGA-based Coprocessor connection  
-
Automatic decode of PowerPC floating-point  
instructions  
Allows custom instructions  
Extremely efficient microcontroller-style interfacing  
Serial ATA: Out of Band (OOB) signalling  
PCI Express: Beaconing, electrical idle, and receiver  
detection  
The PowerPC 440 processors are further discussed in the  
Embedded Processor Block in Virtex-5 FPGAs Reference  
Guide.  
Built-in PRBS generator/checker  
Virtex-5 FPGA RocketIO GTX transceivers are further  
discussed in the Virtex-5 FPGA RocketIO GTX Transceiver  
User Guide.  
Intellectual Property Cores  
Xilinx offers IP cores for commonly used complex functions  
including DSP, bus interfaces, processors, and processor  
peripherals. Using Xilinx LogiCORE™ products and cores from  
third party AllianceCORE participants, customers can shorten  
development time, reduce design risk, and obtain superior  
performance for their designs. Additionally, the CORE Generator™  
system allows customers to implement IP cores into Virtex-5  
FPGAs with predictable and repeatable performance. It offers a  
simple user interface to generate parameter-based cores  
optimized for our FPGAs.  
Xilinx also provides PCI cores for advanced system-synchronous  
operation.  
The MicroBlaze™ 32-bit processor core provides the industry's  
fastest soft processing solution for building complex systems for  
the networking, telecommunication, data communication,  
embedded, and consumer markets. The MicroBlaze processor  
features a RISC architecture with Harvard-style separate 32-bit  
instruction and data buses running at full speed to execute  
programs and access data from both on-chip and external  
memory. A standard set of peripherals are also CoreConnect™  
enabled to offer MicroBlaze designers compatibility and reuse.  
The System Generator for DSP tool allows system architects to  
quickly model and implement DSP functions using handcrafted IP  
and features an interface to third-party system level DSP design  
tools. System Generator for DSP implements many of the high-  
performance DSP cores supporting Virtex-5 FPGAs including the  
Xilinx Forward Error Correction Solution with Interleaver/  
De-interleaver, Reed-Solomon encoder/decoders, and Viterbi  
decoders. These are ideal for creating highly-flexible,  
All IP cores for Virtex-5 FPGAs are found on the Xilinx IP Center  
Internet portal presenting the latest intellectual property cores and  
reference designs using Smart Search for faster access.  
Virtex-5 FPGA LogiCORE Endpoint Block Plus Wrapper  
for PCI Express  
This is the recommended wrapper to configure the integrated  
Endpoint block for PCI Express delivered through the CORE  
Generator system. It provides many ease-of-use features and  
optimal configuration for Endpoint application simplifying the  
design process and reducing the time-to-market. Access to the  
core, including bitstream generation capability can be obtained  
through registration at no extra charge.  
concatenated codecs to support the communications market.  
Using Virtex-5 FPGA RocketIO transceivers, industry leading  
connectivity and networking IP cores include leading-edge PCI  
Express, Serial RapidIO, Fibre Channel, and 10 Gb Ethernet  
cores can be implemented. The Xilinx SPI-4.2 IP core utilizes the  
Virtex-5 FPGA ChipSync technology to implement dynamic phase  
alignment for high-performance source-synchronous operation.  
10  
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Virtex-5 Family Overview  
Virtex-5 Device and Package Combinations and Maximum I/Os  
Table 2: Virtex-5 Device and Package Combinations and Maximum Available I/Os  
FF323  
Package FFG323  
FFV323  
FF324  
FFG324  
FFV324  
FF676  
FFG676  
FFV676  
FF1153  
FF1760  
FFG1760  
FFV1760(2)  
FF665  
FFG665  
FFV665  
FF1136  
FFG1136  
FFV1136(3)  
FF1738  
FF1156  
FFG1156  
FF1759  
FFG1759  
FFG1153  
FFG1738  
FFV1153  
FFV1738(4)  
(1)  
Size (mm)  
Device  
19 x 19  
19 x 19  
27 x 27  
35 x 35  
42.5 x 42.5  
27 x 27  
35 x 35  
35 x 35  
42.5 x 42.5  
42.5 x 42.5  
GTs I/O GTs I/O GTs I/O GTs I/O GTs I/O GTs I/O  
N/A 220 N/A 400  
GTs  
I/O GTs I/O  
GTs  
I/O GTs I/O  
XC5VLX30  
XC5VLX50  
XC5VLX85  
XC5VLX110  
XC5VLX155  
XC5VLX220  
XC5VLX330  
XC5VLX20T  
N/A 220 N/A 440 N/A 560  
N/A 440 N/A 560  
N/A 440 N/A 800 N/A 800  
N/A 800 N/A 800  
N/A 800  
N/A 1,200  
4
172  
GTPs  
XC5VLX30T  
XC5VLX50T  
4
8
172  
360  
GTPs  
GTPs  
8
360 12 GTPs 480  
GTPs  
XC5VLX85T  
XC5VLX110T  
XC5VLX155T  
XC5VLX220T  
XC5VLX330T  
XC5VSX35T  
12 GTPs 480  
16 GTPs 640  
16 GTPs 640  
16 GTPs 680  
16 GTPs 680  
16 GTPs 680  
24 GTPs 960  
8
360  
GTPs  
XC5VSX50T  
8
360 12 GTPs 480  
16 GTPs 640  
GTPs  
XC5VSX95T  
XC5VSX240T  
XC5VTX150T  
24 GTPs 960  
40  
GTXs  
40  
360  
680  
680  
GTXs  
XC5VTX240T  
XC5VFX30T  
XC5VFX70T  
48  
GTXs  
8
360  
GTXs  
8
360 16 GTXs 640  
16 GTXs 640  
GTXs  
XC5VFX100T  
XC5VFX130T  
XC5VFX200T  
16 GTXs 680  
20 GTXs 840  
24 GTXs 960  
Notes:  
1. FFV1153 package is not available in the LX155 device.  
2. FFV1760 package is available in the LX110 device only.  
3. FFV1136 package is not available in the LX155T and FX100T devices.  
4. FFV1738 package is available in the LX110T device only.  
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Virtex-5 Family Overview  
Virtex-5 FPGA Ordering Information  
Virtex-5 FPGA ordering information shown in Figure 1 applies to all packages including Pb-Free.  
X-Ref Target - Figure 1  
Example: XC5VLX50T-1FFG665C  
Device Type  
Temperature Range:  
C = Commercial (TJ = 0°C to +85°C)  
I = Industrial (TJ = –40°C to +100°C)  
Speed Grade  
(-1, -2, -3(1))  
Note:  
Number of Pins  
1) -3 speed grade is not available in all devices  
Pb-Free  
V = RoHS 6/6  
G = RoHS 6/6 with exemption 15  
Package Type  
DS100_01_071515  
Figure 1: Virtex-5 FPGA Ordering Information  
12  
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Virtex-5 Family Overview  
Revision History  
The following table shows the revision history for this document.  
Date  
Version  
Revision  
04/14/06  
1.0  
Initial Xilinx release.  
First version posted to the Xilinx website. Minor typographical edits and description updates to highlight  
new features. Removed LUT utilization bullet from "Virtex-5 FPGA Logic," page 3.  
05/12/06  
1.1  
Added LXT platform to entire document. This includes descriptions of the RocketIO GTP transceivers,  
the Ethernet MACs, and the PCI Express Endpoint block.  
09/06/06  
10/12/06  
2.0  
2.1  
Added LX85T devices. Added System Monitor descriptions and functionality.  
Added LX220T devices. Revised the Total I/O banks for the LX330 in Table 1. Revised the  
XC5VLX50T-FFG665 example in Figure 1. Clarified support for "Differential SSTL 1.8V and 2.5V  
(Class I and II)," page 7.  
12/28/06  
2.2  
02/02/07  
05/23/07  
09/04/07  
12/11/07  
3.0  
3.1  
3.2  
3.3  
Added the SXT platform to entire document.  
Removed support for IEEE 1149.6  
Revised maximum line rate from 3.2 Gb/s to 3.75 Gb/s in entire document.  
Added LX20T, LX155T, and LX155 devices.  
Added Disclaimer. Revised CMT section on page 3. Clarified "Virtex-5 FPGA LogiCORE Endpoint  
Block Plus Wrapper for PCI Express," page 10.  
12/17/07  
3.4  
Added FXT platform to entire document.  
Clarified information in the following sections: "Integrated Endpoint Block for PCI Express Compliance"  
and "Tri-Mode Ethernet Media Access Controller."  
03/31/08  
4.0  
To avoid confusion with PLL functionality, removed PMCD references in "Global Clocking," page 8.  
04/25/08  
05/07/08  
4.1  
4.2  
Added XC5VSX240T to entire document.  
Updated throughout data sheet that the RocketIO GTX transceivers are designed to run from 150 Mb/s  
to 6.5 Gb/s.  
Clarified PPC440MC_DDR2 memory controller on page 5.  
Revised Ethernet MAC column in Table 1, page 2 and added Note 5. Also updated "Tri-Mode  
(10/100/1000 Mb/s) Ethernet MACs," page 9.  
06/18/08  
09/23/08  
4.3  
4.4  
Added TXT platform to entire document.  
Revised RocketIO GTX transciever datapath support on page 10.  
02/6/09  
5.0  
5.1  
Changed document classification to Product Specification from Advance Product Specification.  
Updated Table 2 and Figure 1 with RoHS package information.  
08/21/15  
DS100 (v5.1) August 21, 2015  
www.xilinx.com  
Product Specification  
13  
R
Virtex-5 Family Overview  
Disclaimer  
The information disclosed to you hereunder (the “Materials”) is provided solely for the selection and use of Xilinx products. To the  
maximum extent permitted by applicable law: (1) Materials are made available “AS IS” and with all faults, Xilinx hereby DISCLAIMS ALL  
WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF  
MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable  
(whether in contract or tort, including negligence, or under any other theory of liability) for any loss or damage of any kind or nature related  
to, arising under, or in connection with, the Materials (including your use of the Materials), including for any direct, indirect, special,  
incidental, or consequential loss or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of  
any action brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility  
of the same. Xilinx assumes no obligation to correct any errors contained in the Materials or to notify you of updates to the Materials or to  
product specifications. You may not reproduce, modify, distribute, or publicly display the Materials without prior written consent. Certain  
products are subject to the terms and conditions of Xilinx’s limited warranty, please refer to Xilinx’s Terms of Sale which can be viewed at  
http://www.xilinx.com/legal.htm#tos; IP cores may be subject to warranty and support terms contained in a license issued to you by Xilinx.  
Xilinx products are not designed or intended to be fail-safe or for use in any application requiring fail-safe performance; you assume sole  
risk and liability for use of Xilinx products in such critical applications, please refer to Xilinx’s Terms of Sale which can be viewed at  
http://www.xilinx.com/ legal.htm#tos.  
This document contains preliminary information and is subject to change without notice. Information provided herein relates to products  
and/or services not yet available for sale, and provided solely for information purposes and are not intended, or to be construed, as an offer  
for sale or an attempted commercialization of the products and/or services referred to herein.  
Automotive Applications Disclaimer  
XILINX PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE, OR FOR USE IN ANY APPLICATION REQUIRING FAIL-  
SAFE PERFORMANCE, SUCH AS APPLICATIONS RELATED TO: (I) THE DEPLOYMENT OF AIRBAGS, (II) CONTROL OF A  
VEHICLE, UNLESS THERE IS A FAIL-SAFE OR REDUNDANCY FEATURE (WHICH DOES NOT INCLUDE USE OF SOFTWARE IN  
THE XILINX DEVICE TO IMPLEMENT THE REDUNDANCY) AND A WARNING SIGNAL UPON FAILURE TO THE OPERATOR, OR (III)  
USES THAT COULD LEAD TO DEATH OR PERSONAL INJURY. CUSTOMER ASSUMES THE SOLE RISK AND LIABILITY OF ANY  
USE OF XILINX PRODUCTS IN SUCH APPLICATIONS.  
14  
www.xilinx.com  
DS100 (v5.1) August 21, 2015  
Product Specification  
R
Virtex-5 Family Overview  
Virtex-5 FPGA Documentation  
Complete and up-to-date documentation of the Virtex-5 family of FPGAs is available on the Xilinx website. In addition to the  
most recent Virtex-5 Family Overview, the following files are also available for download:  
Virtex-5 FPGA Data Sheet: DC and Switching  
Virtex-5 FPGA RocketIO GTX Transceiver User Guide  
Characteristics (DS202)  
(UG198)  
This data sheet contains the DC and Switching  
Characteristic specifications for the Virtex-5 family.  
This guide describes the RocketIO GTX transceivers  
available in the Virtex-5 TXT and FXT platforms.  
Virtex-5 FPGA User Guide (UG190)  
Virtex-5 FPGA Tri-Mode Ethernet MAC User Guide  
(UG194)  
This guide includes chapters on:  
This guide describes the dedicated Tri-Mode Ethernet  
Media Access Controller available in the Virtex-5 LXT, SXT,  
TXT, and FXT platforms.  
Clocking Resources  
Clock Management Technology (CMT)  
Phase-Locked Loops (PLL)  
Block RAM  
Configurable Logic Blocks (CLBs)  
SelectIO Resources  
Virtex-5 FPGA Integrated Endpoint Block for PCI  
Express Designs User Guide (UG197)  
This guide describes the integrated Endpoint blocks in the  
Virtex-5 LXT, SXT, TXT, and FXT platforms that are PCI  
Express compliant.  
SelectIO Logic Resources  
Advanced SelectIO Logic Resources  
Virtex-5 FPGA XtremeDSP Design Considerations  
(UG193)  
Embedded Processor Block in Virtex-5 FPGAs  
Reference Guide (UG200)  
This guide describes the DSP48E slice and includes  
reference designs for using DSP48E math functions and  
various filters.  
This reference guide is a description of the embedded  
processor block available in the Virtex-5 FXT platform.  
Virtex-5 FPGA Configuration Guide (UG191)  
This all-encompassing configuration guide includes  
chapters on configuration interfaces (serial and parallel),  
multi-bitstream management, bitstream encryption,  
Boundary-Scan and JTAG configuration, and  
reconfiguration techniques.  
Virtex-5 FPGA Packaging and Pinout Specification  
(UG195)  
This specification includes the tables for device/package  
combinations and maximum I/Os, pin definitions, pinout  
tables, pinout diagrams, mechanical drawings, and thermal  
specifications.  
Virtex-5 FPGA PCB Designer’s Guide (UG203)  
This guide provides information on PCB design for Virtex-5  
devices, with a focus on strategies for making design  
decisions at the PCB and interface level.  
Virtex-5 FPGA System Monitor User Guide (UG192)  
The System Monitor functionality is outlined in this guide.  
Virtex-5 FPGA RocketIO GTP Transceiver User Guide  
(UG196)  
This guide describes the RocketIO GTP transceivers  
available in the Virtex-5 LXT and SXT platforms.  
DS100 (v5.1) August 21, 2015  
www.xilinx.com  
Product Specification  
15  
配单直通车
XC5VLX330-1FFV1760I产品参数
型号:XC5VLX330-1FFV1760I
是否Rohs认证: 符合
生命周期:Active
IHS 制造商:XILINX INC
包装说明:BGA, BGA1760,42X42,40
Reach Compliance Code:unknown
风险等级:5.81
CLB-Max的组合延迟:0.9 ns
JESD-30 代码:S-PBGA-B1760
长度:42.5 mm
可配置逻辑块数量:25920
输入次数:1200
逻辑单元数量:331776
输出次数:1200
端子数量:1760
最高工作温度:100 °C
最低工作温度:-40 °C
组织:25920 CLBS
封装主体材料:PLASTIC/EPOXY
封装代码:BGA
封装等效代码:BGA1760,42X42,40
封装形状:SQUARE
封装形式:GRID ARRAY
可编程逻辑类型:FPGA
座面最大高度:3.5 mm
最大供电电压:1.05 V
最小供电电压:0.95 V
标称供电电压:1 V
表面贴装:YES
温度等级:INDUSTRIAL
端子形式:BALL
端子节距:1 mm
端子位置:BOTTOM
宽度:42.5 mm
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