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产品型号XC6129C48A7R-G的Datasheet PDF文件预览

XC6129Series  
Voltage Detector with Delay Time Adjustable  
ETR0222-002  
GENERAL DESCRIPTION  
XC6129 series is an ultra small highly accurate voltage detector with external capacitor type delay function.  
The device includes a highly accurate reference voltage source, manufactured using CMOS process and laser trimming  
technology, it maintains low power consumption and high accuracy. The device includes the built-in delay circuit. A release  
delay time or detect delay time can be set freely by connecting an external delay capacitor to Cd pin.  
There are two kinds of the output configuration for the XC6129 such as CMOS or N-channel open drain. The series has a  
function to prevent an indefinite operation. Therefore, when the input pin voltage is under minimum operating voltage,  
the function controls an output pin voltage in the indefinite operation less than 0.4V (MAX.). Also, the series allows a choice of  
an output logic when detection; therefore, it is suitable for various electric devices using Microcontrollers.  
Ultra small package USPN-4 and SSOT-24 (standard) are ideally suited for small design of portable devices and high  
densely mounting applications.  
FEATURES  
High Accuracy  
APPLICATIONS  
Microprocessor  
: ±0.8(Ta=25)  
: ±50ppm/(TYP.)  
Temperature Characteristic  
Hysteresis Width  
Logic circuit reset circuitry  
Battery check  
:
:
VDFx5% (TYP.) or Less than VDFx1%  
0.42μA TYP. (at Detect, VDF=2.7V)  
0.58μA TYP. (at Release, VDF=2.7V)  
1.5V5.5V (0.1V increments)  
1.3V6.0V  
Low Power Consumption  
Charge voltage monitors  
Memory battery back-up switch circuits  
System power on reset  
Power failure detection circuits  
Delay circuit  
Detect Voltage Options  
Operating Voltage Range  
Output Configuration  
Output Logic  
:
:
:
:
:
:
:
:
:
:
CMOS or N-channel Open Drain  
Active High or Active Low  
Release Delay Time  
Detect Delay Time  
Manual Reset Input  
Operating Ambient Temperature  
Packages  
13.9ms (Cd=0.01μF, RP=2M)  
17.9ms (Cd=0.01μF, Rn=2M)  
When Cd pin is “L” level, detect state  
-40℃ ~ +85℃  
USPN-4, SSOT-24  
Environmentally Friendly  
EU RoHS Compliant, Pb Free  
TYPICAL PERFORMANCE  
TYPICAL APPLICATION CIRCUITS  
CHARACTERISTICS  
VIN=VDF×0.9V→ VDF×1.1V  
Cd=0.1μF (tDR=139ms)  
XC6129  
200  
180  
160  
140  
120  
100  
-50  
-25  
0
25  
50  
75  
100  
Ambient Temperature : Ta (  
)
1/30  
XC6129 Series  
BLOCK DIAGRAMS  
1) XC6129C Series (Type A/B/C/D/E/F)  
V
IN  
M2  
R1  
M4  
M3  
Comparator  
Rp  
Rn  
DELAY/MR  
CONTROL  
BLOCK  
RESETB  
R2  
Vref  
M1  
VSS  
Cd/ MRB  
2) XC6129C Series (Type G/J/L)  
V
IN  
M2  
R1  
M4  
M3  
Comparator  
Rp  
Rn  
DELAY/MR  
CONTROL  
BLOCK  
RESET  
R2  
Vref  
M1  
VSS  
Cd/MRB  
* Diodes inside the circuits are ESD protection diodes and parasitic diodes.  
2/30  
XC6129  
Series  
BLOCK DIAGRAMS  
3) XC6129N Series (Type A/C/E)  
V
IN  
M2  
R1  
Comparator  
Rp  
Rn  
DELAY/MR  
CONTROL  
BLOCK  
RESETB  
M3  
R2  
Vref  
M1  
VSS  
Cd/ MRB  
4) XC6129N Series (Type G/J/L)  
V
IN  
M2  
R1  
Comparator  
Rp  
DELAY/MR  
CONTROL  
BLOCK  
RESET  
Rn  
M3  
R2  
Vref  
M1  
VSS  
Cd/MRB  
* Diodes inside the circuits are ESD protection diodes and parasitic diodes.  
3/30  
XC6129 Series  
PRODUCT CLASSIFICATION  
Ordering Information  
XC6129①②③④⑤⑥-⑦  
(*1)  
DESIGNATOR  
ITEM  
SYMBOL  
DESCRIPTION  
CMOS output  
C
Output Configuration  
Detect Voltage  
N
Nch open drain output  
②③  
15~55  
e.g. 1.8V =1, =8  
A
B
C
D
E
F
Type  
Refer to Selection Guide  
G
J
L
NR-G  
SSOT-24 (3,000/Reel)  
USPN-4 (5,000/Reel)  
(*1)  
⑤⑥-⑦  
Packages (Order Unit)  
7R-G  
(*1) The “-G” suffix denotes Halogen and Antimony free as well as being fully EU RoHS compliant.  
Selection Guide  
RESETB/RESET  
OUTPUT  
HYSTERESIS  
WIDTH  
RELEASE  
DELAY  
DETECT  
DELAY  
Undefined Operation  
Protect  
TYPE  
A
B
C
D
E
F
G
J
No  
Yes (*2)  
No  
Yes  
No  
No  
Yes  
Yes  
Reset Active Low  
Yes (*2)  
5% (TYP.)  
No  
Yes  
Yes (*2)  
Yes  
No  
No  
Yes  
Yes  
Reset Active High  
No  
L
Yes  
(*2) Only supported with CMOS output.  
4/30  
XC6129  
Series  
PIN CONFIGURATION  
USPN-4  
(BOTTOM VIEW)  
SSOT-2
(TOP VIEW)  
PIN ASSIGNMENT  
PIN NUMBER  
PIN NAME  
FUNCTIONS  
SSOT-24 USPN-4  
1
2
4
3
VIN  
Power Input  
Ground  
VSS  
Adjustable Pin for DelayTime  
/Manual Reset  
3
2
Cd/MRB  
RESETB  
RESET  
Reset Output (Active Low) (*1)  
Reset Output (Active High) (*2)  
4
1
(*1) Type AF (Refer to the in Ordering Information table)  
(*2) Type GM (Refer to the in Ordering Information table)  
5/30  
XC6129 Series  
FUNCTION CHART  
PIN NAME  
Cd/MRB  
SIGNAL  
STATUS  
L
H
Forced Reset  
Release  
OPEN  
Normal Operation  
Refer to the table below.  
1) Output Logic: Active Low  
Function Chart  
VIN  
VCd//MRB  
Transition of VRESETB Condition  
Reset (Low Level) (*1)  
Release (High Level) (*2)  
Reset (Low Level) (*1)  
Undefined (*3)  
V
Cd/MRBVMRL  
VINVDF+VHYS  
VINVDF  
V
Cd/MRBVMRH  
Cd/MRBVMRL  
V
V
Cd/MRBVMRH  
2) Output Logic: Active High  
Function Chart  
VIN  
VCd/MRB  
Transition of VRESET Condition  
Reset (High Level) (*2)  
V
Cd/MRBVMRL  
Cd/MRBVMRH  
Cd/MRBVMRL  
Cd/MRBVMRH  
VINVDF+VHYS  
VINVDF  
V
Release (Low Level) (*1)  
Reset (High Level) (*2)  
Undefined (*3)  
V
V
(* 1) CMOS output: VIN × 0.1 or less, N-ch open drain output, pull-up voltage × 0.1 or less.  
(* 2) CMOS output: VIN × 0.9 or higher, N-ch open drain output, pull-up voltage × 0.9 or higher.  
(* 3) Refer to the OPERATING DESCRIPTION <Manual reset function> below.  
6/30  
XC6129  
Series  
ABSOLUTE MAXIMUM RATINGS  
Ta=25℃  
PARAMETER  
Input Voltage  
SYMBOL  
VIN  
RATINGS  
UNITS  
V
-0.3+6.5  
XC6129C (*1)  
±50  
IRBOUT  
IROUT  
Output Current  
Output Voltage  
mA  
V
XC6129N (*2)  
XC6129C (*1)  
XC6129N (*2)  
50  
VSS-0.3VIN+0.3 or +6.5 (*3)  
VSS-0.3+6.5  
VSS-0.3VIN+0.3  
±5  
VRESETB  
VRESET  
Cd/MRB Pin Voltage  
Cd/MRB Pin Current  
SSOT-24  
USPN-4  
VCd/MRB  
ICd/MRB  
V
mA  
150  
Power Dissipation  
Pd  
mW  
100  
Operating Ambient Temperature  
Storage Temperature  
Topr  
Tstg  
-40+85  
-55+125  
* All voltages are described based on the VSS  
.
(*1) CMOS Output  
(*2) N-ch Open Drain Output  
(*3) The maximum value should be either VIN+0.3 or +6.5 in the lowest.  
7/30  
XC6129 Series  
ELECTRICAL CHARACTERISTICS  
XC6129xxxA~XC6129xxxF Series (Output Logic: Active Low)  
Ta=25℃  
PARAMETER  
SYMBOL  
CONDITIONS  
VDF(T) (*1)=1.5V5.5V  
MIN.  
TYP.  
VDF(T)  
E-1(*2)  
MAX.  
UNITS  
V
CIRCUIT  
VDF(T)×0.992  
VDF(T)×1.008  
Detect Voltage  
VDF  
Temperature  
Characteristics  
VDF  
/
-40Topr85℃  
-
±50  
-
ppm/℃  
(Topr VDF)  
Hysteresis Width  
Supply Current 1  
VHYS  
ISS1  
-
VDF×0.03  
VDF×0.05  
E-2 (*2)  
VDF×0.07  
V
VIN= VDF×0.9V (Detect)  
μA  
-
VIN=VDF×1.1V  
(Type:A,C,E)  
(Type:B,D,F)  
E-3 (*2)  
E-31 (*2)  
-
Supply Current 2  
Operating Voltage  
ISS2  
VIN  
(Release)  
-
1.3  
1.7  
5.2  
8.6  
10.6  
11.7  
-
6.0  
-
V
VIN=1.3V, VRESETB=0.5V (N-ch)  
3.0  
VIN=2.0V(*3), VRESETB=0.5V (N-ch)  
VIN=3.0V(*4), VRESETB=0.5V (N-ch)  
VIN=4.0V(*5), VRESETB=0.5V (N-ch)  
VIN=5.0V(*6), VRESETB=0.5V (N-ch)  
VIN=2.0V(*8), VRESETB=VIN-0.5V (P-ch)  
VIN=3.0V(*9), VRESETB=VIN-0.5V (P-ch)  
VIN=4.0V(*10), VRESETB=VIN-0.5V (P-ch)  
VIN=5.0V(*11), VRESETB=VIN-0.5V (P-ch)  
VIN=6.0V, VRESETB=VIN-0.5V (P-ch)  
6.7  
-
IRBOUT1  
10.2  
12.3  
13.5  
-1.9  
-3.1  
-4.0  
-4.7  
-5.2  
-
-
-
Output Current  
mA  
-0.9  
-2.1  
-3.0  
-3.7  
-4.2  
-
(*7)  
IRBOUT2  
-
-
-
CMOS Output  
VIN=VDF×0.9V, VRESETB=0V  
VIN=6.0V, VRESETB=6.0V  
-
-
-0.01  
0.01  
-
Leakage  
Current  
(P-ch)  
ILEAK  
μA  
N-ch Open  
Drain Output  
0.1  
VIN=6.0V, VCd/MRB =0V  
(Type: A, B, E, F)  
Rp  
Rn  
Delay Resistance (*12)  
1.8  
2.0  
2.15  
MΩ  
VIN=VCd/MRB=VDF×0.9V  
(Type: C, D, E, F)  
Undefined Operation (*13)  
Release Delay Time  
Detect Delay Time  
VUNS  
tDR0  
tDF0  
-
-
0.4  
V
ms  
ms  
V
VIN<1.3V  
VIN=VDF×0.9VVDF×1.1V (*14)  
Cd: OPEN  
VIN=VDF×1.1VVDF×0.9V (*15)  
Cd: OPEN  
-
0.05  
-
-
0.13  
-
VIN=VDF×1.1V6.0V (Release)  
VTCD  
VIN×0.44  
VIN×0.50  
VIN×0.56  
Cd Threshold Voltage  
VIN=VDF×0.9V (Detect)  
VIN=VDF×1.1V6.0V  
VIN=VDF×1.1V6.0V  
VIN=VDF×1.1V  
MRB Low Level Voltage  
MRB High Level Voltage  
VMRL  
VMRH  
0
-
-
VIN×0.17  
VIN  
V
V
VIN×0.56  
Minimum MRB Pulse Width  
tMRB  
5.0  
-
-
μs  
V
Cd/MRB =VIN0VVIN  
(*1)  
V
: Nominal detect voltage  
DF(T)  
(*2) For the detail value, please refer to “Voltage Table”.  
(*3) For VDF(T)2.0V only  
(*4) For VDF(T)3.0V only  
(*5) For VDF(T)4.0V only  
(*6) For VDF(T)5.0V only  
(*7) For XC6129C (CMOS output) only  
(*8) For VDF(T)1.8V only  
(*9) For VDF(T)2.7V only。  
(*10) For VDF(T)3.7V only  
(*11) For VDF(T)4.6V only  
(*12) Resistance is calculated from voltage applied to Cd/MRB pin and current.  
(*13) Types B/D/F of XC6129C series only.  
(*14) Time from VIN=VDF + VHYS until VRESETB=VDF × 1.1 × 0.9 when VIN rises. (CMOS output)  
Time from VIN=VDF + VHYS until VRESETB=Pull-up voltage × 0.9 when VIN rises. (N-ch open drain output)  
(*15) Time from VIN=VDF until VRESETB=VDF × 0.9 × 0.1 when VIN drops. (CMOS output)  
Time from VIN=VDF until VRESETB=Pull-up voltage × 0.1 when VIN drops. (N-ch open drain output)  
8/30  
XC6129  
Series  
ELECTRICAL CHARACTERISTICS (Continued)  
XC6129xxxG~XC6129xxxL Series (Output Logic: Active High)  
Ta=25℃  
PARAMETER  
SYMBOL  
CONDITIONS  
MIN.  
TYP.  
VDF(T)  
E-1 (*2)  
MAX.  
UNITS CIRCUIT  
VDF(T)×0.992  
VDF(T)×1.008  
Detect Voltage  
VDF  
VDF(T) (*1)=1.5V5.5V  
V
ppm/℃  
V
Temperature  
VDF  
/
-40Topr85℃  
-
±50  
-
Characteristics  
(Topr VDF)  
VDF×0.03  
VDF×0.05  
VDF×0.07  
Hysteresis Width  
VHYS  
-
Supply Current 1  
Supply Current 2  
Operating Voltage  
ISS1  
ISS2  
VIN  
VIN=VDF×0.9V (Detect)  
VIN= VDF×1.1V (Release)  
-
VIN=2.0V(*3), VRESET=0.5V (N-ch)  
VIN=3.0V(*4), VRESET=0.5V (N-ch)  
VIN=4.0V(*5), VRESET=0.5V (N-ch)  
E-2 (*2)  
E-3 (*2)  
-
μA  
-
1.3  
5.2  
6.0  
V
6.7  
-
-
-
8.6  
10.2  
12.3  
IROUT1  
10.6  
VIN=5.0V(*6), VRESET=0.5V (N-ch)  
11.7  
13.5  
14.3  
-0.9  
-1.9  
-
VIN=6.0V, VRESET=0.5V (N-ch)  
12.4  
-
Output Current  
mA  
VIN=1.3V, VRESET=VIN-0.5V (P-ch)  
VIN=2.0V(*8), VRESET=VIN-0.5V (P-ch)  
-
-
-0.1  
-0.9  
VIN=3.0V(*9), VRESET=VIN-0.5V (P-ch)  
VIN=4.0V(*10), VRESET=VIN-0.5V (P-ch)  
VIN=5.0V(*11), VRESET=VIN-0.5V (P-ch)  
(*7)  
-
-
-
-3.1  
-4.0  
-4.7  
-2.1  
-3.0  
-3.7  
IROUT2  
CMOS Output  
-
-
-0.01  
0.01  
-
VIN=6.0V, VRESET=0V  
(P-ch)  
Leakage  
Current  
ILEAK  
μA  
N-ch Open  
Drain Output  
0.1  
VIN=VDF×0.9V, VRESET=6.0V  
VIN=6.0V, VCd/MRB=0V  
(Type: G, L)  
Rp  
Rn  
Delay Resistance (*12)  
MΩ  
1.8  
2.0  
2.15  
VIN= VCd/MRB=VDF×0.9V  
(Type: J,L)  
VIN=VDF×0.9VVDF×1.1V (*13)  
-
0.05  
0.13  
-
Release Delay Time  
Detect Delay Time  
tDR0  
ms  
ms  
V
Cd: OPEN  
VIN=VDF×1.1VVDF×0.9V (*14)  
-
-
tDF0  
Cd: OPEN  
VIN=VDF×1.1V6.0V (Release)  
VIN×0.44  
VIN×0.50  
VIN×0.56  
Cd Threshold Voltage  
VTCD  
VIN=VDF×0.9V (Detect)  
VIN=VDF×1.1V6.0V  
VIN=VDF×1.1V6.0V  
0
-
-
VIN×0.17  
VIN  
MRB Low Level Voltage  
MRB High Level Voltage  
VMRL  
VMRH  
V
V
VIN×0.56  
VIN=VDF×1.1V  
5.0  
-
-
Minimum MRB Pulse Width  
tMRB  
μs  
V
Cd/MRB=VIN0VVIN  
(*1)  
V
: Nominal detect voltage  
DF(T)  
(*2) For the detail value, please refer to “Voltage Table”.  
(*3) For VDF(T)1.8V only  
(*4) For VDF(T)2.7V only  
(*5) For VDF(T)3.7V only  
(*6) For VDF(T)4.6V only  
(*7) For XC6129C (CMOS output) only  
(*8) For VDF(T)2.0V only  
(*9) For VDF(T)3.0V only。  
(*10) For VDF(T)4.0V only  
(*11) For VDF(T)5.0V only  
(*12) Resistance is calculated from voltage applied to Cd/MRB pin and current.  
(*13) Time from VIN=VDF + VHYS until VRESETB=VDF × 1.1 × 0.1 when VIN rises. (CMOS output)  
Time from VIN=VDF + VHYS until VRESETB=Pull-up voltage × 0.1 when VIN rises. (N-ch open drain output)  
(*14) Time from VIN=VDF until VRESETB=VDF × 0.9 × 0.9 when VIN drops. (CMOS output)  
Time from VIN=VDF until VRESETB=Pull-up voltage × 0.9 when VIN drops. (N-ch open drain output)  
9/30  
XC6129 Series  
ELECTRICAL CHARACTERISTICS (Continued)  
Ta=25℃  
Voltage Table  
E-1  
DETECT VOLTAGE (V)  
VDF  
E-2  
E-3  
E-31  
NOMINAL  
DETECT  
VOLTAGE  
Supply Current1  
Supply Current2  
(μA)  
(μA)  
ISS1  
ISS2  
VDF(T)  
(V)  
MIN.  
MAX.  
MIN.  
TYP.  
0.38  
MAX.  
MIN.  
-
TYP.  
0.47  
MAX.  
1.39  
MIN.  
-
TYP.  
0.63  
MAX.  
1.67  
1.5  
1.6  
1.7  
1.8  
1.9  
2.0  
2.1  
2.2  
2.3  
2.4  
2.5  
2.6  
2.7  
2.8  
2.9  
3.0  
3.1  
3.2  
3.3  
3.4  
3.5  
3.6  
3.7  
3.8  
3.9  
4.0  
4.1  
4.2  
4.3  
4.4  
4.5  
4.6  
4.7  
4.8  
4.9  
5.0  
5.1  
5.2  
5.3  
5.4  
5.5  
1.4880  
1.5872  
1.6864  
1.7856  
1.8848  
1.9840  
2.0832  
2.1824  
2.2816  
2.3808  
2.4800  
2.5792  
2.6784  
2.7776  
2.8768  
2.9760  
3.0752  
3.1744  
3.2736  
3.3728  
3.4720  
3.5712  
3.6704  
3.7696  
3.8688  
3.9680  
4.0672  
4.1664  
4.2656  
4.3648  
4.4640  
4.5632  
4.6624  
4.7616  
4.8608  
4.9600  
5.0592  
5.1584  
5.2576  
5.3568  
5.4560  
1.5120  
1.6128  
1.7136  
1.8144  
1.9152  
2.0160  
2.1168  
2.2176  
2.3184  
2.4192  
2.5200  
2.6208  
2.7216  
2.8224  
2.9232  
3.0240  
3.1248  
3.2256  
3.3264  
3.4272  
3.5280  
3.6288  
3.7296  
3.8304  
3.9312  
4.0320  
4.1328  
4.2336  
4.3344  
4.4352  
4.5360  
4.6368  
4.7376  
4.8384  
4.9392  
5.0400  
5.1408  
5.2416  
5.3424  
5.4432  
5.5440  
-
1.11  
-
0.42  
1.16  
-
0.58  
1.60  
-
0.74  
1.88  
-
0.47  
1.31  
-
0.71  
1.90  
-
0.87  
2.18  
-
0.52  
1.41  
-
0.83  
2.17  
-
0.99  
2.45  
10/30  
XC6129  
Series  
TEST CIRCUITS  
CIRCUIT①  
CIRCUIT②  
CIRCUIT③  
CIRCUIT④  
11/30  
XC6129 Series  
TEST CIRCUITS (Continued)  
CIRCUIT⑤  
CIRCUIT⑥  
CIRCUIT⑦  
CIRCUIT⑧  
12/30  
XC6129  
Series  
OPERATIONAL DESCRIPTION  
Fig. 1 shows a typical circuit Fig. 2 shows the timing chart of Fig. 1.  
V
IN  
M2  
R1  
M4  
M3  
Comparator  
Rp  
Rn  
DELAY/MR  
CONTROL  
RESETB  
BLOCK  
* The XC6129N series  
(N-ch open drain output)  
requires a resistor to pull  
up the output.  
R2  
Vref  
M1  
VSS  
VDD  
Cd/ MRB  
Cd  
RESET  
SW  
Fig. 1: Typical circuit (Active Low product)  
Power input voltage: VIN  
Release voltage: VDF + VHYS  
Detect voltage: VDF  
Minimum operating voltage (1.3V)  
Delay capacitance pin voltage: VCd/MRB  
Delay capacitance pin threshold voltage: VTCD  
Output pin voltage: VRESETB  
Fig. 2: img cart of Fi. 1  
(1) In the initial state, a voltage sufficiently high in relation to the release voltage is applied to the VIN power input pin, and the  
Cd/MRB delay capacitance pin is charged to the power input pin voltage.  
The power input pin voltage starts to drop, and during the interval until it reaches the detect voltage (VIN>VDF), the output pin  
voltage VRESETB is at High level.  
(2) The power input pin voltage continues to drop, and when it reaches the detect voltage (VIN=VDF), the Nch transistor for delay  
capacitance discharge turns ON and discharge of the delay capacitance starts.  
When the delay capacitance pin drops below the delay capacitance pin threshold voltage, VRESETB changes to Low level.  
The time from VIN=VDF until VRESETB changes to Low level is the detect delay tDF (the detect time when the delay capacitance  
pin is open is tDF0).  
13/30  
XC6129 Series  
OPERATIONAL DESCRIPTION (Continued)  
(3) The power input pin voltage drops further, and during the interval when it is below the detect voltage VDF and higher than 1.3V,  
the delay capacitance pin is discharged to ground level and the output pin voltage VRESETB maintains Low level.  
(4) During the interval in which the power input pin voltage drops below 1.3V and then rises back to 1.3V or higher, the output pin  
voltage VRESETB may not be able to maintain Low level. Operation during this interval is called “unstable operation”, and the  
voltage that appears in VRESETB is called the “unstable operation voltage VUNS”.  
(5) The power input pin voltage rises, and during the interval that it is higher than 1.3V until it reaches the release voltage  
(1.3VVIN<VDF+VHYS), the output pin voltage VRESETB maintains Low level.  
(6) The power input pin voltage continues to rise, and when it reaches the release voltage (VDF+VHYS), the Nch transistor for delay  
capacitance discharge turns OFF and charging of the delay capacitance pin through delay resistor Rp starts.  
(7) During the interval that the power input pin voltage continues to maintain a voltage higher than the release voltage, the delay  
capacitance pin is charged up to the power input pin voltage.  
When the delay capacitance pin voltage reaches VTCD, the output pin voltage VRESETB changes to High level.  
The time from VIN=VDF+VHYS until VRESETB changes to High level is the release delay time tDR (the release time when the delay  
capacitance pin is open is tDR0).  
(8) During the time that the power input pin voltage is higher than the detect voltage (VIN>VDF), the output pin voltage VRESETB  
maintains High level.  
The above operational explanation is for detection using Active Low products.  
For Active High products, reverse the logic of VRESETB  
.
14/30  
XC6129  
Series  
OPERATIONAL DESCRIPTION (Continued)  
<Release delay time / detect delay time>  
The release delay time and detect delay time are determined by the delay resistance (Rp and Rn) and the delay capacitance (Cd).  
The delay resistance is set to 2M(TYP.) internally in the circuit, and thus the delay time can be changed using the delay  
capacitance.  
You can select a product type that has or does not have the release delay time function and the detect delay time function. (Refer  
to the Selection Guide.)  
The release delay tDR is calculated using equation (1).  
t
DR=Rp×Cd×{-ln(1-VTCD/VIN)}+tDR0 …(1)  
Rn : Delay resistance 2.0M(TYP.)  
TCD : Delay capacitance pin threshold voltage VIN/2 (TYP.)  
* ln is the natural logarithm.  
V
When tDR0 can be neglected, this can be calculated in a simple manner using equation (2).  
DR=Rp×Cd×[-ln{1-(VIN/2)/VIN}]=Rp×Cd×0.693 …(2)  
t
Example: When the delay capacitance Cd is 0.68μF, the release delay time tDR is 2.0×106×0.68×10-6×0.693=942(ms).  
The detect delay tDF is calculated using equation (3).  
t
DF=Rn×Cd×-ln(VTCD/VIN1)}+tDF0 …(3)  
Rn: Delay resistance 2.0M(TYP.)  
VTCD: Delay capacitance pin threshold voltage VIN2/2 (TYP.) *VIN2 is the power input pin voltage at detection.  
IN1: Power input pin voltage at release  
* ln is the natural logarithm.  
V
When VIN=VDF×1.1VVDF×0.9V and tDF0 can be neglected, this can be calculated in a simple manner using equation (4).  
DF=Rn×Cd×{-ln(VIN2/2)/VIN1}=Rn×Cd×[-ln{(VDF×0.9×0.5)/(VDF×1.1)}]=Rn×Cd×0.894 …(4)  
t
For details of the detect delay time of equation (4), refer to Fig. 3.  
Example: When the delay capacitance Cd is 0.68μF at VIN=VDF×1.1VVDF×0.9V, the detect delay time tDF is 2.0×106×0.68×10-6×0.894=1216(ms).  
VIN=VDF x 1.1V  
Power input pin voltage: VIN  
VIN2=VDF x 0.9V  
Release state (VIN1  
)
Detect delay time: tDF  
Output pin voltage: VRESETB  
Detect state (VSS  
)
Release state (VIN1  
)
VIN1=VDF x 1.1V  
Delay capacitance pin threshold voltage  
VTCD=VIN2/2=0.9x0.5  
Delay capacitance pin voltage: VCd/MRB  
Fig. 3: Detect delay time of equation (4) (timing chart)  
Delay time table  
Delay capacitance Cd  
(μF)  
Release delay time tDR (ms) (*1)  
Detect delay time tDF (ms) (*1)  
TYP.  
13.9  
30.5  
65.1  
139  
MIN.toMAX. (*2)  
10.4 to 17.7  
22.9 to 38.9  
48.9 to 83.0  
104 to 177  
TYP.  
17.9  
39.3  
84.0  
179  
MIN.toMAX. (*2)  
0.01  
0.022  
0.047  
0.1  
12.7 to 22.0  
28.0 to 48.4  
59.8 to 103.3  
127 to 220  
0.22  
0.47  
1
305  
229 to 389  
393  
280 to 484  
651  
489 to 830  
840  
598 to 1033  
1274 to 2198  
1386  
1042 to 1766  
1788  
The release delay time values are the values calculated from equation (2).  
The detect delay time values are the values calculated from equation (4).  
(*1) Note that the delay time will vary depending on the actual capacitance value of the delay capacitance Cd.  
(*2) The values are calculated with consideration given to deviations in the delay resistance and delay capacitance pin threshold voltage.  
15/30  
XC6129 Series  
OPERATIONAL DESCRIPTION (Continued)  
<Manual reset function>  
The reset output pin signal can be forced into the detect state by inputting a voltage into the delay capacitance pin when in the  
release state.  
When the delay capacitance pin voltage input reaches an HL level signal, the reset output pin outputs an HL level signal.  
(RESETBActive Low type)  
When the delay capacitance pin voltage input reaches an HL level signal, the reset output pin outputs an LH level signal.  
(RESETActive High type)  
* During manual reset, there is no delay time even when a delay capacitance is connected.  
* When the delay capacitance pin voltage input reaches an LH level signal in the detection state, the reset output pin outputs an  
LH level signal.  
(RESETBActive Low type)  
* When the delay capacitance pin voltage input reaches an LH level signal in the detection state, the reset output pin outputs an  
HL level signal.  
(RESETActive High type)  
Under the detect condition, the condition will be kept even if the RESET switch turns on and off.  
In the case that either H level or L level is fed to the Cd/MRB pin without the RESET switch, the behavior of the XC6129 follows  
the timing chart in Fig. 4.  
L level is fed to the MRB pin under the detect condition, the RESET switch will be kept.  
H level is fed to the MRB pin under the detect condition, the RESET switch will be undefined.  
Even though the voltage at the VSEN pin changes from a higher voltage than the detect voltage to a lower voltage, as long as H  
level is fed to the MRB pin, the release condition is kept.  
If H level or L level is fed to the Cd/MRB pin forcibly, then even though Cd is connected to the pin, the XC6129 can’t have any  
delay time.  
Release voltage:VDF+VHYS  
Detect voltage:VDF  
Input Voltage:VINMIN.:0V,MAX.:6.0V)  
MRB High level voltage:VMRH  
Cd pin threshold voltage:VTCd  
MRB Low level voltage:VMRL  
Cd/MRB pin voltage:VCd/MRB (MIN.:VSS,MAX.:VIN  
)
Release voltage:VDF+VHYS  
Detect voltage:VDF  
Undefined  
Output voltage:VRESETB  
(MIN.:VSS,MAX.:VIN(CMOS),Vpull(Nch open drain))  
Fig. 4: Manual reset operation by the delay capacitance pin (Active Low product)  
<Unstable operation prevention function>  
Types B/D/F of the XC6129C series include an unstable operation prevention function.  
When the power input pin voltage is less than the minimum operation voltage, the output pin voltage due to unstable operation  
is limited to 0.4V (MAX.) or less.  
* Types A/C/E of the XC6129C series and each of the XC6129N series do not have an unstable operation prevention function.  
16/30  
XC6129  
Series  
NOTE ON USE  
1) Please use this IC within the stated maximum ratings. For temporary, transitional voltage drop or voltage rising phenomenon, the IC is  
liable to malfunction should the ratings be exceeded.  
2) The power input pin voltage may fall due to the flow through current during IC operation and the resistance component  
between the power supply and the power input pin.  
In the case of CMOS output, a drop in the power input pin voltage may occur in the same way due to the output current. When  
this happens, if the power input pin voltage drops below the minimum operating voltage, malfunctioning may occur.  
In addition, when the power input pin voltage is below the detect voltage, the output pin voltage may oscillate. Exercise  
caution in particular if a resistor is connected to the power input pin.  
3) Note that large, sharp changes of the power input pin voltage may cause malfunctioning.  
4) Power supply noise is sometimes a cause of malfunctioning. Sufficiently test using the actual device, such as inserting a  
capacitor between VIN and GND.  
5) If a capacitor is connected to the delay capacitance pin and the power input pin voltage drops suddenly during release operation (for  
example, from 6.0V to 0V), there is a possibility that the delay capacitance pin voltage will exceed the absolute maximum rating. If  
there is a possibility that the power input pin voltage will drop suddenly during release operation, connect a Schottky diode  
between the power input pin and delay capacitance pin as shown in Fig. 5.  
(not needed with CMOS output)  
Fig. 5: Circuit example with a Schottky diode connected to the delay capacitance pin  
6) When an N-ch open drain output is used, the VRESETB voltage at detection and release is determined by the pull-up resistance  
connected to the output pin. Refer to the following when selecting the resistance value.  
At detection:  
V
RESETB=Vpull/(1+Rpull/RON  
)
Vpull : Voltage after pull-up  
RON(*1): ON resistance of N-ch driver M3 (calculated from VRESETB/IRBOUT1 based on electrical characteristics)  
Example: When VIN=2.0V(*2), RON=0.5/5.2×10-3=96(MAX.). If it is desired to make VRESETB at detection 0.1V or less when Vpull is 3.0V,  
Rpull=(Vpull/VRESETB-1)×RON=(3/0.1-1)×962.8kΩ  
Therefore, to make the output voltage at detection 0.1V or less under the above conditions, the pull-up resistance must be 2.8kor higher.  
(*1) Note that RON becomes larger as VIN becomes smaller.  
(*2) For VIN in the calculation, use the lowest value of the input voltage range you will use.  
At release:  
V
RESETB=Vpull/(1+Rpull/Roff)  
pull: Voltage after pull-up  
V
Roff: Resistance when N-ch driver M3 is OFF (calculated from VRESETB/ILEAK based on electrical characteristics)  
Example: When Vpull is 6.0V, Roff=6/(0.1×10-6)=60M(MIN.). If it is desired to make VRESETB 5.99V or higher,  
R
pull=(Vpull/VRESETB-1)×Roff=(6/5.99-1)×60×106100kΩ  
Therefore, to make the output voltage at release 5.99V or higher under the above conditions, the pull-up resistance must be  
100kor less.  
17/30  
XC6129 Series  
NOTE ON USE (Continued)  
7) If the discharge time of the delay capacitance Cd at detection is short and the delay capacitance Cd cannot be discharged to  
ground level, charging will take place at the next release operation with electric charge remaining in the delay capacitance Cd,  
and this may cause the release delay time to become noticeably short.  
8) If the charging time of the delay capacitance Cd at release is short and the delay capacitance Cd cannot be charged to the  
VIN level, the delay capacitance Cd will discharge from less than the VIN level at the next detection operation, and this may  
cause the detect delay time to become noticeably short.  
9) Even with a non-delay type, a delay time is added when a delay capacitance Cd is connected.  
10) For a manual reset function, in case when the function is activated by feeding either MRB H level or MRB L level to Cd/MRB  
pin instead of using a reset switch, please note these phenomena below;  
The RESET output signal will be undefined when MRB H is fed to Cd/MRB pin under the detect condition.  
The RESET output signal will be undefined based on the voltage relationship between VSEN pin and Cd/MRB pin.  
11) Torex places an importance on improving our products and their reliability.  
We request that users incorporate fail-safe designs and post-aging protection treatment when using Torex products in their  
systems.  
18/30  
XC6129  
Series  
TYPICAL PERFORMANCE CHARACTERISTICS  
(1) Detect, Release Voltage vs. Ambient Temperature  
XC6129 (VDF(T)=1.5V)  
XC6129 (VDF(T)=2.7V)  
1.600  
1.575  
1.550  
1.525  
1.500  
1.475  
1.450  
2.90  
2.85  
2.80  
2.75  
2.70  
2.65  
VDR  
VDR  
VDF  
VDF  
-50  
-25  
0
25  
50  
75  
100  
-50  
-25  
0
25  
50  
75  
100  
Ambient Temperature : Ta (  
)
Ambient Temperature : Ta (  
)
(2) Detect, Release Voltage vs. Input Voltage  
XC6129 (VDF(T)=5.5V)  
XC6129C (VDF(T)=1.5V)  
Type : A/C/E  
No Pull-up  
5.85  
5.80  
5.75  
5.70  
5.65  
5.60  
5.55  
5.50  
5.45  
5.40  
6
: V  
: V  
DF
5
4
3
2
1
0
DR
VDR  
Ta=-40  
Ta=25  
Ta=85  
VDF  
0
1
2
3
4
5
6
-50  
-25  
0
25  
50  
75  
100  
Input Voltage : VIN (V)  
Ambient Temperature : Ta (  
)
XC6129C (VDF(T)=2.7V)  
XC6129C (VDF(T)=5.5V)  
Type : A/C/E  
No Pull-up  
Type : A/C/E  
No Pull-up  
6
5
4
3
2
1
0
6
: V  
: V  
: V  
DF
DF
5
4
3
2
1
0
: V  
DR
DR
Ta=-40  
Ta=25  
Ta=-40  
Ta=85  
Ta=25  
Ta=85  
0
1
2
3
4
5
6
0
1
2
3
4
5
6
Input Voltage : VIN (V)  
Input Voltage : VIN (V)  
19/30  
XC6129 Series  
TYPICAL PERFORMANCE CHARACTERISTICS (Continued)  
(2) Detect, Release Voltage vs. Input Voltage (Continued)  
(3) Supply Current vs. Input Voltage  
XC6129 (VDF(T)=1.5V)  
1.50  
1.35  
Ta=-40  
1.20  
1.05  
0.90  
0.75  
0.60  
0.45  
0.30  
0.15  
0.00  
Ta=25  
Ta=85  
0
1
2
3
4
5
6
Input Voltage: VIN (V)  
XC6129 (VDF(T)=2.7V)  
XC6129 (VDF(T)=5.5V)  
1.50  
1.35  
1.20  
1.05  
0.90  
0.75  
0.60  
0.45  
0.30  
0.15  
0.00  
1.50  
1.35  
1.20  
1.05  
0.90  
0.75  
0.60  
0.45  
0.30  
0.15  
0.00  
Ta=-40  
Ta=-40  
Ta=25  
Ta=25  
Ta=85  
Ta=85  
0
1
2
3
4
5
6
0
1
2
3
4
5
6
Input Voltage: VIN (V)  
Input Voltage: VIN (V)  
20/30  
XC6129  
Series  
TYPICAL PERFORMANCE CHARACTERISTICS (Continued)  
(4) Supply Current vs. Ambient Temperature  
XC6129 (VDF(T)=1.5V)  
XC6129 (VDF(T)=2.7V)  
VIN=VDF 0.9V (Detect)  
VIN=VDF 0.9V (Detect)  
×
×
V
IN=VDF 1.1V (Release)  
×
VIN=VDF 1.1V (Release)  
×
1.50  
1.35  
1.20  
1.05  
0.90  
0.75  
0.60  
0.45  
0.30  
0.15  
0.00  
1.50  
1.35  
1.20  
1.05  
0.90  
0.75  
0.60  
0.45  
0.30  
0.15  
0.00  
Detect  
Detect  
Release  
Release  
-50  
-25  
0
25  
50  
75  
100  
-50  
-25  
0
25  
50  
75  
100  
Ambient Temperature : Ta (  
)
Ambient Temperature : Ta (  
)
(5) Output Current vs. Input Voltage  
XC6129x55A  
XC6129 (VDF(T)=5.5V)  
VIN=VDF 0.9V (Detect)  
V
RESETB=0.5V (Nch)  
×
25  
VIN=VDF 1.1V (Release)  
×
1.50  
1.35  
1.20  
1.05  
0.90  
0.75  
0.60  
0.45  
0.30  
0.15  
0.00  
20  
15  
10  
5
Ta=-40  
Detect  
Ta=25  
Release  
Ta=85  
0
0.0  
0.5  
1.0  
1.5  
2.0  
2.5  
3.0  
3.5  
4.0  
4.5  
5.0  
5.5  
6.0  
-50  
-25  
0
25  
50  
75  
100  
Input Voltage : VIN (V)  
Ambient Temperature : Ta (  
)
XC6129C15A  
VRESETB=VIN-0.5V (Pch)  
0
-1  
-2  
-3  
-4  
-5  
-6  
Ta=-40  
-7  
Ta=25  
-8  
Ta=85  
-9  
-10  
0.0  
0.5  
1.0  
1.5  
2.0  
2.5  
3.0  
3.5  
4.0  
4.5  
5.0  
5.5  
6.0  
Input Voltage : VIN (V)  
21/30  
XC6129 Series  
TYPICAL PERFORMANCE CHARACTERISTICS (Continued)  
(5) Output Current vs. Input Voltage (Continued)  
(6) Delay Resistance vs. Ambient Temperature  
XC6129x  
VIN=6.0V , VCD/MRB=0V  
(Type : A,B,E,F)  
2.5  
2.4  
2.3  
2.2  
2.1  
2.0  
1.9  
1.8  
1.7  
1.6  
1.5  
-50  
-25  
0
25  
50  
75  
100  
Ambient Temperature : Ta (  
)
(7) Release Delay Time vs. Ambient Temperature  
XC6129x  
XC6129  
VIN=VDF 0.9V , VCD/MRB=6.0V  
VIN=VDF 0.9V  
V
1.1V  
×
×
×
DF  
(Type : C,D,E,F)  
Cd=0.01 F (tDR=13.9ms)  
μ
2.5  
2.4  
2.3  
2.2  
2.1  
2.0  
1.9  
1.8  
1.7  
1.6  
1.5  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
10  
-50  
-25  
0
25  
50  
75  
100  
-50  
-25  
0
25  
50  
75  
100  
Ambient Temperature : Ta (  
)
Ambient Temperature : Ta (  
)
(8) Detect Delay Time vs. Ambient Temperature  
XC6129  
XC6129  
VIN=VDF 0.9V  
V
1.1V  
×
VIN=VDF 1.1V  
V
0.9V  
×
×
×
DF  
DF  
Cd=0.1 F (tDR=139ms)  
μ
Cd=0.01 F (tDR=17.9ms)  
μ
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
10  
200  
190  
180  
170  
160  
150  
140  
130  
120  
110  
100  
-50  
-25  
0
25  
50  
75  
100  
-50  
-25  
0
25  
50  
75  
100  
Ambient Temperature : Ta (  
)
Ambient Temperature : Ta (  
)
22/30  
XC6129  
Series  
TYPICAL PERFORMANCE CHARACTERISTICS (Continued)  
(8) Detect Delay Time vs. Ambient Temperature (Continued)  
(9) Cd pin MRB High Level Voltage vs. Ambient Temperature  
XC6129x  
XC6129  
4.0  
VIN=VDF 1.1V  
V
0.9V  
×
×
DF  
Cd=0.1 F (tDR=179ms)  
μ
200  
190  
180  
170  
160  
150  
140  
130  
120  
110  
100  
VIN=6.0V  
3.0  
2.0  
VIN=4.0V  
1.0  
VIN=2.0V  
0.0  
-50  
-25  
0
25  
50  
75  
100  
-50  
-25  
0
25  
50  
75  
100  
Ambient Temperature : Ta (  
)
Ambient Temperature : Ta (  
)
(10) Cd pin MRB High Level Voltage vs. Input Voltage  
(11) Cd pin MRB Low Level Voltage vs. Ambient Temperature  
XC6129x  
XC6129  
1.5  
4.0  
VIN=6.0V  
3.5  
Ta=-40  
1.2  
Ta=25  
Ta=85  
3.0  
2.5  
2.0  
1.5  
1.0  
0.5  
0.0  
0.9  
VIN=4.0V  
0.6  
0.3  
VIN=2.0V  
0.0  
1.5  
2.0  
2.5  
3.0  
3.5  
4.0  
4.5  
5.0  
5.5  
6.0  
-50  
-25  
0
25  
50  
75  
100  
Input Voltage : VIN (V)  
Ambient Temperature : Ta (  
)
(12) Cd pin MRB Low Level Voltage vs. Input Voltage  
XC6129  
1.50  
1.35  
Ta=-40  
1.20  
1.05  
0.90  
0.75  
0.60  
0.45  
0.30  
0.15  
0.00  
Ta=25  
Ta=85  
1.5  
2.0  
2.5  
3.0  
3.5  
4.0  
4.5  
5.0  
5.5  
6.0  
Input Voltage : VIN (V)  
23/30  
XC6129 Series  
PACKAGING INFORMATION  
unit: mm  
USPN-4 Reference Pattern Layout  
USPN-4 Reference Metal Mask Design  
24/30  
XC6129  
Series  
SSOT-24 Power Dissipation  
Power dissipation data for the SSOT-24 is shown in this page.  
The value of power dissipation varies with the mount board conditions.  
Please use this data as the reference data taken in the following condition.  
40.0  
28.9  
1. Measurement Condition  
Condition: Mount on a board  
Ambient: Natural convection  
Soldering: Lead (Pb) free  
Dimensions 40×40mm (1600mm2 in one side)  
Copper (Cu) traces occupy 50% of the board  
area in top and back faces  
Board:  
Package heat-sink is tied to the copper traces  
Material: Glass Epoxy (FR-4)  
Thickness: 1.6mm  
Through-hole: 4 x 0.8 Diameter  
2.54 1.4  
Evaluation Board (Unit: mm)  
2. Power Dissipation vs. Ambient Temperature  
Ambient Temperature (Tjmax=125)  
Ambient Temperature ()  
Power Dissipation Pd (mW)  
Thermal Resistance (/W)  
25  
85  
500  
200  
200.00  
Pd vs. Ta  
600  
500  
400  
300  
200  
100  
0
25  
45  
65  
85  
105  
125  
Ambient Temperature: Ta ()  
25/30  
XC6129 Series  
USPN-4 Power Dissipation  
Power dissipation data for the USPN-4 is shown in this page.  
The value of power dissipation varies with the mount board conditions.  
Please use this data as the reference data taken in the following condition.  
1. Measurement Condition  
40.0  
28.9  
Condition: Mount on a board  
2.5  
Ambient: Natural convection  
Soldering: Lead (Pb) free  
Board: Dimensions 40×40mm (1600mm2 in one side)  
Copper (Cu) traces occupy 50% of the front and  
50% of the back is 12.5% of total.  
The copper area is divided into four block,  
one block is 12.5% of total.  
The USPN-4 package has for terminals.  
Each terminal connects one copper block in the  
front and one in the back.  
Material: Glass Epoxy (FR-4)  
Thickness: 1.6mm  
Through-hole: 4 x 0.8 Diameter  
Evaluation Board (Unit: mm)  
2. Power Dissipation vs. Ambient Temperature  
Board Mount (Tjmax=125)  
Ambient Temperature ()  
Power Dissipation Pd (mW) Thermal Resistance (/W)  
25  
85  
600  
166.67  
240  
Pd vs. Ta  
700  
600  
500  
400  
300  
200  
100  
0
25  
45  
65  
85  
105  
125  
Ambient Temperature: Ta ()  
26/30  
XC6129  
Series  
MARKING RULE  
SSOT-24  
Indicates mark (1) product series. Indicates the detect voltage range and output type.  
Mark (1)-1 (XC6129C*****-G is underline mark specification.)  
(with underline mark)  
DETECT VOLTAGE  
MARK  
OUTPUT  
TYPE  
PRODUCT SERIES  
RANGE (V)  
0
1
A
B
C
D
E
F
G
J
XC6129C15A**-G to XC6129C55A**-G  
XC6129C15B**-G to XC6129C55B**-G  
XC6129C15C**-G to XC6129C55C**-G  
XC6129C15D**-G to XC6129C55D**-G  
XC6129C15E**-G to XC6129C55E**-G  
XC6129C15F**-G to XC6129C55F**-G  
XC6129C15G**-G to XC6129C55G**-G  
XC6129C15J**-G to XC6129C55J**-G  
XC6129C15L**-G to XC6129C55L**-G  
XC6129C16A**-G to XC6129C54A**-G  
XC6129C16B**-G to XC6129C54B**-G  
XC6129C16C**-G to XC6129C54C**-G  
XC6129C16D**-G to XC6129C54D**-G  
XC6129C16E**-G to XC6129C54E**-G  
XC6129C16F**-G to XC6129C54F**-G  
XC6129C16G**-G to XC6129C54G**-G  
XC6129C16J**-G to XC6129C54J**-G  
XC6129C16L**-G to XC6129C54L**-G  
2
3
4
Odd number  
5
6
8
A
C
D
E
F
H
K
L
L
CMOS  
A
B
C
D
E
F
G
J
Even number  
N
R
L
SSOT-24  
Mark (1)-2 (XC6129N*****-G is overline mark specification.)  
(with overline mark)  
DETECT VOLTAGE  
MARK  
OUTPUT  
TYPE  
PRODUCT SERIES  
RANGE (V)  
0
1
A
B
C
D
E
F
G
J
XC6129N15A**-G to XC6129N55A**-G  
XC6129N15B**-G to XC6129N55B**-G  
XC6129N15C**-G to XC6129N55C**-G  
XC6129N15D**-G to XC6129N55D**-G  
XC6129N15E**-G to XC6129N55E**-G  
XC6129N15F**-G to XC6129N55F**-G  
XC6129N15G**-G to XC6129N55G**-G  
XC6129N15J**-G to XC6129N55J**-G  
XC6129N15L**-G to XC6129N55L**-G  
XC6129N16A**-G to XC6129N54A**-G  
XC6129N16B**-G to XC6129N54B**-G  
XC6129N16C**-G to XC6129N54C**-G  
XC6129N16D**-G to XC6129N54D**-G  
XC6129N16E**-G to XC6129N54E**-G  
XC6129N16F**-G to XC6129N54F**-G  
XC6129N16G**-G to XC6129N54G**-G  
XC6129N16J**-G to XC6129N54J**-G  
XC6129N16L**-G to XC6129N54L**-G  
2
3
4
Odd number  
5
6
8
A
C
D
E
F
H
K
L
L
N-ch  
A
B
C
D
E
F
G
J
Even number  
N
R
L
27/30  
XC6129 Series  
MARKING RULE (Continued)  
represents detect voltage  
DETECT  
MARK  
DETECT  
DETECT  
MARK  
MARK  
VOLTEGE(V)  
VOLTEGE(V)  
VOLTEGE(V)  
A
B
C
D
E
F
1.5  
1.7  
1.9  
2.1  
2.3  
2.5  
2.7  
1.6  
1.8  
2.0  
2.2  
2.4  
2.6  
2.8  
K
L
2.9  
3.1  
3.3  
3.5  
3.7  
3.9  
4.1  
3.0  
3.2  
3.4  
3.6  
3.8  
4.0  
4.2  
T
U
V
X
Y
Z
0
4.3  
4.5  
4.7  
4.9  
5.1  
5.3  
5.5  
4.4  
4.6  
4.8  
5.0  
5.2  
5.4  
-
M
N
P
R
S
H
,represents production lot number  
0109, 0A0Z, 119Z, A1A9, AAAZ, B1ZZ repeated.  
(GIJOQW excluded)  
* No character inversion used.  
28/30  
XC6129  
Series  
MARKING RULE (Continued)  
USPN-4  
represents detect voltage  
PRODUCT SERIES  
MARK  
OUTPUT  
CMOS  
N-ch  
K
L
XC6129C*****-G  
XC6129N*****-G  
represents detect voltage range and product series  
DETECT VOLTAGE  
MARK  
TYPE  
PRODUCT SERIES  
RANGE (V)  
0
1
A
B
C
D
E
F
G
J
XC6129*15A**-G XC6129*55A**-G  
XC6129*15B**-G XC6129*55B**-G  
XC6129*15C**-G XC6129*55C**-G  
XC6129*15D**-G XC6129*55D**-G  
XC6129*15E**-G XC6129*55E**-G  
XC6129*15F**-G XC6129*55F**-G  
XC6129*15G**-G XC6129*55G**-G  
XC6129*15J**-G XC6129*55J**-G  
XC6129*15L**-G XC6129*55L**-G  
XC6129*16A**-G XC6129*54A**-G  
XC6129*16B**-G XC6129*54B**-G  
XC6129*16C**-G XC6129*54C**-G  
XC6129*16D**-G XC6129*54D**-G  
XC6129*16E**-G XC6129*54E**-G  
XC6129*16F**-G XC6129*54F**-G  
XC6129*16G**-G XC6129*54G**-G  
XC6129*16J**-G XC6129*54J**-G  
XC6129*16L**-G XC6129*54L**-G  
2
3
4
Odd number  
5
6
8
A
C
D
E
F
H
K
L
L
A
B
C
D
E
F
G
J
Even number  
N
R
L
represents detect voltage  
DETECT  
MARK  
DETECT  
DETECT  
MARK  
MARK  
VOLTEGE(V)  
VOLTEGE(V)  
VOLTEGE(V)  
A
B
C
D
E
F
1.5  
1.7  
1.9  
2.1  
2.3  
2.5  
2.7  
1.6  
1.8  
2.0  
2.2  
2.4  
2.6  
2.8  
K
L
2.9  
3.1  
3.3  
3.5  
3.7  
3.9  
4.1  
3.0  
3.2  
3.4  
3.6  
3.8  
4.0  
4.2  
T
U
V
X
Y
Z
0
4.3  
4.5  
4.7  
4.9  
5.1  
5.3  
5.5  
4.4  
4.6  
4.8  
5.0  
5.2  
5.4  
-
M
N
P
R
S
H
,represents production lot number  
0109, 0A0Z, 119Z, A1A9, AAAZ, B1ZZ repeated.  
(GIJOQW excluded)  
* No character inversion used.  
29/30  
XC6129 Series  
1. The products and product specifications contained herein are subject to change without  
notice to improve performance characteristics. Consult us, or our representatives  
before use, to confirm that the information in this datasheet is up to date.  
2. We assume no responsibility for any infringement of patents, patent rights, or other  
rights arising from the use of any information and circuitry in this datasheet.  
3. Please ensure suitable shipping controls (including fail-safe designs and aging  
protection) are in force for equipment employing products listed in this datasheet.  
4. The products in this datasheet are not developed, designed, or approved for use with  
such equipment whose failure of malfunction can be reasonably expected to directly  
endanger the life of, or cause significant injury to, the user.  
(e.g. Atomic energy; aerospace; transport; combustion and associated safety  
equipment thereof.)  
5. Please use the products listed in this datasheet within the specified ranges.  
Should you wish to use the products under conditions exceeding the specifications,  
please consult us or our representatives.  
6. We assume no responsibility for damage or loss due to abnormal use.  
7. All rights reserved. No part of this datasheet may be copied or reproduced without the  
prior permission of TOREX SEMICONDUCTOR LTD.  
30/30  
配单直通车
XC6127N31D7R-G产品参数
型号:XC6127N31D7R-G
是否Rohs认证: 符合
生命周期:Active
IHS 制造商:TOREX SEMICONDUCTOR LTD
包装说明:USPN-4
Reach Compliance Code:compliant
ECCN代码:EAR99
HTS代码:8542.39.00.01
风险等级:5.2
其他特性:DETECT VOLTAGE IS 3.1V
可调阈值:NO
模拟集成电路 - 其他类型:POWER SUPPLY SUPPORT CIRCUIT
JESD-30 代码:R-PDSO-N4
JESD-609代码:e4
长度:1.2 mm
湿度敏感等级:1
信道数量:1
功能数量:1
端子数量:4
最高工作温度:85 °C
最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY
封装代码:VSON
封装等效代码:SOLCC4,.05,22
封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, VERY THIN PROFILE
峰值回流温度(摄氏度):260
电源:0.8/5.5 V
认证状态:Not Qualified
座面最大高度:0.4 mm
子类别:Power Management Circuits
最大供电电流 (Isup):0.00235 mA
最大供电电压 (Vsup):6 V
最小供电电压 (Vsup):0.7 V
标称供电电压 (Vsup):1 V
表面贴装:YES
技术:CMOS
温度等级:INDUSTRIAL
端子面层:Nickel/Gold (Ni/Au)
端子形式:NO LEAD
端子节距:0.55 mm
端子位置:DUAL
阈值电压标称:+3.1V
处于峰值回流温度下的最长时间:10
宽度:0.9 mm
Base Number Matches:1
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