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产品型号XC95108-7TQ100C的概述

XC95108-7TQ100C 概述 XC95108-7TQ100C 是由赛灵思（Xilinx）推出的一款基于 CPLD（Complex Programmable Logic Device，复杂可编程逻辑器件）架构的芯片。该芯片是 XC9500 系列中的一员，专为需要高性能和灵活性的设计需求而开发。CPLD 技术使得设计者能够创建复杂数字逻辑功能，同时具备较低的功耗和成本效益。XC95108-7TQ100C 是广泛应用于各种数字电路设计中的一种理想选择。芯片的详细参数 XC95108-7TQ100C 具备如下关键参数： 1. 逻辑单元数量：8064 个逻辑单元 2. 输入/输出引脚数量：100 个 I/O 引脚 3. 克隆类型：7 个时钟 4. 工作电压：3.3V 5. 供电电流：最大 500 mA 6. 烧录技术：支持 ISP（In-System Programming，在线编程）...

产品型号XC95108-7TQ100C的Datasheet PDF文件预览

XC95108 In-System Programmable

CPLD

December 4, 1998 (Version 3.0)

Product Specification

Features

Power Management

•

7.5 ns pin-to-pin logic delays on all pins

to 125 MHz

Power dissipation can be reduced in the XC95108 by con-

figuring macrocells to standard or low-power modes of

operation. Unused macrocells are turned off to minimize

power dissipation.

CNT

•

108 macrocells with 2400 usable gates

Up to 108 user I/O pins

5 V in-system programmable (ISP)

Operating current for each design can be approximated for

specific operating conditions using the following equation:

Endurance of 10,000 program/erase cycles

Program/erase over full commercial voltage and

temperature range

(mA) =

•

Enhanced pin-locking architecture

Flexible 36V18 Function Block

(1.7) + MC (0.9) + MC (0.006 mA/MHz) f

HP LP

Where:

90 product terms drive any or all of 18 macrocells

within Function Block

= Macrocells in high-performance mode

Global and product term clocks, output enables, set

and reset signals

MC = Macrocells in low-power mode

MC = Total number of macrocells used

f = Clock frequency (MHz)

•

Extensive IEEE Std 1149.1 boundary-scan (JTAG)

support

Programmable power reduction mode in each

macrocell

Slew rate control on individual outputs

User programmable ground pin capability

Extended pattern security features for design protection

High-drive 24 mA outputs

Figure 1 shows a typical calculation for the XC95108

device.

•

300

3.3 V or 5 V I/O capability

Advanced CMOS 5V FastFLASH technology

Supports parallel programming of more than one

XC9500 concurrently

Available in 84-pin PLCC, 100-pin PQFP, 100-pin TQFP

and 160-pin PQFP packages

(250)

High Performance

200

•

(180)

(170)

Low Power

Description

The XC95108 is a high-performance CPLD providing

advanced in-system programming and test capabilities for

general purpose logic integration. It is comprised of six

36V18 Function Blocks, providing 2,400 usable gates with

propagation delays of 7.5 ns. See Figure 2 for the architec-

ture overview.

100

Clock Frequency (MHz)

X5898

Figure 1: Typical I_CCvs. Frequency for XC95108

December 4, 1998 (Version 3.0)

XC95108 In-System Programmable CPLD

JTAG

In-System Programming Controller

JTAG Port

Controller

Function

Block 1

I/O

Macrocells

1 to 18

I/O

Function

Block 2

Macrocells

1 to 18

I/O

Blocks

I/O

Function

Block 3

Macrocells

1 to 18

I/O

I/O/GCK

I/O/GSR

I/O/GTS

Function

Block 4

Macrocells

1 to 18

Function

Block 5

Macrocells

1 to 18

Function

Block 6

Macrocells

1 to 18

X5897

Figure 2: XC95108 Architecture

Note: Function Block outputs (indicated by the bold line) drive the I/O Blocks directly

December 4, 1998 (Version 3.0)

XC95108 In-System Programmable CPLD

Absolute Maximum Ratings

Symbol

Parameter

Value

Units

Supply voltage relative to GND

-0.5 to 7.0

DC input voltage relative to GND

-0.5 to V

+ 0.5

Voltage applied to 3-state output with respect to GND

Storage temperature

-0.5 to V

+ 0.5

-65 to +150

°C

STG

SOL

Max soldering temperature (10 s @ 1/16 in = 1.5 mm)

+260

Warning: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are

stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under

Recommended Operating Conditions is not implied. Exposure to Absolute Maximum Rating conditions for extended periods

of time may affect device reliability.

Recommended Operation Conditions

Symbol

Parameter

Min

Max

Units

Supply voltage for internal logic and input buffer

4.75

(4.5)

5.25

(5.5)

CCINT

Supply voltage for output drivers for 5 V operation

Supply voltage for output drivers for 3.3 V operation

Low-level input voltage

4.75 (4.5)

5.25 (5.5)

3.6

CCIO

3.0

0.80

High-level input voltage

2.0

+0.5

CCINT

Output voltage

CCIO

Note: 1. Numbers in parenthesis are for industrial-temperature range versions.

Endurance Characteristics

Symbol

Parameter

Min

Max

Units

Years

Cycles

Data Retention

Program/Erase Cycles

10,000

December 4, 1998 (Version 3.0)

XC95108 In-System Programmable CPLD

DC Characteristics Over Recommended Operating Conditions

Symbol

Parameter

Test Conditions

Min

Max

Units

Output high voltage for 5 V operation

= -4.0 mA

= Min

2.4

Output high voltage for 3.3 V operation

Output low voltage for 5 V operation

Output low voltage for 3.3 V operation

Input leakage current

= -3.2 mA

= Min

2.4

= 24 mA

= Min

0.5

0.4

= 10 mA

= Min

= Max

±10.0

10.0

µA

= GND or V

I/O high-Z leakage current

= Max

= GND or V

I/O capacitance

= GND

f = 1.0 MHz

Operating Supply Current

(low power mode, active)

V = GND, No load

f = 1.0 MHz

100 (Typ)

AC Characteristics

XC95108-7 XC95108-10 XC95108-15 XC95108-20

Min Max Min Max Min Max Min Max

Symbol

Parameter

Units

I/O to output valid

7.5

10.0

15.0

20.0

I/O setup time before GCK

I/O hold time after GCK

4.5

0.0

6.0

0.0

8.0

0.0

10.0

0.0

GCK to output valid

4.5

6.0

8.0

10.0

CNT

16-bit counter frequency

125.0

83.3

0.5

111.1

66.7

2.0

95.2

55.6

4.0

83.3

50.0

4.0

MHz

Multiple FB internal operating frequency

I/O setup time before p-term clock input

I/O hold time after p-term clock input

P-term clock to output valid

GTS to output valid

SYSTEM

PSU

4.0

6.0

8.5

5.5

9.5

10.0

6.0

12.0

11.0

14.0

16.0

18.0

PCO

GTS to output disable

6.0

Product term OE to output enabled

Product term OE to output disabled

GCK pulse width (High or Low)

10.0

POE

POD

WLH

4.0

4.5

5.5

Note: 1. f_CNTis the fastest 16-bit counter frequency available, using the local feedback when applicable.

f_CNTis also the Export Control Maximum flip-flop toggle rate, f_TOG

2. f is the internal operating frequency for general purpose system designs spanning multiple FBs.

SYSTEM

December 4, 1998 (Version 3.0)

XC95108 In-System Programmable CPLD

TEST

Output Type

CCIO

TEST

Device Output

5.0 V

3.3 V

5.0 V

3.3 V

160 Ω

260 Ω

120 Ω

360 Ω

35 pF

X5906

Figure 3: AC Load Circuit

Internal Timing Parameters

XC95108-7 XC95108-10 XC95108-15 XC95108-20

Min Max Min Max Min Max Min Max

Symbol

Parameter

Units

Buffer Delays

Input buffer delay

2.5

1.5

4.5

5.5

2.5

0.0

3.5

2.5

6.0

3.0

0.0

4.5

3.0

6.5

3.0

9.5

GCK buffer delay

GSR buffer delay

GTS buffer delay

Output buffer delay

GCK

GSR

GTS

OUT

7.5

11.0

4.5

16.0

6.5

Output buffer enable/disable delay

0.0

Product Term Control Delays

Product term clock delay

Product term set/reset delay

Product term 3-state delay

3.0

2.0

4.5

3.0

2.5

3.5

2.5

3.0

5.0

2.5

3.0

5.0

PTCK

PTSR

PTTS

Internal Register and Combinatorial delays

Combinatorial logic propagation delay

0.5

1.0

3.0

4.0

PDI

SUI

1.5

3.0

2.5

3.5

4.5

3.5

6.5

0.5

6.5

0.5

7.0

0.5

8.0

0.5

8.0

COI

AOI

RAI

LOGI

Internal logic delay

10.0

2.0

2.5

3.0

t_LOGILP

Internal low power logic delay

10.0

11.0

11.5

Feedback Delays

FastCONNECT matrix feedback delay

Function Block local feeback delay

8.0

4.0

9.5

3.5

11.0

3.5

13.0

5.0

Time Adders

Incremental Product Term Allocator delay

Slew-rate limited delay

1.0

4.0

1.0

4.5

1.0

5.0

1.5

5.5

PTA

SLEW

Note: 3. t_PTAis multiplied by the span of the function as defined in the family data sheet.

December 4, 1998 (Version 3.0)

XC95108 In-System Programmable CPLD

XC95108 I/O Pins

Function

Block

BScan

Order

Function

Block

BScan

Order

Macrocell PC84 PQ100 TQ100 PQ160

Notes

Macrocell PC84 PQ100 TQ100 PQ160

Notes

–

321

318

315

312

309

306

303

300

297

294

291

288

285

282

279

276

273

270

–

213

210

207

204

201

198

195

192

189

186

183

180

177

174

171

168

165

162

–

[1]

–

158 267

154 264

156 261

–

123 159

134 156

135 153

133 150

138 147

139 144

128 141

140 138

142 135

147 132

143 129

144 126

153 123

146 120

148 117

145 114

152 111

155 108

–

258

–

159 255

[1]

–

252

249

246

243

240

237

234

231

228

225

222

219

216

–

[1]

–

Notes: [1] Global control pin

December 4, 1998 (Version 3.0)

XC95108 In-System Programmable CPLD

XC95108 I/O Pins (continued)

Function

BScan

Order

Function

Block

BScan

Order

Macrocell PC84 PQ100 TQ100 PQ160

Block

Notes

Macrocell PC84 PQ100 TQ100 PQ160

Notes

–

101

102

105

102

–

103

104

116

106

108

105

111

113

107

115

117

112

122

124

129

126

114

–

XC95108 Global, JTAG and Power Pins

Pin Type

I/O/GCK1

I/O/GCK2

I/O/GCK3

I/O/GTS1

I/O/GTS2

I/O/GSR

TCK

PC84

PQ100

TQ100

PQ160

159

TDI

136

TDO

TMS

5 V

38,73,78

7,59,100

28,40,53,90

5,57,98

10,46,94,157

CCINT

3.3 V/5 V

22,64

26,38,51,88

1,41,61,81,121,141

20,31,40,51,70,80,99

100,110,120,127,137

160

CCIO

GND

8,16,27,42,49,60

2,23,33,46,64,71,77,86 100,21,31,44,62,69,75,84

–

GND

No connects

3,5,7,32,38,39,48,53,55,6

5,66,67,83,85,93,109,

118,119,125,130,131,

132,149,150,151

December 4, 1998 (Version 3.0)

XC95108 In-System Programmable CPLD

Ordering Information

XC95108 -7 PQ 160 C

Device Type

Speed

Temperature Range

Number of Pins

Package Type

Speed Options

- 20 20 ns pin-to-pin delay

Packaging Options

PC84 84-Pin Plastic Leaded Chip Carrier (PLCC)

PQ100 100-Pin Plastic Quad Flat Pack (PQFP)

TQ100 100-Pin Very Thin Quad Flat Pack (TQFP)

PQ160 160-Pin Plastic Quad Flat Pack (PQFP)

-15 15 ns pin-to-pin delay

-10 10 ns pin-to-pin delay

-7

7 ns pin-to-pin delay

Temperature Options

Commercial 0°C to +70°C

Industrial –40°C to +85°C

Component Availability

Pins

Type

Code

100

160

Plastic

PLCC

Plastic

PQFP

Plastic

TQFP

Plastic

PQFP

PC84

C(I)

PQ100

C(I)

TQ100

C(I)

PQ160

C(I)

–20

–15

–10

–7

C(I)

XC95108

C(I)

C = Commercial = 0° to +70°C I = Industrial = –40° to +85°C

Revision Control

Date

Revision

Update AC Characteristics and Internal Parameters

12/04/98

December 4, 1998 (Version 3.0)

XC95108-7TQ100C相关文章

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XC95108-7TQ100C产品参数

型号:	XC95108-7TQ100C
是否无铅：	含铅
是否Rohs认证：	不符合
生命周期：	Obsolete
零件包装代码：	QFP
包装说明：	TQFP-100
针数：	100
Reach Compliance Code：	unknown
ECCN代码：	EAR99
HTS代码：	8542.39.00.01
风险等级：	5.78
其他特性：	YES
系统内可编程：	YES
JESD-30 代码：	S-PQFP-G100
JESD-609代码：	e0
JTAG BST：	YES
长度：	14 mm
湿度敏感等级：	3
专用输入次数：
I/O 线路数量：	81
宏单元数：	108
端子数量：	100
最高工作温度：	70 °C
最低工作温度：
组织：	0 DEDICATED INPUTS, 81 I/O
输出函数：	MACROCELL
封装主体材料：	PLASTIC/EPOXY
封装代码：	HLFQFP
封装等效代码：	QFP100,.63SQ,20
封装形状：	SQUARE
封装形式：	FLATPACK, HEAT SINK/SLUG, LOW PROFILE, FINE PITCH
峰值回流温度（摄氏度）：	225
电源：	3.3/5,5 V
可编程逻辑类型：	FLASH PLD
传播延迟：	7.5 ns
认证状态：	Not Qualified
座面最大高度：	1.6 mm
子类别：	Programmable Logic Devices
最大供电电压：	5.25 V
最小供电电压：	4.75 V
标称供电电压：	5 V
表面贴装：	YES
技术：	CMOS
温度等级：	COMMERCIAL
端子面层：	Tin/Lead (Sn85Pb15)
端子形式：	GULL WING
端子节距：	0.5 mm
端子位置：	QUAD
处于峰值回流温度下的最长时间：	30
宽度：	14 mm
Base Number Matches：	1

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