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产品型号XC95144-15PQG100C的概述

XC95144-15PQG100C芯片概述 XC95144-15PQG100C是一款来自赛灵思（Xilinx）的复杂可编程逻辑器件（CPLD），广泛应用于数字电路设计与开发中。作为一款CPLD，XC95144系列提供了比传统逻辑器件更高的集成度和更强的灵活性，适合于各种嵌入式应用和快速原型制作。该器件的设计旨在解决复杂逻辑功能的实现，提高设计的效率并降低开发成本。 CPLD是一种集成电路，其中包含多个可编程逻辑块，可以根据设计需求进行配置。XC95144系列具备多个逻辑块，支持灵活的I/O配置和多种电源管理选项，使其能够满足高性能和低功耗设计的需求。XC95144-15PQG100C特别适合于数据通信、工业控制、汽车电子等应用领域。 XC95144-15PQG100C详细参数 - 器件类型: CPLD - 逻辑宏单元数量: 144 - 最大I/O引脚数量: 100 - 最大工作频率: ...

产品型号XC95144-15PQG100C的Datasheet PDF文件预览

XC95144 In-System

Programmable CPLD

DS067 (v5.7) May 28, 2009

Product Specification

Features

Description

•

7.5 ns pin-to-pin logic delays on all pins

The XC95144 is a high-performance CPLD providing

advanced in-system programming and test capabilities for

general purpose logic integration. It is comprised of eight

36V18 Function Blocks, providing 3,200 usable gates with

propagation delays of 7.5 ns. See Figure 2 for the architec-

ture overview.

f_CNTto 111 MHz

144 macrocells with 3,200 usable gates

Up to 133 user I/O pins

5V in-system programmable

Endurance of 10,000 program/erase cycles

Program/erase over full commercial voltage and

temperature range

Power Management

Power dissipation can be reduced in the XC95144 by con-

figuring macrocells to standard or low-power modes of

operation. Unused macrocells are turned off to minimize

power dissipation.

•

Enhanced pin-locking architecture

Flexible 36V18 Function Block (FB)

90 product terms drive any or all of 18 macrocells

within Function Block

Operating current for each design can be approximated for

specific operating conditions using the following equation:

Global and product term clocks, output enables,

set and reset signals

_CC(mA) = MC_HP(1.7) + MC_LP(0.9) + MC (0.006 mA/MHz) f

Where:

MC_HP= Macrocells in high-performance mode

•

Extensive IEEE Std 1149.1 boundary-scan (JTAG)

support

Programmable power reduction mode in each

macrocell

MC_LP= Macrocells in low-power mode

MC = Total number of macrocells used

f = Clock frequency (MHz)

•

Slew rate control on individual outputs

User programmable ground pin capability

Extended pattern security features for design

protection

Figure 1 shows a typical calculation for the XC95144

device.

•

High-drive 24 mA outputs

3.3V or 5V I/O capability

Advanced CMOS 5V FastFLASH technology

Supports parallel programming of more than one

XC9500 concurrently

Available in 100-pin PQFP, 100-pin TQFP, and 160-pin

PQFP packages

600

(480)

•

400

(320)

(300)

200

(160)

100

Clock Frequency (MHz)

DS067_01_110101

Figure 1: Typical I vs. Frequency for XC95144

All other trademarks are the property of their respective owners.

DS067 (v5.7) May 28, 2009

www.xilinx.com

Product Specification

XC95144 In-System Programmable CPLD

JTAG

In-System Programming Controller

JTAG Port

Controller

Function

Block 1

I/O

Macrocells

1 to 18

I/O

Function

Block 2

Macrocells

1 to 18

I/O

Blocks

I/O

Function

Block 3

Macrocells

1 to 18

I/O

I/O/GCK

I/O/GSR

I/O/GTS

Function

Block 4

Macrocells

1 to 18

Function

Block 8

Macrocells

1 to 18

DS067_02_110101

Figure 2: XC95144 Architecture

Function block outputs (indicated by the bold line) drive the I/O blocks directly.

DS067 (v5.7) May 28, 2009

www.xilinx.com

Product Specification

XC95144 In-System Programmable CPLD

Absolute Maximum Ratings

Symbol

Description

Value

Units

Supply voltage relative to GND

–0.5 to 7.0

Input voltage relative to GND

Voltage applied to 3-state output

Storage temperature (ambient)

Junction temperature

–0.5 to V + 0.5

–65 to +150

+150

STG

Notes:

1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress

ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions

is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.

Recommended Operation Conditions

Symbol

Parameter

Commercial T = 0 C to 70 C

Min

4.75

4.5

4.75

4.5

3.0

Max

5.25

5.5

Units

Supply voltage for internal logic

and input buffers

CCINT

Industrial T = –40 C to +85 C

Supply voltage for output drivers

for 5V operation

Commercial T = 0 C to 70 C

5.25

5.5

CCIO

Industrial T = –40 C to +85 C

Supply voltage for output drivers for 3.3V operation

Low-level input voltage

3.6

0.80

High-level input voltage

2.0

+ 0.5

CCINT

Output voltage

CCIO

Quality and Reliability Characteristics

Symbol

Parameter

Min

Max

Units

Data Retention

Program/Erase Cycles (Endurance)

Years

10,000

Cycles

DC Characteristic Over Recommended Operating Conditions

Symbol

Parameter

Test Conditions

Min

Max

Units

Output high voltage for 5V outputs

Output high voltage for 3.3V outputs

Output low voltage for 5V outputs

Output low voltage for 3.3V outputs

Input leakage current

= –4.0 mA, V = Min

2.4

= –3.2 mA, V = Min

2.4

= 24 mA, V = Min

0.5

0.4

= 10 mA, V = Min

= Max

μA

= GND or V

I/O high-Z leakage current

I/O capacitance

= Max

= GND or V

μA

= GND

f = 1.0 MHz

Operating supply current

(low power mode, active)

V = GND, No load

f = 1.0 MHz

160 (Typical)

DS067 (v5.7) May 28, 2009

www.xilinx.com

Product Specification

XC95144 In-System Programmable CPLD

AC Characteristics

XC95144-7

XC95144-10

XC95144-15

Symbol

Parameter

I/O to output valid

Min

Max

7.5

Min

Max

Min

Max

Units

10.0

8.0

15.0

I/O setup time before GCK

I/O hold time after GCK

4.5

6.0

GCK to output valid

4.5

6.0

8.0

(1)

16-bit counter frequency

125.0

111.1

95.2

55.6

4.0

MHz

CNT

(2)

Multiple FB internal operating frequency

I/O setup time before p-term clock input

I/O hold time after p-term clock input

P-term clock output valid

83.3

66.7

SYSTEM

0.5

2.0

PSU

4.0

8.5

5.5

9.5

10.0

6.0

10.0

12.0

11.0

14.0

PCO

GTS to output valid

GTS to output disable

Product term OE to output enabled

Product term OE to output disabled

GCK pulse width (High or Low)

POE

POD

WLH

4.0

7.0

4.5

7.5

5.5

8.0

Asynchronous preset/reset pulse width

(High or Low)

APRPW

Notes:

1. f_CNTis the fastest 16-bit counter frequency available, using the local feedback when applicable.

f_CNTis also the Export Control Maximum flip-flop toggle rate, f_TOG

2. f_SYSTEMis the internal operating frequency for general purpose system designs spanning multiple FBs.

TEST

Output Type

CCIO

TEST

Device Output

5.0V

3.3V

5.0V

3.3V

160Ω

260Ω

120Ω

360Ω

35 pF

DS067_03_110101

Figure 3: AC Load Circuit

DS067 (v5.7) May 28, 2009

www.xilinx.com

Product Specification

XC95144 In-System Programmable CPLD

Internal Timing Parameters

XC95144-7

XC95144-10

XC95144-15

Symbol

Parameter

Min

Max

Min

Max

Min

Max

Units

Buffer Delays

Input buffer delay

2.5

1.5

4.5

5.5

2.5

3.5

2.5

6.0

3.0

4.5

3.0

7.5

11.0

4.5

GCK buffer delay

GCK

GSR

GSR buffer delay

GTS buffer delay

GTS

Output buffer delay

Output buffer enable/disable delay

OUT

Product Term Control Delays

Product term clock delay

Product term set/reset delay

Product term 3-state delay

3.0

2.0

4.5

3.0

2.5

3.5

2.5

3.0

5.0

PTCK

PTSR

PTTS

Internal Register and Combinatorial Delays

Combinatorial logic propagation delay

1.5

3.0

0.5

1.0

3.0

PDI

SUI

2.5

3.5

4.5

Internal logic delay

0.5

6.5

0.5

7.0

0.5

8.0

COI

AOI

7.5

10.0

RAI

2.0

10.0

2.5

11.0

3.0

11.5

LOGI

Internal low power logic delay

LOGILP

Feedback Delays

FastCONNECT feedback delay

8.0

4.0

9.5

3.5

11.0

3.5

Function block local feedback delay

Time Adders

(1)

Incremental product term allocator delay

Slew-rate limited delay

1.0

4.0

1.0

4.5

1.0

5.0

PTA

SLEW

Notes:

1. T_PTAis multiplied by the span of the function as defined in the XC9500 family data sheet.

DS067 (v5.7) May 28, 2009

www.xilinx.com

Product Specification

XC95144 In-System Programmable CPLD

XC95144 I/O Pins

Function Macro-

BScan

TQ100 PQ100 PQ160 Order

Function Macro-

BScan

Block

cell

Block

cell

TQ100 PQ100 PQ160 Order

–

429

426

423

420

417

414

411

408

405

402

399

396

393

390

387

384

–

321

[1]

–

318

–

315

312

309

306

303

–

[1]

–

300

–

297

294

291

288

285

282

279

276

273

270

267

264

261

258

255

252

249

246

243

240

237

234

231

228

225

222

219

216

–

[1]

381

–

378

–

158

375

–

132

140

147

149

142

143

150

144

145

151

146

148

153

152

154

155

156

–

[1]

159

372

–

369

–

366

–

[1]

363

360

–

[1]

–

357

[1]

354

351

–

[1]

–

348

–

345

342

339

336

333

330

327

324

–

Notes:

1. Global control pin.

Macrocell outputs to package pins subject to change, contact factory for latest information. Power, GND, JTAG, and Global Signals are

fixed.

DS067 (v5.7) May 28, 2009

www.xilinx.com

Product Specification

XC95144 In-System Programmable CPLD

XC95144 I/O Pins (Continued)

Function Macro-

BScan

TQ100 PQ100 PQ160 Order

Function Macro-

BScan

Block

cell

Block

cell

TQ100 PQ100 PQ160 Order

–

213

210

207

204

201

198

195

192

189

186

183

180

177

174

171

168

165

162

159

156

153

150

147

144

141

138

135

132

129

126

123

120

117

114

111

108

–

105

102

–

117

119

123

122

124

125

126

129

128

133

134

130

135

138

131

139

–

101

105

107

102

103

109

104

106

112

108

111

114

113

115

118

116

–

Notes:

1. Global control pin.

Macrocell outputs to package pins subject to change, contact factory for latest information. Power, GND, JTAG, and Global Signals are

fixed.

DS067 (v5.7) May 28, 2009

www.xilinx.com

Product Specification

XC95144 In-System Programmable CPLD

XC95144 Global, JTAG, and Power Pins

Pin Type

I/O/GCK1

I/O/GCK2

I/O/GCK3

I/O/GTS1

I/O/GTS2

I/O/GTS3

I/O/GTS4

I/O/GSR

TCK

TQ100

PQ100

PQ160

159

TDI

TDO

136

TMS

_CCINT5V

5, 57, 98

26, 38, 51, 88

7, 59, 100

28, 40, 53, 90

10, 46, 94, 157

1, 41, 61, 81, 121, 141

_CCIO3.3V/5V

GND

100, 21, 31, 44, 62, 69, 75, 2, 23, 33, 46, 64, 71, 77, 86

20, 31, 40, 51, 70, 80, 99,

100, 110, 120, 127, 137, 160

No Connects

–

DS067 (v5.7) May 28, 2009

www.xilinx.com

Product Specification

XC95144 In-System Programmable CPLD

Device Part Marking and Ordering Combination Information

Device Type

Package

XC95xxx

TQ144

This line not

related to device

part number

Speed

Operating Range

Sample package with part marking.

Speed

(pin-to-pin

delay)

Device Ordering and

Part Marking Number

Pkg.

Symbol

No. of

Pins

Operating

Range

(1)

Package Type

XC95144-7PQ100C

XC95144-7PQG100C

XC95144-7TQ100C

XC95144-7TQG100C

XC95144-7PQ160C

XC95144-7PQG160C

XC95144-10PQ100C

XC95144-10PQG100C

XC95144-10TQ100C

XC95144-10TQG100C

XC95144-10PQ160C

XC95144-10PQG160C

XC95144-10PQ100I

XC95144-10PQG100I

XC95144-10TQ100I

XC95144-10TQG100I

XC95144-10PQ160I

XC95144-10PQG160I

XC95144-15PQ100C

XC95144-15PQG100C

XC95144-15TQ100C

XC95144-15TQG100C

XC95144-15PQ160C

XC95144-15PQG160C

XC95144-15PQ100I

XC95144-15PQG100I

XC95144-15TQ100I

XC95144-15TQG100I

7.5 ns

10 ns

15 ns

PQ100 100-pin

PQG100 100-pin

TQ100 100-pin

TQG100 100-pin

PQ160 160-pin

PQG160 160-pin

PQ100 100-pin

PQG100 100-pin

TQ100 100-pin

TQG100 100-pin

PQ160 160-pin

PQG160 160-pin

PQ100 100-pin

PQG100 100-pin

TQ100 100-pin

TQG100 100-pin

PQ160 160-pin

PQG160 160-pin

PQ100 100-pin

PQG100 100-pin

TQ100 100-pin

TQG100 100-pin

PQ160 160-pin

PQG160 160-pin

PQ100 100-pin

PQG100 100-pin

TQ100 100-pin

TQG100 100-pin

Plastic Quad Flat Pack (PQFP)

Plastic Quad Flat Pack (PQFP); Pb-Free

Thin Quad Flat Pack (TQFP)

Thin Quad Flat Pack (TQFP); Pb-Free

Plastic Quad Flat Pack (PQFP)

Plastic Quad Flat Pack (PQFP); Pb-Free

Plastic Quad Flat Pack (PQFP)

Plastic Quad Flat Pack (PQFP); Pb-Free

Thin Quad Flat Pack (TQFP)

Thin Quad Flat Pack (TQFP); Pb-Free

Plastic Quad Flat Pack (PQFP)

Plastic Quad Flat Pack (PQFP); Pb-Free

Plastic Quad Flat Pack (PQFP)

Plastic Quad Flat Pack (PQFP); Pb-Free

Thin Quad Flat Pack (TQFP)

Thin Quad Flat Pack (TQFP); Pb-Free

Plastic Quad Flat Pack (PQFP)

Plastic Quad Flat Pack (PQFP); Pb-Free

Plastic Quad Flat Pack (PQFP)

Plastic Quad Flat Pack (PQFP); Pb-Free

Thin Quad Flat Pack (TQFP)

Thin Quad Flat Pack (TQFP); Pb-Free

Plastic Quad Flat Pack (PQFP)

Plastic Quad Flat Pack (PQFP); Pb-Free

Plastic Quad Flat Pack (PQFP)

Plastic Quad Flat Pack (PQFP); Pb-Free

Thin Quad Flat Pack (TQFP)

Thin Quad Flat Pack (TQFP); Pb-Free

DS067 (v5.7) May 28, 2009

www.xilinx.com

Product Specification

XC95144 In-System Programmable CPLD

Speed

(pin-to-pin

delay)

Device Ordering and

Part Marking Number

Pkg.

Symbol

No. of

Pins

Operating

Range

(1)

Package Type

XC95144-15PQ160I

XC95144-15PQG160I

Notes:

15 ns

PQ160 160-pin

PQG160 160-pin

Plastic Quad Flat Pack (PQFP)

Plastic Quad Flat Pack (PQFP); Pb-Free

1. C = Commercial: T_A= 0° to +70°C; I = Industrial: T_A= –40° to +85°C

Additional Information

XC9500 data sheets and application notes.

Packages

Revision History

The following table shows the revision history for this document.

Date

Version

4.0

Revision

Update AC characteristics and internal parameters.

Updated format.

12/04/98

06/18/03

08/21/03

11/06/03

02/16/04

5.0

5.1

Updated Package Device Marking Pin 1 orientation.

Update pin count on PQ160 packages.

5.2

5.3

Correct GTS pin information by removing rows on GTS3 GTS4 from table on page 8. Add

links to additional information.

04/15/05

01/03/06

04/03/06

05/28/09

5.4

5.5

5.6

5.7

Added asynchronous preset/reset pulse width specification (T

APRPW

Added GTS3 and GTS4 pins to table on page 8.

Added Warranty Disclaimer. Added Pb-Free package ordering information.

Removed table note reference from Function Block 2, Macrocell 3 in XC95144 I/O Pins.

Notice of Disclaimer

THE XILINX HARDWARE FPGA AND CPLD DEVICES REFERRED TO HEREIN (“PRODUCTS”) ARE SUBJECT TO THE

TERMS AND CONDITIONS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED AT

http://www.xilinx.com/warranty.htm. THIS LIMITED WARRANTY DOES NOT EXTEND TO ANY USE OF PRODUCTS IN

AN APPLICATION OR ENVIRONMENT THAT IS NOT WITHIN THE SPECIFICATIONS STATED IN THE XILINX DATA

SHEET. ALL SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE. PRODUCTS ARE NOT DESIGNED OR

INTENDED TO BE FAIL-SAFE OR FOR USE IN ANY APPLICATION REQUIRING FAIL-SAFE PERFORMANCE, SUCH AS

LIFE-SUPPORT OR SAFETY DEVICES OR SYSTEMS, OR ANY OTHER APPLICATION THAT INVOKES THE

POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL

APPLICATIONS”). USE OF PRODUCTS IN CRITICAL APPLICATIONS IS AT THE SOLE RISK OF CUSTOMER, SUBJECT

TO APPLICABLE LAWS AND REGULATIONS.

DS067 (v5.7) May 28, 2009

www.xilinx.com

Product Specification

XC95144-15PQG100C相关文章

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XC95144-15PQG100C产品参数

型号:	XC95144-15PQG100C
是否无铅：	不含铅
是否Rohs认证：	符合
生命周期：	Obsolete
IHS 制造商：	XILINX INC
零件包装代码：	QFP
包装说明：	LEAD FREE, PLASTIC, QFP-100
针数：	100
Reach Compliance Code：	unknown
ECCN代码：	EAR99
HTS代码：	8542.39.00.01
风险等级：	5.62
其他特性：	YES
最大时钟频率：	55.6 MHz
系统内可编程：	YES
JESD-30 代码：	R-PQFP-G100
JESD-609代码：	e3
JTAG BST：	YES
长度：	20 mm
湿度敏感等级：	3
专用输入次数：
I/O 线路数量：	81
宏单元数：	144
端子数量：	100
最高工作温度：	70 °C
最低工作温度：
组织：	0 DEDICATED INPUTS, 81 I/O
输出函数：	MACROCELL
封装主体材料：	PLASTIC/EPOXY
封装代码：	QFP
封装等效代码：	QFP100,.7X.9
封装形状：	RECTANGULAR
封装形式：	FLATPACK
峰值回流温度（摄氏度）：	245
电源：	3.3/5,5 V
可编程逻辑类型：	FLASH PLD
传播延迟：	15 ns
认证状态：	Not Qualified
座面最大高度：	3.4 mm
子类别：	Programmable Logic Devices
最大供电电压：	5.25 V
最小供电电压：	4.75 V
标称供电电压：	5 V
表面贴装：	YES
技术：	CMOS
温度等级：	COMMERCIAL
端子面层：	Matte Tin (Sn)
端子形式：	GULL WING
端子节距：	0.65 mm
端子位置：	QUAD
处于峰值回流温度下的最长时间：	30
宽度：	14 mm
Base Number Matches：	1

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