0
R
XC95144XL High Performance
CPLD
0
5
DS056 (v1.5) August 21, 2003
Preliminary Product Specification
Features
Power Estimation
Power dissipation in CPLDs can vary substantially depend-
ing on the system frequency, design application and output
loading. To help reduce power dissipation, each macrocell
in a XC9500XL device may be configured for low-power
mode (from the default high-performance mode). In addi-
tion, unused product-terms and macrocells are automati-
cally deactivated by the software to further conserve power.
•
•
•
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5 ns pin-to-pin logic delays
System frequency up to 178 MHz
144 macrocells with 3,200 usable gates
Available in small footprint packages
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100-pin TQFP (81 user I/O pins)
144-pin TQFP (117 user I/O pins)
144-CSP (117 user I/O pins)
For a general estimate of I , the following equation may be
•
•
Optimized for high-performance 3.3V systems
CC
used:
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Low power operation
5V tolerant I/O pins accept 5V, 3.3V, and 2.5V
signals
I
(mA) = MC (0.175*PT + 0.345) + MC (0.052*PT
CC
HS HS LP LP
+ 0.272) + 0.04 * MC
(MC +MC )* f
TOG
HS
LP
where:
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3.3V or 2.5V output capability
Advanced 0.35 micron feature size CMOS
Fast FLASH™ technology
MC = # macrocells in high-speed configuration
HS
PT = average number of high-speed product terms
HS
Advanced system features
per macrocell
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In-system programmable
MC = # macrocells in low power configuration
LP
Superior pin-locking and routability with
Fast CONNECT™ II switch matrix
Extra wide 54-input Function Blocks
Up to 90 product-terms per macrocell with
individual product-term allocation
Local clock inversion with three global and one
product-term clocks
Individual output enable per output pin with local
inversion
Input hysteresis on all user and boundary-scan pin
inputs
PT = average number of low power product terms per
LP
macrocell
f = maximum clock frequency
MCTOG = average % of flip-flops toggling per clock
(~12%)
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-
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This calculation was derived from laboratory measurements
of an XC9500XL part filled with 16-bit counters and allowing
a single output (the LSB) to be enabled. The actual I
value varies with the design application and should be veri-
fied during normal system operation. Figure 1 shows the
above estimation in a graphical form. For a more detailed
discussion of power consumption in this device, see Xilinx
application note XAPP114, “Understanding XC9500XL
CPLD Power.”
CC
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Bus-hold circuitry on all user pin inputs
Full IEEE Standard 1149.1 boundary-scan (JTAG)
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•
•
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Fast concurrent programming
Slew rate control on individual outputs
Enhanced data security features
Excellent quality and reliability
250
178 MHz
200
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Endurance exceeding 10,000 program/erase
cycles
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20 year data retention
ESD protection exceeding 2,000V
150
104 MHz
•
Pin-compatible with 5V-core XC95144 device in the
100-pin TQFP package
100
50
0
Description
The XC95144XL is a 3.3V CPLD targeted for high-perfor-
mance, low-voltage applications in leading-edge communi-
cations and computing systems. It is comprised of eight
54V18 Function Blocks, providing 3,200 usable gates with
propagation delays of 5 ns. See Figure 2 for architecture
overview.
100
Clock Frequency (MHz)
200
50
150
DS056_01_121501
Figure 1: Typical I vs. Frequency for XC95144XL
CC
© 2003 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS056 (v1.5) August 21, 2003
www.xilinx.com
1
Preliminary Product Specification
1-800-255-7778