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产品型号XC9536-7PC44I的概述

XC9536-7PC44I芯片概述 XC9536-7PC44I是一款由赛灵思（Xilinx）公司研发的复杂可编程逻辑器件（CPLD），其主要针对高性能、低功耗的应用场景。作为一款可编程逻辑器件，XC9536-7PC44I不仅提供了灵活的逻辑功能，还允许用户在设计时根据需求灵活配置。这种芯片深受设计师青睐，广泛应用于通信、消费电子、工业控制、汽车电子等多个领域。 XC9536-7PC44I属于XC9500系列，特点是具备高达36个逻辑单元，支持大量复杂的逻辑运算，满足现代电子产品对高集成度和高性能的需求。此外，该芯片在逻辑单元的数量、组合逻辑的复杂度、与外部设备的接口能力等方面都表现出色，能够有效提升设计效率，加快产品的上市时间。 XC9536-7PC44I详细参数 XC9536-7PC44I的技术参数涵盖了多个方面，具体如下： 1. 逻辑单元（LE）数量：36个逻辑单元。 2. 输入输...

产品型号XC9536-7PC44I的Datasheet PDF文件预览

XC9536 In-System Programmable

CPLD

December 4, 1998 (Version 5.0)

Product Specification

Features

Power Management

•

5 ns pin-to-pin logic delays on all pins

to 100 MHz

Power dissipation can be reduced in the XC9536 by config-

uring macrocells to standard or low-power modes of opera-

tion. Unused macrocells are turned off to minimize power

dissipation.

CNT

•

36 macrocells with 800 usable gates

Up to 34 user I/O pins

5 V in-system programmable (ISP)

Operating current for each design can be approximated for

specific operating conditions using the following equation:

Endurance of 10,000 program/erase cycles

Program/erase over full commercial voltage and

temperature range

(mA) =

•

Enhanced pin-locking architecture

Flexible 36V18 Function Block

(1.7) + MC (0.9) + MC (0.006 mA/MHz) f

HP LP

Where:

90 product terms drive any or all of 18 macrocells

within Function Block

= Macrocells in high-performance mode

Global and product term clocks, output enables, set

and reset signals

MC = Macrocells in low-power mode

MC = Total number of macrocells used

f = Clock frequency (MHz)

•

Extensive IEEE Std 1149.1 boundary-scan (JTAG)

support

Programmable power reduction mode in each

macrocell

Figure 1 shows a typical calculation for the XC9536 device.

•

Slew rate control on individual outputs

User programmable ground pin capability

Extended pattern security features for design protection

High-drive 24 mA outputs

(83)

3.3 V or 5 V I/O capability

Advanced CMOS 5V FastFLASH technology

Supports parallel programming of more than one

XC9500 concurrently

(50)

•

Available in 44-pin PLCC, 44-pin VQFP, and 48-pin

CSP packages

(30)

Description

The XC9536 is a high-performance CPLD providing

advanced in-system programming and test capabilities for

general purpose logic integration. It is comprised of two

36V18 Function Blocks, providing 800 usable gates with

propagation delays of 5 ns. See Figure 2 for the architec-

ture overview.

100

Clock Frequency (MHz)

X5920

Figure 1: Typical I

vs. Frequency For XC9536

December 4, 1998 (Version 5.0)

XC9536 In-System Programmable CPLD

JTAG

In-System Programming Controller

JTAG Port

Controller

Function

Block 1

I/O

Macrocells

1 to 18

I/O

Function

Block 2

Macrocells

1 to 18

I/O

Blocks

I/O

I/O/GCK

I/O/GSR

I/O/GTS

X5919

Figure 2: XC9536 Architecture

Note: Function Block outputs (indicated by the bold line) drive the I/O Blocks directly

December 4, 1998 (Version 5.0)

XC9536 In-System Programmable CPLD

Absolute Maximum Ratings

Symbol

Parameter

Value

Units

Supply voltage relative to GND

-0.5 to 7.0

DC input voltage relative to GND

-0.5 to V

+ 0.5

Voltage applied to 3-state output with respect to GND

Storage temperature

-0.5 to V

+ 0.5

-65 to +150

+260

°C

STG

SOL

Max soldering temperature (10 s @ 1/16 in = 1.5 mm)

Warning: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are

stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under

Recommended Operating Conditions is not implied. Exposure to Absolute Maximum Rating conditions for extended periods

of time may affect device reliability.

Recommended Operating Conditions

Symbol

CCINT

Parameter

Min

Max

Units

Supply voltage for internal logic and input buffer

4.75

(4.5)

5.25

(5.5)

Supply voltage for output drivers for 5 V operation

Supply voltage for output drivers for 3.3 V operation

Low-level input voltage

4.75 (4.5)

5.25 (5.5)

3.6

CCIO

3.0

0.80

High-level input voltage

2.0

+0.5

CCINT

Output voltage

CCIO

Note 1. Numbers in parenthesis are for industrial-temperature range versions.

Endurance Characteristics

Symbol

Parameter

Min

Max

Units

Data Retention

Program/Erase Cycles

Years

10,000

Cycles

December 4, 1998 (Version 5.0)

XC9536 In-System Programmable CPLD

DC Characteristics Over Recommended Operating Conditions

Symbol

Parameter

Test Conditions

Min

Max

Units

Output high voltage for 5 V operation

= -4.0 mA

= Min

2.4

Output high voltage for 3.3 V operation I

= -3.2 mA

= Min

2.4

Output low voltage for 5 V operation

Output low voltage for 3.3 V operation

Input leakage current

= 24 mA

= Min

0.5

0.4

= 10 mA

= Min

= Max

±10.0

10.0

µA

= GND or V

I/O high-Z leakage current

I/O capacitance

= Max

= GND or V

= GND

f = 1.0 MHz

Operating Supply Current

(low power mode, active)

V = GND, No load

f = 1.0 MHz

30 (Typ)

AC Characteristics

XC9536-5 XC9536-6 XC9536-7 XC9536-10 XC9536-15

Min Max Min Max Min Max Min Max Min Max

Symbol

Parameter

Units

I/O to output valid

5.0

6.0

7.5

10.0

15.0 ns

I/O setup time before GCK

I/O hold time after GCK

GCK to output valid

3.5

0.0

3.5

0.0

4.5

0.0

6.0

0.0

8.0

0.0

4.0

4.5

6.0

8.0

16-bit counter frequency

100.0

0.5

83.3

0.5

66.7

2.0

55.6

4.0

MHz

CNT

Multiple FB internal operating frequency 100.0

I/O setup time before p-term clock input 0.5

SYSTEM

PSU

I/O hold time after p-term clock input

P-term clock to output valid

GTS to output valid

3.0

4.0

7.0

5.0

9.0

7.0

5.0

9.0

8.5

5.5

9.5

10.0

6.0

12.0 ns

11.0 ns

14.0 ns

PCO

GTS to output disable

6.0

Product term OE to output enabled

Product term OE to output disabled

GCK pulse width (High or Low)

10.0

POE

POD

WLH

4.0

4.5

5.5

Note: 1. f_CNTis the fastest 16-bit counter frequency available.

f_CNTis also the Export Control Maximum flip-flop toggle rate, f_TOG

2. f_SYSTEMis the internal operating frequency for general purpose system designs spanning multiple FBs.

December 4, 1998 (Version 5.0)

XC9536 In-System Programmable CPLD

TEST

Output Type

CCIO

TEST

Device Output

5.0 V

3.3 V

5.0 V

3.3 V

160 Ω

260 Ω

120 Ω

360 Ω

35 pF

X5906

Figure 3: AC Load Circuit

Internal Timing Parameters

XC9536-5 XC9536-6 XC9536-7 XC9536-10 XC9536-15

Min Max Min Max Min Max Min Max Min Max

Symbol

Parameter

Units

Buffer Delays

Input buffer delay

GCK buffer delay

1.5

4.0

5.0

2.0

0.0

1.5

4.0

5.0

2.0

0.0

2.5

1.5

4.5

5.5

2.5

0.0

3.5

2.5

6.0

3.0

0.0

4.5

3.0

7.5

GCK

GSR

GTS

OUT

GSR buffer delay

GTS buffer delay

11.0 ns

Output buffer delay

4.5

0.0

Output buffer enable/disable delay

Product Term Control Delays

Product term clock delay

Product term set/reset delay

Product term 3-state delay

3.0

1.0

5.5

3.0

1.0

5.5

3.0

2.0

4.5

3.0

2.5

3.5

2.5

3.0

5.0

PTCK

PTSR

PTTS

Internal Register and Combinatorial delays

Combinatorial logic propagation delay

0.5

1.5

0.5

1.0

3.0

PDI

SUI

2.5

1.0

2.5

1.0

1.5

3.0

2.5

3.5

4.5

0.5

6.0

0.5

6.0

0.5

6.5

0.5

7.0

0.5

8.0

COI

AOI

RAI

LOGI

Internal logic delay

5.0

7.5

10.0

1.0

9.0

1.0

9.0

2.0

2.5

3.0

t_LOGILPInternal low power logic delay

10.0

11.0

11.5 ns

Feedback Delays

FastCONNECT matrix feeback delay

6.0

8.0

9.5

11.0 ns

Time Adders

Incremental Product Term Allocator delay

Slew-rate limited delay

0.8

3.5

0.8

3.5

1.0

4.0

1.0

4.5

1.0

5.0

PTA

SLEW

Note: 3. t_PTAis multiplied by the span of the function as defined in the family data sheet.

December 4, 1998 (Version 5.0)

XC9536 In-System Programmable CPLD

XC9536 I/O Pins

Function

Block

BScan

Order

Function

Block

BScan

Order

Macrocell PC44 VQ44 CS48

Notes

Macrocell PC44 VQ44 CS48

Notes

105

102

[1]

–

Note: [1] Global control pin

XC9536 Global, JTAG and Power Pins

Pin Type

I/O/GCK1

I/O/GCK2

I/O/GCK3

I/O/GTS1

I/O/GTS2

I/O/GSR

TCK

PC44

VQ44

CS48

TDI

TDO

TMS

5 V

21,41

15,35

C1,F7

CCINT

3.3 V/5 V

CCIO

GND

23,10,31

—

17,4,25

—

A5, D1, F3

No Connects

C4, D3, D4, E4

December 4, 1998 (Version 5.0)

XC9536 In-System Programmable CPLD

Ordering Information

XC9536 -5 PC 44 C

Device Type

Temperature Range

Number of Pins

Package Type

Speed

Speed Options

Packaging Options

-15

-10

-7

-6

-5

15 ns pin-to-pin delay

10 ns pin-to-pin delay

7.5 ns pin-to-pin delay

6 ns pin-to-pin delay

5 ns pin-to-pindelay

PC44 44-Pin Plastic Leaded Chip Carrier (PLCC)

VQ44 44-Pin Thin Quad Pack (VQFP)

CS48 48-Pin Chip Scale Package (CSP)

Temperature Options

C = Commercial (0°C to +70°C)

I = Industrial (–40°C to +85°C)

Component Availability

Pins

Type

Code

Plastic

PLCC

Plastic

VQFP

Plastic

CSP

PC44

C,I

VQ44

C,I

CS48

–15

–10

–7

XC9536

–6

–5

C = Commercial (0°C to +70°C), I = Industrial (–40°C to +85°C)

Revision Control

Date

Reason

6/3/98

11/2/98

12/04/98

Revise datasheet to reflect new CSP package pinouts & ordering code.

Revise datasheet to reflect new AC characteristics and Internal Timing Parameters.

Revise datasheet to remove PCI compliancy statement and remove t_LF

December 4, 1998 (Version 5.0)

XC9536-7PC44I相关文章

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XC9536-7PC44I产品参数

型号:	XC9536-7PC44I
是否无铅：	含铅
是否Rohs认证：	不符合
生命周期：	Obsolete
IHS 制造商：	XILINX INC
零件包装代码：	LCC
包装说明：	PLASTIC, LCC-44
针数：	44
Reach Compliance Code：	not_compliant
ECCN代码：	EAR99
HTS代码：	8542.39.00.01
风险等级：	5.67
Is Samacsys：	N
其他特性：	YES
最大时钟频率：	83.3 MHz
系统内可编程：	YES
JESD-30 代码：	S-PQCC-J44
JESD-609代码：	e0
JTAG BST：	YES
长度：	16.5862 mm
湿度敏感等级：	3
专用输入次数：
I/O 线路数量：	34
宏单元数：	36
端子数量：	44
最高工作温度：	85 °C
最低工作温度：	-40 °C
组织：	0 DEDICATED INPUTS, 34 I/O
输出函数：	MACROCELL
封装主体材料：	PLASTIC/EPOXY
封装代码：	QCCJ
封装等效代码：	LDCC44,.7SQ
封装形状：	SQUARE
封装形式：	CHIP CARRIER
峰值回流温度（摄氏度）：	225
电源：	3.3/5,5 V
可编程逻辑类型：	FLASH PLD
传播延迟：	7.5 ns
认证状态：	Not Qualified
座面最大高度：	4.572 mm
子类别：	Programmable Logic Devices
最大供电电压：	5.5 V
最小供电电压：	4.5 V
标称供电电压：	5 V
表面贴装：	YES
技术：	CMOS
温度等级：	INDUSTRIAL
端子面层：	Tin/Lead (Sn85Pb15)
端子形式：	J BEND
端子节距：	1.27 mm
端子位置：	QUAD
处于峰值回流温度下的最长时间：	30
宽度：	16.5862 mm
Base Number Matches：	1

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