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产品型号XC9536XL-10VQ44I的概述

XC9536XL-10VQ44I芯片概述 XC9536XL-10VQ44I是由赛灵思（Xilinx）公司制造的一款可编程逻辑器件，属于其CoolRunner系列。该器件广泛应用于数字逻辑设计和电路实现。XC9536XL是该系列中快速、高效和低功耗的可编程设备，具有高度的灵活性和可重构性。它在许多高效的嵌入式系统和数字电路应用中取得了显著成绩，尤其是在需要进行快速布线和时序优化的情况下。 XC9536XL-10VQ44I的结构设计使其能够在较低的电源电压下进行操作，并具备出色的温度特性。这使得它成为了汽车、消费者电子、通信设备以及工业控制等多个领域的理想选择。该芯片内置的逻辑单元数量和I/O引脚数量为设计者提供了充足的资源，不论是简单的逻辑控制还是复杂的信号处理任务，XC9536XL都能够顺利实现。芯片详细参数 XC9536XL-10VQ44I的详细参数如下： - 逻辑单元数量：36 ...

产品型号XC9536XL-10VQ44I的Datasheet PDF文件预览

XC9536XL High Performance

CPLD

DS058 (v1.2) June 25, 2001

Preliminary Product Specification

cations and computing systems. It is comprised of two

54V18 Function Blocks, providing 800 usable gates with

propagation delays of 5 ns. See Figure 2 for architecture

overview.

Features

•

5 ns pin-to-pin logic delays

System frequency up to 178 MHz

36 macrocells with 800 usable gates

Available in small footprint packages

Power Estimation

44-pin PLCC (34 user I/O pins)

44-pin VQFP (34 user I/O pins)

48-pin CSP (36 user I/O pins)

64-pin VQFP (36 user I/O pins)

Power dissipation in CPLDs can vary substantially depend•

ing on the system frequency, design application and output

loading. To help reduce power dissipation, each macrocell

in a XC9500XL device may be configured for low-power

mode (from the default high-performance mode). In addi•

tion, unused product-terms and macrocells are automati•

cally deactivated by the software to further conserve power.

•

Optimized for high-performance 3.3V systems

Low power operation

5V tolerant I/O pins accept 5 V, 3.3V, and 2.5V

signals

For a general estimate of I , the following equation may be

3.3V or 2.5V output capability

Advanced 0.35 micron feature size CMOS

FastFLASH™ technology

used:

(mA) = MC (0.5) + MC (0.3) + MC(0.0045 mA/MHz) f

HP LP

Where:

MC = Macrocells in high-performance (default) mode

Advanced system features

In-system programmable

Superior pin-locking and routability with

FastCONNECT II™ switch matrix

Extra wide 54-input Function Blocks

Up to 90 product-terms per macrocell with

individual product-term allocation

Local clock inversion with three global and one

product-term clocks

MC = Macrocells in low-power mode

MC = Total number of macrocells used

f = Clock frequency (MHz)

This calculation is based on typical operating conditions

using a pattern of 16-bit up/down counters in each Function

Block with no output loading. The actual I

value varies

Individual output enable per output pin

Input hysteresis on all user and boundary-scan pin

inputs

with the design application and should be verified during

normal system operation.

Figure 1 shows the above estimation in a graphical form.

Bus-hold circuitry on all user pin inputs

Full IEEE Standard 1149.1 boundary-scan (JTAG)

•

Fast concurrent programming

178 MHz

Slew rate control on individual outputs

Enhanced data security features

Excellent quality and reliability

Endurance exceeding 10,000 program/erase

cycles

125 MHz

20 year data retention

ESD protection exceeding 2,000V

•

Pin-compatible with 5V-core XC9536 device in the

44-pin PLCC package and the 48-pin CSP package

Description

100

200

250

150

The XC9536XL is a 3.3V CPLD targeted for high-perfor•

mance, low-voltage applications in leading-edge communi•

Clock Frequency (MHz)

DS058_01_061101

Figure 1: Typical I vs. Frequency for XC9536XL

All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.

DS058 (v1.2) June 25, 2001

www.xilinx.com

Preliminary Product Specification

1-800-255-7778

XC9536XL High Performance CPLD

JTAG

In-System Programming Controller

JTAG Port

Controller

Function

Block 1

I/O

Macrocells

1 to 18

I/O

Function

Block 2

Macrocells

1 to 18

I/O

Blocks

I/O

I/O/GCK

I/O/GSR

I/O/GTS

DS058_02_081500

Figure 2: XC9536XL Architecture

Function Block outputs (indicated by the bold line) drive the I/O Blocks directly.

www.xilinx.com

DS058 (v1.2) June 25, 2001

1-800-255-7778

Preliminary Product Specification

XC9536XL High Performance CPLD

Absolute Maximum Ratings

Symbol

Description

Value

–0.5 to 4.0

–0.5 to 5.5

–65 to +150

+260

Units

Supply voltage relative to GND

(1)

Input voltage relative to GND

(1)

Voltage applied to 3-state output

Storage temperature (ambient)

STG

Maximum soldering temperature (10s @ 1/16 in. = 1.5 mm)

Junction temperature

SOL

+150

Notes:

1. Maximum DC undershoot below GND must be limited to either 0.5V or 10 mA, whichever is easier to achieve. During transitions, the

device pins may undershoot to –2.0 V or overshoot to +7.0V, provided this over- or undershoot lasts less than 10 ns and with the

forcing current being limited to 200 mA.

2. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress

ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions

is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.

Recommended Operation Conditions

Symbol

Parameter

Min

3.0

2.3

Max

3.6

Units

Supply voltage for internal logic

and input buffers

Commercial T = 0 C to 70 C

CCINT

Industrial T = –40 C to +85 C

3.6

Supply voltage for output drivers for 3.3V operation

Supply voltage for output drivers for 2.5V operation

Low-level input voltage

3.6

CCIO

2.7

0.80

5.5

High-level input voltage

2.0

Output voltage

CCIO

Quality and Reliability Characteristics

Symbol

Parameter

Min

Max

Units

Data Retention

Years

Cycles

Volts

Program/Erase Cycles (Endurance)

Electrostatic Discharge (ESD)

10,000

2,000

ESD

DC Characteristic Over Recommended Operating Conditions

Symbol

Parameter

Output high voltage for 3.3V outputs

Output high voltage for 2.5V outputs

Output low voltage for 3.3V outputs

Output low voltage for 2.5V outputs

Input leakage current

Test Conditions

Min

2.4

90%

Max

Units

= –4.0 mA

= –500 µA

= 8.0 mA

= 500 µA

CCIO

0.4

= Max

±10

µA

= GND or V

I/O high-Z leakage current

I/O capacitance

= Max

±10

µA

= GND or V

= GND

f = 1.0 MHz

Operating supply current

(low power mode, active)

V = GND, No load

f = 1.0 MHz

10 (Typical)

DS058 (v1.2) June 25, 2001

Preliminary Product Specification

www.xilinx.com

1-800-255-7778

XC9536XL High Performance CPLD

AC Characteristics

XC9536XL-5

XC9536XL-7

XC9536XL-10

Symbol

Parameter

Min

Max

5.0

Min

Max

7.5

Min

Max Units

I/O to output valid

10.0

MHz

I/O setup time before GCK

I/O hold time after GCK

3.7

4.8

6.5

GCK to output valid

3.5

178.6

4.5

125

5.8

100

Multiple FB internal operating frequency

I/O setup time before p-term clock input

I/O hold time after p-term clock input

P-term clock output valid

SYSTEM

1.7

1.6

2.1

PSU

2.0

3.2

4.4

5.5

4.0

7.0

10.0

10.5

7.7

5.0

9.5

12.0

12.6

10.2

7.0

11.0

14.5

15.3

PCO

GTS to output valid

GTS to output disable

Product term OE to output enabled

Product term OE to output disabled

GSR to output valid

POE

POD

P-term S/R to output valid

GCK pulse width (High or Low)

P-term clock pulse width (High or Low)

PAO

WLH

2.8

5.0

4.0

6.5

4.5

7.0

PLH

TEST

Output Type

TEST

CCIO

Device Output

3.3V

2.5V

3.3V

2.5V

320 Ωꢀ

250 Ωꢀ

360 Ωꢀ

660 Ωꢀ

35 pF

DS058_03_081500

Figure 3: AC Load Circuit

www.xilinx.com

DS058 (v1.2) June 25, 2001

1-800-255-7778

Preliminary Product Specification

XC9536XL High Performance CPLD

Internal Timing Parameters

XC9536XL-5

XC9536XL-7

XC9536XL-10

Symbol

Parameter

Min

Max

Min

Max

Min

Max Units

Buffer Delays

Input buffer delay

GCK buffer delay

GSR buffer delay

GTS buffer delay

1.5

1.1

2.0

4.0

2.0

2.3

1.5

3.1

5.0

2.5

3.5

1.8

4.5

7.0

3.0

GCK

GSR

GTS

OUT

Output buffer delay

Output buffer enable/disable delay

Product Term Control Delays

Product term clock delay

Product term set/reset delay

Product term 3-state delay

1.6

1.0

5.5

2.4

1.4

7.2

2.7

1.8

7.5

PTCK

PTSR

PTTS

Internal Register and Combinatorial Delays

Combinatorial logic propagation delay

2.3

1.4

2.3

1.4

0.5

2.6

2.2

2.6

2.2

1.3

3.0

3.5

3.0

3.5

1.7

PDI

SUI

Internal logic delay

ECSU

ECHO

0.4

6.0

0.5

6.4

1.0

7.0

COI

AOI

5.0

7.5

10.0

RAI

1.0

5.0

1.4

6.4

1.8

7.3

LOGI

Internal low power logic delay

LOGILP

Feedback Delays

FastCONNECT II feedback delay

Time Adders

1.9

3.5

4.2

Incremental product term allocator delay

Slew-rate limited delay

0.7

3.0

0.8

4.0

1.0

4.5

PTA

SLEW

DS058 (v1.2) June 25, 2001

www.xilinx.com

Preliminary Product Specification

1-800-255-7778

XC9536XL High Performance CPLD

XC9536XL I/O Pins

Function Macro

BScan

PC44 VQ44 CS48 VQ64 Order

Function Macro

BScan

Block

cell

Block

cell

PC44 VQ44 CS48 VQ64 Order

105

102

(1)

Notes:

1. Global control pin.

XC9536XL Global, JTAG and Power Pins

Pin Type

I/O/GCK1

I/O/GCK2

I/O/GCK3

I/O/GTS1

I/O/GTS2

I/O/GSR

TCK

PC44

VQ44

CS48

VQ64

TDI

TDO

TMS

21, 41

V_CCINT3.3V

V_CCIO2.5V/3.3V

GND

15, 35

C1, F7

3, 37

10, 23, 31

4, 17, 25

A5, D1, F3

C4, D4

21, 41, 54

No Connects

1, 4, 12, 13, 14, 18,

23, 26, 31, 32, 34, 40,

46, 47, 51, 52, 58, 59

www.xilinx.com

1-800-255-7778

DS058 (v1.2) June 25, 2001

Preliminary Product Specification

XC9536XL High Performance CPLD

Ordering Information

Example:

XC9536XL -5 PC 44 C

Device Type

Temperature Range

Number of Pins

Package Type

Speed Grade

Device Ordering Options

Speed

Package

Temperature

-10 10 ns pin-to-pin delay

-7 7.5 ns pin-to-pin delay

-5 5 ns pin-to-pin delay

-4 4 ns pin-to-pin delay

PC44 44-pin Plastic Lead Chip Carrier (PLCC)

VQ44 44-pin Quad Flat Pack (VQFP)

CS48 48-pin Chip Scale Package

VQ64 64-pin Quad Flat Pack (VQFP)

C = Commercial

I = Industrial

T = 0°C to +70°C

T = –40°C to +85°C

Component Availability

Pins

Plastic

PLCC

PC44

C, I

Plastic

VQFP

VQ44

C, I

Plastic

CSP

CS48

C, I

Plastic

VQFP

VQ64

C, I

Type

Code

XC9536XL

-10

-7

C, I

-5

Notes:

1. C = Commercial (T = 0 C to +70 C); I = Industrial (T = –40 C to +85 C).

Revision History

The following table shows the revision history for this document.

Date

Version

1.0

Revision

09/28/98

08/28/00

06/25/01

Initial Xilinx release.

1.1

Added VQ44 package.

1.2

Removed -4 device. Added C4 and D4 pins to CS48 No Connects in pinout table. Added

industrial availability to -7 device.

DS058 (v1.2) June 25, 2001

www.xilinx.com

Preliminary Product Specification

1-800-255-7778

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XC9536XL-10VQ44I产品参数

型号:	XC9536XL-10VQ44I
是否无铅：	含铅
是否Rohs认证：	不符合
生命周期：	Active
IHS 制造商：	XILINX INC
零件包装代码：	QFP
包装说明：	TQFP, TQFP44,.47SQ,32
针数：	44
Reach Compliance Code：	not_compliant
ECCN代码：	EAR99
HTS代码：	8542.39.00.01
Factory Lead Time：	12 weeks
风险等级：	1.5
Is Samacsys：	N
其他特性：	YES
系统内可编程：	YES
JESD-30 代码：	S-PQFP-G44
JESD-609代码：	e0
JTAG BST：	YES
长度：	10 mm
湿度敏感等级：	3
专用输入次数：
I/O 线路数量：	34
宏单元数：	36
端子数量：	44
最高工作温度：	85 °C
最低工作温度：	-40 °C
组织：	0 DEDICATED INPUTS, 34 I/O
输出函数：	MACROCELL
封装主体材料：	PLASTIC/EPOXY
封装代码：	TQFP
封装等效代码：	TQFP44,.47SQ,32
封装形状：	SQUARE
封装形式：	FLATPACK, THIN PROFILE
峰值回流温度（摄氏度）：	225
电源：	2.5/3.3,3.3 V
可编程逻辑类型：	FLASH PLD
传播延迟：	10 ns
认证状态：	Not Qualified
座面最大高度：	1.2 mm
子类别：	Programmable Logic Devices
最大供电电压：	3.6 V
最小供电电压：	3 V
标称供电电压：	3.3 V
表面贴装：	YES
技术：	CMOS
温度等级：	INDUSTRIAL
端子面层：	Tin/Lead (Sn85Pb15)
端子形式：	GULL WING
端子节距：	0.8 mm
端子位置：	QUAD
处于峰值回流温度下的最长时间：	30
宽度：	10 mm
Base Number Matches：	1

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