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芯片XCR3128XL-10VQG100C的概述 XCR3128XL-10VQG100C是一款由Xilinx公司制造的可编程逻辑器件，属于XCR家族中的一员。作为一种复杂可编程逻辑设备（CPLD），XCR3128XL-10VQG100C提供了高密度的逻辑单元，灵活的设计方案，以及优秀的性能表现。这款芯片以其广泛的应用领域和易于实现的设计要求，为电子工程师和开发人员提供了强大的工具。XCR3128XL-10VQG100C特别适合用于数据处理、信号处理以及建立嵌入式系统的控制逻辑。芯片的详细参数 XCR3128XL-10VQG100C的基本参数如下： - 逻辑单元：提供高达1280个可编程逻辑单元（PLD），每个逻辑单元可实现多种逻辑功能。 - 最大发射延迟：在10ns的工作频率下，保证了高速数据处理的流畅性。 - 输入/输出引脚：总共具备100个引脚，其中包括64个可编程I/O引脚，支...

产品型号XCR3128XL-10VQG100C的Datasheet PDF文件预览

XCR3128XL 128 Macrocell CPLD

DS016 (v2.6) March 31, 2006

Product Specification

Features

Description

•

Low power 3.3V 128 macrocell CPLD

The CoolRunner™ XPLA3 XCR3128XL device is a 3.3V

128 macrocell CPLD targeted at power sensitive designs

that require leading edge programmable logic solutions. A

total of eight function blocks provide 3,000 usable gates.

Pin-to-pin propagation delays are as fast as 5.5 ns with a

maximum system frequency of 175 MHz.

5.5 ns pin-to-pin logic delays

System frequencies up to 175 MHz

128 macrocells with 3,000 usable gates

Available in small footprint packages

144-pin TQFP (108 user I/O pins)

144-ball CS BGA (108 user I/O)

100-pin VQFP (84 user I/O)

TotalCMOS Design Technique for Fast

Zero Power

•

Optimized for 3.3V systems

CoolRunner XPLA3 CPLDs offer a TotalCMOS™ solution,

both in process technology and design technique. Xilinx

employs a cascade of CMOS gates to implement its sum of

products instead of the traditional sense amp approach.

This CMOS gate implementation allows Xilinx CPLDs to

offer devices that are both high performance and low power,

breaking the paradigm that to have low power, you must

have low performance. Refer to Figure 1 or Figure 2 and

Table 1or Table 2 showing the I_CCvs. Frequency of the

XCR3128XL TotalCMOS CPLD (data taken with eight

resetable up/down, 16-bit counters at 3.3V, 25°C).

Ultra low power operation

Typical Standby Current of 17 μA at 25°C

5V tolerant I/O pins with 3.3V core supply

Advanced 0.35 micron five layer metal EEPROM

process

Fast Zero Power™ (FZP) CMOS design

technology

3.3V PCI electrical specification compatible outputs

(no internal clamp diode on any input or I/O)

•

Advanced system features

In-system programming

Input registers

Predictable timing model

Up to 23 available clocks per function block

Excellent pin retention during design changes

Full IEEE Standard 1149.1 boundary-scan (JTAG)

Four global clocks

Eight product term control terms per function block

•

Fast ISP programming times

Port Enable pin for additional I/O

2.7V to 3.6V supply voltage at industrial temperature

range

•

Programmable slew rate control per output

Security bit prevents unauthorized access

100 120 140 160

Frequency (MHz)

Refer to XPLA3 family data sheet (DS012) for

DS016_01_120902

architecture description

Figure 1: Typical I_CCvs. Frequency at V_CC= 3.3V, 25°C

Table 1: Typical I_CCvs. Frequency at V_CC= 3.3V, 25°C

Frequency (MHz)

100

120

140

160

Typical I_CC(mA)

0.017

0.5

2.48

4.97

9.89

19.7

29.5

39.1

48.7

58.0

67.3

76.8

All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.

DS016 (v2.6) March 31, 2006

www.xilinx.com

Product Specification

XCR3128XL 128 Macrocell CPLD

(1)

DC Electrical Characteristics Over Recommended Operating Conditions

Symbol

Parameter

Output High voltage

Test Conditions

Typical

Min.

Max. Unit

(2)

V_OH

V_CC= 3.0V to 3.6V, I_OH= –8 mA

2.4

_CC= 2.7V to 3.0V, I_OH= –8 mA

_OH= –500 μA

Output Low voltage for 3.3V outputs I_OL= 8 mA

2.0

(3)

90% V_CC

V_OL

I_IL

0.4

100

Input leakage current

I/O High-Z leakage current

Standby current

V_IN= GND or V_CCto 5.5V

–10

μA

I_IH

V_IN= GND or V_CCto 5.5V

V_CC= 3.6V

f = 1 MHz

–10

(7)

I_CCSB

I_CC

Dynamic current^(4,5)

f = 50 MHz

C_IN

Input pin capacitance⁽⁶⁾

Clock input capacitance⁽⁶⁾

I/O pin capacitance⁽⁶⁾

f = 1 MHz

C_CLK

C_I/O

f = 1 MHz

Notes:

1. See the CoolRunner XPLA3 family data sheet (DS012) for recommended operating conditions.

2. See Figure 2 for output drive characteristics of the XPLA3 family.

3. This parameter guaranteed by design and characterization, not by testing.

4. See Table 1, Figure 1 for typical values.

5. This parameter measured with a 16-bit, resetable up/down counter loaded into every function block, with all outputs disabled and

unloaded. Inputs are tied to V_CCor ground. This parameter guaranteed by design and characterization, not testing.

6. Typical values, not tested.

7. Typical value at 70° C.

100

(3.3V)

(2.7V)

0.5

1.5

2.5

Volts

3.5

4.5

DS012_10_031802

Figure 2: Typical I/V Curve for the CoolRunner XPLA3 Family, 25°C

www.xilinx.com

DS016 (v2.6) March 31, 2006

Product Specification

XCR3128XL 128 Macrocell CPLD

(1,2)

AC Electrical Characteristics Over Recommended Operating Conditions

-6

-7

-10

Max. Unit

Symbol

T_PD1

Parameter

Propagation delay time (single p-term)

Propagation delay time (OR array)⁽³⁾

Clock to output (global synchronous pin clock)

Setup time (fast input register)

Setup time (single p-term)

Setup time (OR array)

Min.

Max.

5.5

6.0

4.0

Min. Max.

Min.

7.0

7.5

5.0

9.1

10.0

6.5

MHz

μs

T_PD2

T_CO

T_SUF

T_SU1

T_SU2

2.5

3.0

(4)

3.5

4.3

5.4

4.0

4.8

6.3

(4)

T_H

Hold time

(4)

T_WLH

Global Clock pulse width (High or Low)

P-term clock pulse width

2.5

3.0

4.0

(4)

T_PLH

4.0

5.0

6.0

T_APRPW

Asynchronous preset/reset pulse width (High or Low)

Input rise time

4.0

5.0

6.0

(4)

T_R

175

100

7.5

7.0

8.0

119

100

9.3

8.3

9.3

100

11.2

10.7

11.2

(4)

T_L

Input fall time

(4)

f_SYSTEM

Maximum system frequency

Configuration time⁽⁵⁾

T_CONFIG

(4)

T_INIT

ISP initialization time

(4)

T_POE

P-term OE to output enabled

P-term OE to output disabled⁽⁶⁾

P-term clock to output

(4)

T_POD

(4)

T_PCO

(4)

T_PAO

P-term set/reset to output valid

Notes:

1. Specifications measured with one output switching.

2. See the CoolRunner XPLA3 family data sheet (DS012) for recommended operating conditions.

3. See Figure 6 for derating.

4. These parameters guaranteed by design and/or characterization, not testing.

5. Typical current draw during configuration is 9 mA at 3.6V.

6. Output C_L= 5 pF.

(1,2)

Internal Timing Parameters

-6

-7

-10

Symbol

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Unit

Buffer Delays

T_IN

Input buffer delay

Fast Input buffer delay

1.3

2.3

0.8

2.2

4.2

1.6

3.0

1.0

2.7

5.0

2.2

3.1

1.3

3.6

5.7

T_FIN

T_GCK

T_OUT

T_EN

Global Clock buffer delay

Output buffer delay

Output buffer enable/disable delay

Internal Register and Combinatorial Delays

T_LDI

T_SUI

T_HI

Latch transparent delay

1.3

1.6

2.0

1.0

0.3

1.0

0.5

1.2

0.7

DS016 (v2.6) March 31, 2006

www.xilinx.com

Product Specification

XCR3128XL 128 Macrocell CPLD

-6

-7

-10

Symbol

T_ECSU

T_ECHO

T_COI

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Unit

2.0

2.5

3.0

4.5

5.5

1.0

2.5

4.0

2.5

2.0

2.5

1.3

2.3

5.0

2.7

3.2

1.6

2.1

6.0

3.3

4.2

T_AOI

T_RAI

T_PTCK

T_LOGI1

T_LOGI2

Product term clock delay

Internal logic delay (single p-term)

Internal logic delay (PLA OR term)

Feedback Delays

T_F

ZIA delay

1.2

2.9

3.5

Time Adders

T_LOGI3

T_UDA

Fold-back NAND delay

Universal delay

2.0

1.7

4.0

2.5

2.2

5.0

3.0

2.7

6.0

T_SLEW

Notes:

Slew rate limited delay

1. These parameters guaranteed by design and/or characterization, not testing.

2. See the CoolRunner XPLA family data sheet (DS012) for timing model.

www.xilinx.com

DS016 (v2.6) March 31, 2006

Product Specification

XCR3128XL 128 Macrocell CPLD

Switching Characteristics

Component

Values

390Ω

35 pF

OUT

Measurement

Open

Closed

Open

Closed

(High)

POE

(Low)

POE

Note: For T , C1 = 5 pF. Delay measured at

POD

output level of V + 300 mV, V

– 300 mV.

DS016_03_102401

Figure 3: AC Load Circuit

+3.0V

6.0

5.8

90%

10%

5.6

5.4

5.2

1.5 ns

Measurements:

All circuit delays are measured at the +1.5V level of

inputs and outputs, unless otherwise specified.

5.0

4.8

DS016_05_042800

Figure 5: Voltage Waveform

Number of Adjacent Outputs Switching

DS016_04a_120902

Figure 4: Derating Curve for T_PD2

DS016 (v2.6) March 31, 2006

www.xilinx.com

Product Specification

XCR3128XL 128 Macrocell CPLD

Table 3: XCR3128XL I/O Pins (Continued)

Pin Descriptions

Function

Table 2: XCR3128XL User I/O Pins

Block

Macrocell

VQ100

CS144

G13

G12⁽¹⁾

H13

H12

H11

J13

J12

TQ144

89⁽¹⁾

VQ100

CS144

TQ144

62⁽¹⁾

Total User I/O Pins

108

Table 3: XCR3128XL I/O Pins

Function

Block

Macrocell

VQ100

CS144

B12

D11⁽¹⁾

D12

D13

E10

E11

E12

TQ144

106

104⁽¹⁾

102

101

100

73⁽¹⁾

J11

J10

K13

K12

K11

K10

E13

F10

F12

F13

G10

G11

A13

A12

B11

A11

D10

C10

B10

107

109

110

111

112

113

114

N10

M10

L10

N11

M11

L11

M12

116

117

118

119

120

121

143

142

141

140

100

www.xilinx.com

DS016 (v2.6) March 31, 2006

Product Specification

XCR3128XL 128 Macrocell CPLD

Table 3: XCR3128XL I/O Pins (Continued)

Function

Block

Function

Block

Macrocell

VQ100

CS144

TQ144

139

138

Macrocell

VQ100

CS144

TQ144

20⁽¹⁾

H2⁽¹⁾

D2⁽¹⁾

137

136

134

133

132

131

15⁽¹⁾

4⁽¹⁾

Notes:

1. JTAG pins

DS016 (v2.6) March 31, 2006

www.xilinx.com

Product Specification

XCR3128XL 128 Macrocell CPLD

Table 4: XCR3128XL Global, JTAG, Port Enable, Power,

and No Connect Pins

Table 4: XCR3128XL Global, JTAG, Port Enable, Power,

and No Connect Pins

Pin Type

VQ100

CS144

TQ144

Pin Type

IN0 / CLK0

IN1 / CLK1

IN2 / CLK2

IN3 / CLK3

TCK

VQ100

CS144

TQ144

128

127

126

125

GND

26, 38, 43, A6, A8, C5,

59, 74, 86,

3, 17, 33,

52, 57, 59,

C13, D3,

G4, H10, 64, 85, 105,

L6, L7, M9,

N2, N8

124, 129,

135

No Connects

B13, C1,

C2, C11,

C12, L2, L3, 48, 49, 75,

19, 34, 35,

36, 43, 47,

G12

TDI

L12, M1,

M13, N13

103, 108,

122

TDO

D11

104

TMS

Notes:

PORT_EN

Vcc

11⁽¹⁾

F1⁽¹⁾

13⁽¹⁾

1. Port Enable is brought High to enable JTAG pins when JTAG

pins are used as I/O. See family data sheet (DS012) for full

explanation.

3, 18, 34, A10,B2,B6, 24, 50, 51,

39, 51, 66, B8, D4, F11, 58, 73, 76,

82, 91

J2, K6, K7,

L13, N5,

N12

95, 115,

123, 130,

144

www.xilinx.com

DS016 (v2.6) March 31, 2006

Product Specification

XCR3128XL 128 Macrocell CPLD

Device Part Marking and Ordering Combination Information

Device Type

Package

XCRxxxxXL

TQ144

This line not

related to device

part number

Speed

Operating Range

Sample package with part marking.

Speed

Device Ordering and

(pin-to-pin

delay)

Pkg.

Symbol Pins

No. of

Operating

Range⁽¹⁾

Part Marking Number

XCR3128XL-6VQ100C

XCR3128XL-6VQG100C

XCR3128XL-6CS144C

XCR3128XL-6CSG144C

XCR3128XL-6TQ144C

XCR3128XL-6TQG144C

XCR3128XL-7VQ100C

XCR3128XL-7VQG100C

XCR3128XL-7CS144C

XCR3128XL-7CSG144C

XCR3128XL-7TQ144C

XCR3128XL-7TQG144C

XCR3128XL-7VQ100I

XCR3128XL-7VQG100I

XCR3128XL-7CS144I

XCR3128XL-7CSG144I

XCR3128XL-7TQ144I

XCR3128XL-7TQG144I

XCR3128XL-10VQ100C

XCR3128XL-10VQG100C

XCR3128XL-10CS144C

XCR3128XL-10CSG144C

XCR3128XL-10TQ144C

XCR3128XL-10TQG144C

Package Type

6 ns

VQ100

VQG100

CS144

100

144

100

144

100

144

100

144

Very Thin Quad Flat Package (VQFP)

Very Thin Quad Flat Package (VQFP); Pb-Free

Chip Scale Package (CSP)

6 ns

CSG144

TQ144

Chip Scale Package (CSP); Pb-Free

Thin Quad Flat Pack (TQFP)

6 ns

TQG144

VQ100

Thin Quad Flat Pack (TQFP); Pb-Free

Very Thin Quad Flat Package (VQFP)

Very Thin Quad Flat Package (VQFP); Pb-Free

Chip Scale Package (CSP)

7.5 ns

10 ns

VQG100

CS144

CSG144

TQ144

Chip Scale Package (CSP); Pb-Free

Thin Quad Flat Pack (TQFP)

TQG144

VQ100

Thin Quad Flat Pack (TQFP); Pb-Free

Very Thin Quad Flat Package (VQFP)

Very Thin Quad Flat Package (VQFP); Pb-Free

Chip Scale Package (CSP)

VQG100

CS144

CSG144

TQ144

Chip Scale Package (CSP); Pb-Free

Thin Quad Flat Pack (TQFP)

TQG144

VQ100

Thin Quad Flat Pack (TQFP); Pb-Free

Very Thin Quad Flat Package (VQFP)

Very Thin Quad Flat Package (VQFP); Pb-Free

Chip Scale Package (CSP)

VQG100

CS144

CSG144

TQ144

Chip Scale Package (CSP); Pb-Free

Thin Quad Flat Pack (TQFP)

TQG144

Thin Quad Flat Pack (TQFP); Pb-Free

DS016 (v2.6) March 31, 2006

www.xilinx.com

Product Specification

XCR3128XL 128 Macrocell CPLD

Speed

Device Ordering and

Part Marking Number

(pin-to-pin

delay)

Pkg.

Symbol Pins

No. of

Operating

Range⁽¹⁾

Package Type

XCR3128XL-10VQ100I

XCR3128XL-10VQG100I

XCR3128XL-10CS144I

XCR3128XL-10CSG144I

XCR3128XL-10TQ144I

XCR3128XL-10TQG144I

Notes:

10 ns

VQ100

VQG100

CS144

100

144

Very Thin Quad Flat Package (VQFP)

Very Thin Quad Flat Package (VQFP); Pb-Free

Chip Scale Package (CSP)

CSG144

TQ144

Chip Scale Package (CSP); Pb-Free

Thin Quad Flat Pack (TQFP)

TQG144

Thin Quad Flat Pack (TQFP); Pb-Free

1. C = Commercial: T_A= 0° to +70°C; I = Industrial: T_A= –40° to +85°C

Warranty Disclaimer

THESE PRODUCTS ARE SUBJECT TO THE TERMS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED

AT http://www.xilinx.com/warranty.htm. THIS LIMITED WARRANTY DOES NOT EXTEND TO ANY USE OF THE

PRODUCTS IN AN APPLICATION OR ENVIRONMENT THAT IS NOT WITHIN THE SPECIFICATIONS STATED ON THE

THEN-CURRENT XILINX DATA SHEET FOR THE PRODUCTS. PRODUCTS ARE NOT DESIGNED TO BE FAIL-SAFE

AND ARE NOT WARRANTED FOR USE IN APPLICATIONS THAT POSE A RISK OF PHYSICAL HARM OR LOSS OF

LIFE. USE OF PRODUCTS IN SUCH APPLICATIONS IS FULLY AT THE RISK OF CUSTOMER SUBJECT TO

APPLICABLE LAWS AND REGULATIONS.

Additional Information

CoolRunner XPLA3 Data Sheets and Application Notes

Device Package User Guide

Device Packages

Revision History

The following table shows the revision history for this document.

Date

Version

1.0

Revision

04/07/00

05/03/00

11/20/00

12/08/00

01/17/01

04/11/01

04/19/01

08/10/01

01/08/02

Initial Xilinx release.

1.1

Minor updates and added Boundary Scan to pinout table.

Updated pinout tables; corrected note in Table 4 to read: "port enable pin is brought High".

Updated pinout tables.

1.2

1.3

1.4

Removed Timing Model.

1.5

Added Typical I/V curve, Figure 2; added Table 2: Total User I/O; changed V_OHspec.

Updated Typical I/V curve, Figure 2: added voltage levels.

Moved Figure 1 and Table 1 to first page. Changed VQ144 to VQ100 in Table 2.

1.6

1.7

1.8

Updated T_SUFand T_FINspec to match software timing. Added single p-term setup time (T_SU1) to

AC Table, renamed T_SUto T_SU2for setup time through the OR array. Added T_INITspec. Updated

_CONFIGspec. Updated T_HIspec to correct a typo. Updated AC Load Circuit diagram to more

closely resemble true test conditions, added note for T_PODdelay measurement.

01/27/03

1.9

Updated product availability and AC/DC parameters for -6 Commercial and -7 Industrial devices.

Updated T_PCO(added T_PTCK), T_CONFIG, T_INIT, T_F. Updated I_CCvs. Frequency Curve for -6 device;

updated system frequency to 175 MHz; removed Advance Information from -6 device; updated

Derating Curve for -6 device. Updated Ordering Information format.

www.xilinx.com

DS016 (v2.6) March 31, 2006

Product Specification

XCR3128XL 128 Macrocell CPLD

Date

Version

2.0

Revision

07/15/03

08/21/03

02/13/04

07/09/04

Updated test conditions for I_ILand I_IH.

Updated Package Device Marking Pin 1 orientation.

2.1

2.2

Added soldering temperature. Added links to application notes and data sheets.

2.3

Updated the following specifications based on characterization of product after move to UMC

fabrication for all family members: V_OH, T_LOGI3. Deleted derating curve for T_PD2for MOSIV

fabricated material.

11/11/04

04/08/05

03/31/06

2.4

2.5

2.6

Moved from Preliminary Product Specification to Product Specification.

Added I_CCSBTypical and T_APRPWspecifications. Removed T_SOLspecification.

Added Warranty Disclaimer. Added Pb-Free information to ordering table.

DS016 (v2.6) March 31, 2006

www.xilinx.com

Product Specification

XCR3128XL-10VQG100C相关文章

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XCR3128XL-10VQG100C产品参数

型号:	XCR3128XL-10VQG100C
是否无铅：	不含铅
是否Rohs认证：	符合
生命周期：	Active
IHS 制造商：	XILINX INC
零件包装代码：	QFP
包装说明：	TFQFP, TQFP100,.63SQ
针数：	100
Reach Compliance Code：	compliant
ECCN代码：	EAR99
HTS代码：	8542.39.00.01
Factory Lead Time：	12 weeks
风险等级：	0.93
Is Samacsys：	N
其他特性：	YES
最大时钟频率：	95 MHz
系统内可编程：	YES
JESD-30 代码：	S-PQFP-G100
JESD-609代码：	e3
JTAG BST：	YES
长度：	14 mm
湿度敏感等级：	3
专用输入次数：
I/O 线路数量：	84
宏单元数：	128
端子数量：	100
最高工作温度：	70 °C
最低工作温度：
组织：	0 DEDICATED INPUTS, 84 I/O
输出函数：	MACROCELL
封装主体材料：	PLASTIC/EPOXY
封装代码：	TFQFP
封装等效代码：	TQFP100,.63SQ
封装形状：	SQUARE
封装形式：	FLATPACK, THIN PROFILE, FINE PITCH
峰值回流温度（摄氏度）：	260
电源：	3.3 V
可编程逻辑类型：	EE PLD
传播延迟：	10 ns
认证状态：	Not Qualified
座面最大高度：	1.2 mm
子类别：	Programmable Logic Devices
最大供电电压：	3.6 V
最小供电电压：	3 V
标称供电电压：	3.3 V
表面贴装：	YES
技术：	CMOS
温度等级：	COMMERCIAL
端子面层：	Matte Tin (Sn)
端子形式：	GULL WING
端子节距：	0.5 mm
端子位置：	QUAD
处于峰值回流温度下的最长时间：	30
宽度：	14 mm
Base Number Matches：	1

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