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产品型号XCS30XL-4PQG208C的概述

芯片XCS30XL-4PQG208C的概述 XCS30XL-4PQG208C是一款由Xilinx公司推出的可编程逻辑器件（FPGA）。作为其Xilinx Spartan-3系列的一个重要成员，该芯片以灵活性、效率和经济性著称，广泛应用于各种数字电路设计、通信系统、图像处理等领域。该FPGA的设计理念是为开发者提供一个可重构的硬件平台，使其能够根据不同的应用需求进行实时的功能更新和优化。 Spartan-3系列以其高性价比在市场中占据了一席之地，此系列FPGA特别适合嵌入式系统、消费电子产品、汽车电子及其他需要低功耗和高性能的应用。XCS30XL-4PQG208C在开发周期短、设计灵活度高的优势下，为工程师和开发人员提供了强大的支持。芯片XCS30XL-4PQG208C的详细参数 XCS30XL-4PQG208C具备多项重要参数，这些参数确保了其在多种应用中的有效性。以下是该芯片的一些...

产品型号XCS30XL-4PQG208I的Datasheet PDF文件预览

XC9536XL High Performance

CPLD

DS058 (v1.9) April 3, 2007

Product Specification

54V18 Function Blocks, providing 800 usable gates with

propagation delays of 5 ns. See Figure 2 for architecture

overview.

Features

•

5 ns pin-to-pin logic delays

System frequency up to 178 MHz

36 macrocells with 800 usable gates

Available in small footprint packages

Power Estimation

Power dissipation in CPLDs can vary substantially depend-

ing on the system frequency, design application and output

loading. To help reduce power dissipation, each macrocell

in a XC9500XL device may be configured for low-power

mode (from the default high-performance mode). In addi-

tion, unused product-terms and macrocells are automati-

cally deactivated by the software to further conserve power.

44-pin PLCC (34 user I/O pins)

44-pin VQFP (34 user I/O pins)

48-pin CSP (36 user I/O pins)

64-pin VQFP (36 user I/O pins)

Pb-free available for all packages

•

Optimized for high-performance 3.3V systems

Low power operation

5V tolerant I/O pins accept 5 V, 3.3V, and 2.5V

signals

For a general estimate of I_CC, the following equation may be

used:

_CC(mA) = MC_HS(0.175*PT_HS+ 0.345) + MC_LP(0.052*PT_LP

+ 0.272) + 0.04 * MC_TOG(MC_HS+MC_LP)* f

3.3V or 2.5V output capability

Advanced 0.35 micron feature size CMOS

Fast FLASH™ technology

where:

MC_HS= # macrocells in high-speed configuration

Advanced system features

PT_HS= average number of high-speed product terms

per macrocell

MC_LP= # macrocells in low power configuration

PT_LP= average number of low power product terms per

macrocell

f = maximum clock frequency

MCTOG = average % of flip-flops toggling per clock

(~12%)

In-system programmable

Superior pin-locking and routability with

Fast CONNECT™ II switch matrix

Extra wide 54-input Function Blocks

Up to 90 product-terms per macrocell with

individual product-term allocation

Local clock inversion with three global and one

product-term clocks

Individual output enable per output pin

Input hysteresis on all user and boundary-scan pin

inputs

Bus-hold circuitry on all user pin inputs

Full IEEE Standard 1149.1 boundary-scan (JTAG)

This calculation was derived from laboratory measurements

of an XC9500XL part filled with 16-bit counters and allowing

a single output (the LSB) to be enabled. The actual I_CC

value varies with the design application and should be veri-

fied during normal system operation. Figure 1 shows the

above estimation in a graphical form. For a more detailed

discussion of power consumption in this device, see Xilinx

•

Fast concurrent programming

Slew rate control on individual outputs

Enhanced data security features

Excellent quality and reliability

Endurance exceeding 10,000 program/erase

cycles

20 year data retention

ESD protection exceeding 2,000V

•

Pin-compatible with 5V-core XC9536 device in the

44-pin PLCC package and the 48-pin CSP package

WARNING: Programming temperature range of

T_A= 0° C to +70° C

Description

The XC9536XL is a 3.3V CPLD targeted for high-perfor-

mance, low-voltage applications in leading-edge communi-

cations and computing systems. It is comprised of two

All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.

DS058 (v1.9) April 3, 2007

www.xilinx.com

Product Specification

XC9536XL High Performance CPLD

application note XAPP114, “Understanding XC9500XL

CPLD Power.”

178 MHz

rmance

rfo

wer

125 MHz

100

Clock Frequency (MHz)

200

250

150

DS058_01_121501

Figure 1: Typical I_CCvs. Frequency for XC9536XL

JTAG

In-System Programming Controller

JTAG Port

Controller

Function

Block 1

I/O

Macrocells

1 to 18

I/O

Function

Block 2

Macrocells

1 to 18

I/O

Blocks

I/O

I/O/GCK

I/O/GSR

I/O/GTS

DS058_02_081500

Figure 2: XC9536XL Architecture

Function Block outputs (indicated by the bold line) drive the I/O Blocks directly.

www.xilinx.com

DS058 (v1.9) April 3, 2007

Product Specification

XC9536XL High Performance CPLD

(2)

Absolute Maximum Ratings

Symbol

Description

Value

–0.5 to 4.0

–0.5 to 5.5

–65 to +150

+150

Units

V_CC

V_IN

Supply voltage relative to GND

Input voltage relative to GND⁽¹⁾

Voltage applied to 3-state output⁽¹⁾

Storage temperature (ambient)⁽³⁾

Junction temperature

V_TS

T_STG

T_J

^oC

Notes:

1. Maximum DC undershoot below GND must be limited to either 0.5V or 10 mA, whichever is easier to achieve. During transitions, the

device pins may undershoot to –2.0 V or overshoot to +7.0V, provided this over- or undershoot lasts less than 10 ns and with the

forcing current being limited to 200 mA. External I/O voltage may not exceed V_CCINTby 4.0V.

2. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress

ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions

is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.

3. For soldering guidelines and thermal considerations, see the Device Packaging information on the Xilinx website. For Pb-free

packages, see XAPP427.

Recommended Operation Conditions

Symbol

Parameter

Supply voltage for internal logic

and input buffers

Min

3.0

2.3

Max

3.6

Units

V_CCINT

Commercial T_A= 0^oC to 70^oC

Industrial T_A= –40^oC to +85^oC

3.6

V_CCIO

Supply voltage for output drivers for 3.3V operation

Supply voltage for output drivers for 2.5V operation

Low-level input voltage

3.6

2.7

V_IL

V_IH

V_O

0.80

5.5

High-level input voltage

2.0

Output voltage

V_CCIO

Quality and Reliability Characteristics

Symbol

Parameter

Min

Max

Units

T_DR

Data Retention

Years

Cycles

Volts

N_PE

Program/Erase Cycles (Endurance)

Electrostatic Discharge (ESD)

10,000

2,000

V_ESD

DC Characteristic Over Recommended Operating Conditions

Symbol

Parameter

Test Conditions

I_OH= –4.0 mA

_OH= –500 μA

I_OL= 8.0 mA

_OL= 500 μA

V_CC= Max; V_IN= GND or V_CC

V_CC= Max; V_CCIO= Max;

Min

Max

Units

V_OH

Output high voltage for 3.3V outputs

Output high voltage for 2.5V outputs

Output low voltage for 3.3V outputs

Output low voltage for 2.5V outputs

Input leakage current

2.4

90% V_CCIO

V_OL

0.4

±10

I_IL

I_IH

μA

I/O high-Z leakage current

V_IN= GND or 3.6V

_CCMin < V_IN< 5.5V

±50

μA

C_IN

I_CC

I/O capacitance

V_IN= GND; f = 1.0 MHz

Operating supply current

(low power mode, active)

V_IN= GND, No load; f = 1.0 MHz

10 (Typical)

DS058 (v1.9) April 3, 2007

www.xilinx.com

Product Specification

XC9536XL High Performance CPLD

AC Characteristics

XC9536XL-5

XC9536XL-7

XC9536XL-10

Symbol

T_PD

Parameter

Min

Max

5.0

Min

Max

7.5

Min

Max Units

I/O to output valid

10.0

MHz

T_SU

I/O setup time before GCK

I/O hold time after GCK

GCK to output valid

3.7

4.8

6.5

T_H

T_CO

3.5

178.6

4.5

125

5.8

100

f_SYSTEMMultiple FB internal operating frequency

T_PSUI/O setup time before p-term clock input

1.7

2.0

1.6

3.2

2.1

4.4

T_PH

I/O hold time after p-term clock input

T_PCOP-term clock output valid

5.5

4.0

7.0

10.0

10.5

7.7

5.0

9.5

12.0

12.6

10.2

7.0

11.0

14.5

15.3

T_OE

T_OD

GTS to output valid

GTS to output disable

T_POEProduct term OE to output enabled

T_PODProduct term OE to output disabled

T_AO

GSR to output valid

T_PAOP-term S/R to output valid

T_WLHGCK pulse width (High or Low)

2.8

5.0

4.0

6.5

4.5

7.0

T_APRPWAsynchronous preset/reset pulse width (High or Low)

T_PLHP-term clock pulse width (High or Low)

TEST

Output Type

CCIO

TEST

Device Output

3.3V

2.5V

3.3V

2.5V

320 Ω

250 Ω

360 Ω

660 Ω

35 pF

DS058_03_081500

Figure 3: AC Load Circuit

www.xilinx.com

DS058 (v1.9) April 3, 2007

Product Specification

XC9536XL High Performance CPLD

Internal Timing Parameters

XC9536XL-5

XC9536XL-7

XC9536XL-10

Symbol

Parameter

Min

Max

Min

Max

Min

Max Units

Buffer Delays

T_IN

Input buffer delay

1.5

1.1

2.0

4.0

2.0

2.3

1.5

3.1

5.0

2.5

3.5

1.8

4.5

7.0

3.0

T_GCKGCK buffer delay

T_GSRGSR buffer delay

T_GTSGTS buffer delay

T_OUTOutput buffer delay

T_EN

Output buffer enable/disable delay

Product Term Control Delays

T_PTCKProduct term clock delay

T_PTSRProduct term set/reset delay

T_PTTSProduct term 3-state delay

Internal Register and Combinatorial Delays

T_PDICombinatorial logic propagation delay

T_SUIRegister setup time

1.6

1.0

5.5

2.4

1.4

7.2

2.7

1.8

7.5

2.3

1.4

2.3

1.4

0.5

2.6

2.2

2.6

2.2

1.3

3.0

3.5

3.0

3.5

1.7

T_HI

T_ECSURegister clock enable setup time

T_ECHORegister clock enable hold time

T_COIRegister clock to output valid time

T_AOIRegister async. S/R to output delay

T_RAIRegister async. S/R recover before clock

T_LOGIInternal logic delay

0.4

6.0

0.5

6.4

1.0

7.0

5.0

7.5

10.0

1.0

5.0

1.4

6.4

1.8

7.3

T_LOGILPInternal low power logic delay

Feedback Delays

T_F

Fast CONNECT II feedback delay

1.9

3.5

4.2

Time Adders

T_PTAIncremental product term allocator delay

T_SLEWSlew-rate limited delay

0.7

3.0

0.8

4.0

1.0

4.5

DS058 (v1.9) April 3, 2007

www.xilinx.com

Product Specification

XC9536XL High Performance CPLD

(2)

XC9536XL I/O Pins

Function Macro-

BScan

PC44 VQ44 CS48 VQ64 Order

Function Macro-

BScan

Block

cell

Block

cell

PC44 VQ44 CS48 VQ64 Order

5⁽¹⁾

105

102

5⁽¹⁾

43⁽¹⁾B7⁽¹⁾15⁽¹⁾

42 C6 11

44⁽¹⁾B6⁽¹⁾16⁽¹⁾

42⁽¹⁾36⁽¹⁾E6⁽¹⁾

43 37 E7

40⁽¹⁾34⁽¹⁾F6⁽¹⁾

2⁽¹⁾

6⁽¹⁾

7⁽¹⁾

1⁽¹⁾

39⁽¹⁾33⁽¹⁾G7⁽¹⁾64⁽¹⁾

A7⁽¹⁾17⁽¹⁾

Notes:

1. Global control pin.

2. The pin-outs are the same for Pb-free versions of packages.

(1)

XC9536XL Global, JTAG and Power Pins

Pin Type

I/O/GCK1

I/O/GCK2

I/O/GCK3

I/O/GTS1

I/O/GTS2

I/O/GSR

TCK

PC44

VQ44

CS48

VQ64

TDI

TDO

TMS

21, 41

_CCINT3.3V

_CCIO2.5V/3.3V

GND

15, 35

C1, F7

3, 37

10, 23, 31

4, 17, 25

A5, D1, F3

C4, D4

21, 41, 54

No Connects

1, 4, 12, 13, 14, 18,

23, 26, 31, 32, 34, 40,

46, 47, 51, 52, 58, 59

Notes:

1. The pin-outs are the same for Pb-free versions of packages.

www.xilinx.com

DS058 (v1.9) April 3, 2007

Product Specification

XC9536XL High Performance CPLD

Device Part Marking and Ordering Combination Information

Device Type

Package

XC95xxxXL

TQ144

This line not

related to device

part number

Speed

Operating Range

Sample package with part marking.

Notes:

1. Due to the small size of chip scale packages, part marking on these packages does not follow the above

sample and the complete part number cannot be included in the marking. Part marking on chip scale

packages by line:

Line 1 = X (Xilinx logo), then truncated part number (no XC), i.e., 95xxxXL.

Line 2 = Not related to device part number.

Line 3 = Not related to device part number.

Line 4 = Package code, speed, operating temperature, three digits not related to part

number. Package codes: C1 = CS48, C2 = CSG48.

Speed

Device Ordering and

Part Marking Number

(pin-to-pin

delay)

Pkg.

Symbol

No. of

Pins

Operating

Range⁽¹⁾

Package Type

Plastic Lead Chip Carrier (PLCC)

Quad Flat Pack (VQFP)

XC9536XL-5PC44C

XC9536XL-5VQ44C

XC9536XL-5CS48C

XC9536XL-5VQ64C

XC9536XL-7PC44C

XC9536XL-7VQ44C

XC9536XL-7CS48C

XC9536XL-7VQ64C

XC9536XL-7PC44I

XC9536XL-7VQ44I

XC9536XL-7CS48I

XC9536XL-7VQ64I

XC9536XL-10PC44C

XC9536XL-10VQ44C

XC9536XL-10CS48C

XC9536XL-10VQ64C

XC9536XL-10PC44I

XC9536XL-10VQ44I

XC9536XL-10CS48I

XC9536XL-10VQ64I

XC9536XL-5PCG44C

XC9536XL-5VQG44C

5 ns

PC44

VQ44

CS48

VQ64

PC44

VQ44

CS48

VQ64

PC44

VQ44

CS48

VQ64

PC44

VQ44

CS48

VQ64

PC44

VQ44

CS48

VQ64

PCG44

44-pin

48-ball

64-pin

44-pin

48-ball

64-pin

44-pin

48-ball

64-pin

44-pin

48-ball

64-pin

44-pin

48-ball

64-pin

44-pin

5 ns

Chip Scale Package (CSP)

Quad Flat Pack (VQFP)

5 ns

7.5 ns

10 ns

5 ns

Plastic Lead Chip Carrier (PLCC)

Quad Flat Pack (VQFP)

Chip Scale Package (CSP)

Quad Flat Pack (VQFP)

Plastic Lead Chip Carrier (PLCC)

Quad Flat Pack (VQFP)

Chip Scale Package (CSP)

Quad Flat Pack (VQFP)

Plastic Lead Chip Carrier (PLCC)

Quad Flat Pack (VQFP)

Chip Scale Package (CSP)

Quad Flat Pack (VQFP)

Plastic Lead Chip Carrier (PLCC)

Quad Flat Pack (VQFP)

Chip Scale Package (CSP)

Quad Flat Pack (VQFP)

Plastic Lead Chip Carrier (PLCC); Pb-free

Quad Flat Pack (VQFP); Pb-free

5 ns

VQG44 44-pin

DS058 (v1.9) April 3, 2007

www.xilinx.com

Product Specification

XC9536XL High Performance CPLD

Speed

Device Ordering and

Part Marking Number

(pin-to-pin

delay)

Pkg.

Symbol

No. of

Pins

Operating

Range⁽¹⁾

Package Type

XC9536XL-5CSG48C

XC9536XL-5VQG64C

XC9536XL-7PCG44C

XC9536XL-7VQG44C

XC9536XL-7CSG48C

XC9536XL-7VQG64C

XC9536XL-7PCG44I

XC9536XL-7VQG44I

XC9536XL-7CSG48I

XC9536XL-7VQG64I

XC9536XL-10PCG44C

XC9536XL-10VQG44C

XC9536XL-10CSG48C

XC9536XL-10VQG64C

XC9536XL-10PCG44I

XC9536XL-10VQG44I

XC9536XL-10CSG48I

XC9536XL-10VQG64I

Notes:

5 ns

CSG48 48-ball

VQG64 64-pin

Chip Scale Package (CSP); Pb-free

Quad Flat Pack (VQFP); Pb-free

Plastic Lead Chip Carrier (PLCC); Pb-free

Quad Flat Pack (VQFP); Pb-free

Chip Scale Package (CSP); Pb-free

Quad Flat Pack (VQFP); Pb-free

Plastic Lead Chip Carrier (PLCC); Pb-free

Quad Flat Pack (VQFP); Pb-free

Chip Scale Package (CSP); Pb-free

Quad Flat Pack (VQFP); Pb-free

Plastic Lead Chip Carrier (PLCC); Pb-free

Quad Flat Pack (VQFP); Pb-free

Chip Scale Package (CSP); Pb-free

Quad Flat Pack (VQFP); Pb-free

Plastic Lead Chip Carrier (PLCC); Pb-free

Quad Flat Pack (VQFP); Pb-free

Chip Scale Package (CSP); Pb-free

Quad Flat Pack (VQFP); Pb-free

5 ns

7.5 ns

10 ns

PCG44

44-pin

VQG44 44-pin

CSG48 48-ball

VQG64 64-pin

PCG44

44-pin

VQG44 44-pin

CSG48 48-ball

VQG64 64-pin

PCG44

44-pin

VQG44 44-pin

CSG48 48-ball

VQG64 64-pin

PCG44

44-pin

VQG44 44-pin

CSG48 48-ball

VQG64 64-pin

1. C = Commercial: T_A= 0° to +70°C; I = Industrial: T_A= –40° to +85°C.

Pb-

XC9536XL -4 TQ

144

Free Example:

Standard Example: XC9536XL -4 TQ 144

Device

Speed Grade

Package Type

Speed Grade

Package Type

Number of Pins

Temperature Range

-Free

Number of Pins

Temperature Range

www.xilinx.com

DS058 (v1.9) April 3, 2007

Product Specification

XC9536XL High Performance CPLD

Warranty Disclaimer

THESE PRODUCTS ARE SUBJECT TO THE TERMS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED

AT http://www.xilinx.com/warranty.htm. THIS LIMITED WARRANTY DOES NOT EXTEND TO ANY USE OF THE

PRODUCTS IN AN APPLICATION OR ENVIRONMENT THAT IS NOT WITHIN THE SPECIFICATIONS STATED ON THE

THEN-CURRENT XILINX DATA SHEET FOR THE PRODUCTS. PRODUCTS ARE NOT DESIGNED TO BE FAIL-SAFE

AND ARE NOT WARRANTED FOR USE IN APPLICATIONS THAT POSE A RISK OF PHYSICAL HARM OR LOSS OF

LIFE. USE OF PRODUCTS IN SUCH APPLICATIONS IS FULLY AT THE RISK OF CUSTOMER SUBJECT TO

APPLICABLE LAWS AND REGULATIONS.

XCS30XL-4PQG208C相关文章

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XCS30XL-4PQG208I产品参数

型号:	XCS30XL-4PQG208I
是否Rohs认证：	符合
生命周期：	Obsolete
IHS 制造商：	XILINX INC
零件包装代码：	QFP
包装说明：	PLASTIC, QFP-208
针数：	208
Reach Compliance Code：	unknown
ECCN代码：	EAR99
HTS代码：	8542.39.00.01
风险等级：	5.79
其他特性：	MAXIMUM USABLE GATES 30000
最大时钟频率：	217 MHz
CLB-Max的组合延迟：	1.1 ns
JESD-30 代码：	S-PQFP-G208
JESD-609代码：	e3
长度：	28 mm
湿度敏感等级：	3
可配置逻辑块数量：	576
等效关口数量：	10000
输入次数：	169
逻辑单元数量：	1368
输出次数：	169
端子数量：	208
组织：	576 CLBS, 10000 GATES
封装主体材料：	PLASTIC/EPOXY
封装代码：	FQFP
封装等效代码：	QFP208,1.2SQ,20
封装形状：	SQUARE
封装形式：	FLATPACK, FINE PITCH
峰值回流温度（摄氏度）：	245
电源：	3.3 V
可编程逻辑类型：	FIELD PROGRAMMABLE GATE ARRAY
认证状态：	Not Qualified
座面最大高度：	4.1 mm
子类别：	Field Programmable Gate Arrays
最大供电电压：	3.6 V
最小供电电压：	3 V
标称供电电压：	3.3 V
表面贴装：	YES
技术：	CMOS
端子面层：	Matte Tin (Sn)
端子形式：	GULL WING
端子节距：	0.5 mm
端子位置：	QUAD
处于峰值回流温度下的最长时间：	30
宽度：	28 mm
Base Number Matches：	1

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