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Advance Information

MPC107EC/D

Rev. 4, 7/2003

MPC107

PCI Bridge/Memory Controller

Hardware Specifications

This document provides an overview of the MPC107 PCI bridge/memory controller

(PCIB/MC) for high-performance embedded systems. The MPC107 is a cost-effective,

general-purpose PCIB/MC for applications using PCI in networking infrastructure,

telecommunications, and other embedded markets. It can be used in applications such as

network routers and switches, mass storage subsystems, network appliances, and print and

imaging systems.

This document describes pertinent electrical and physical characteristics of the MPC107. For

functional characteristics of the processor, refer to the MPC107 PCI Bridge/Memory

Controller User’s Manual (MPC107UM/D).

This document contains the following topics:

Topic

Page

1

Section 1.1, “Overview”

Section 1.2, “Features”

2

Section 1.3, “General Parameters”

Section 1.4, “Electrical and Thermal Characteristics”

Section 1.5, “Package Description”

Section 1.6, “PLL Configuration”

Section 1.7, “System Design Information”

Section 1.8, “Document Revision History”

Section 1.9, “Ordering Information”

4

29

37

44

47

To locate any published errata or updates for this document, refer to the web site at

http://www.motorola.com/semiconductors.

1.1 Overview

The MPC107 integrates a PCI bridge, memory controller, DMA controller, PIC timers, a

message unit with an Intelligent Input/Output (I O) message controller, and an

2

Inter-Integrated Circuit (I C) controller. The integration reduces the overall packaging

requirements and the number of discrete devices required for an embedded system.

Figure 1 shows the major functional units within the MPC107. Note that this is a conceptual

block diagram intended to show basic features rather than an attempt to show how these

features are physically implemented.

Features

60x Interface

Additional Features:

• Programmable I/O

with Watchpoint

• JTAG/COP Interface

• Power Management

MPC107

60x Bus Interface (64- or 32-Bit Data Bus)

Peripheral Logic Block

Data Bus

Data (64-Bit)

Address

(64- or 32-Bit)

with 8-Bit Parity

or ECC

Data Path

(32-Bit)

ECC Controller

Message

Unit

(with I₂O)

Memory/ROM/

Port X Control/

Address

Central

Memory

Controller

Control

Unit

DMA

Controller

Configuration

Registers

SDRAM_SYNC_IN

I²C

SDRAM Clocks

CPU Clocks

Controller

DLL

PLL

PCI Bus

Interface Unit

PCI_SYNC_IN

PIC

5 Direct/

16 Serial

Interrupts

Address

Translator

PCI

Arbiter

Interrupt

Controller/

Timers

Fanout

Buffers

PCI Bus

Clocks

OSC_IN

32-Bit

Five

PCI Interface Request/Grant

Pairs

Figure 1. MPC107 Block Diagram

1.2 Features

The MPC107 provides an integrated high-bandwidth, high-performance interface for up to two 60x

processors, the PCI bus, and main memory. This section summarizes the major features of the MPC107, as

follows:

•

Memory interface

— 64-/32-bit 100-MHz bus

— Programmable timing supporting either FPM DRAM, EDO DRAM, or SDRAM

— High-bandwidth bus (32-/64-bit data bus) to DRAM

— Supports one to eight banks of 4-, 16-, 64-, or 128-Mbit memory devices, and up to four banks

of 256-Mbit SDRAM devices

— Supports 1-Mbyte to 1-Gbyte DRAM memory

— 144 Mbytes of ROM space

— 8-, 32-, or 64-bit ROM

— Write buffering for PCI and processor accesses

— Supports normal parity, read-modify-write (RMW), or ECC

— Data-path buffering between memory interface and processor

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MPC107 PCI Bridge/Memory Controller Hardware Specifications

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Features

— Low-voltage TTL logic (LVTTL) interfaces

— Port X: 8-, 32-, or 64-bit general-purpose I/O port using ROM controller interface with

programmable address strobe timing

•

32-bit PCI interface operating up to 66 MHz

— PCI 2.1-compliant

— PCI 5.0-V tolerance

— Support for PCI locked accesses to memory

— Support for accesses to PCI memory, I/O, and configuration spaces

— Selectable big- or little-endian operation

— Store gathering of processor-to-PCI write and PCI-to-memory write accesses

— Memory prefetching of PCI read accesses

— Selectable hardware-enforced coherency

— PCI bus arbitration unit (five request/grant pairs)

— PCI agent mode capability

— Address translation unit

— Some internal configuration registers accessible from PCI

Two-channel integrated DMA controller (writes to ROM/Port X not supported)

— Supports direct mode or chaining mode (automatic linking of DMA transfers)

— Supports scatter gathering—read or write discontinuous memory

— Interrupt on completed segment, chain, and error

— Local-to-local memory

•

— PCI-to-PCI memory

— PCI-to-local memory

— PCI memory-to-local memory

•

Message unit

— Two doorbell registers

— An extended doorbell register mechanism that facilitates interprocessor communication

through interrupts in a dual-local-processor system

— Two inbound and two outbound messaging registers

— I O message controller

2

•

I C controller with full master/slave support (except broadcast all)

Programmable interrupt controller (PIC)

— Five hardware interrupts (IRQs) or 16 serial interrupts

— Four programmable timers

•

Integrated PCI bus, CPU, and SDRAM clock generation

Programmable PCI bus, 60x, and memory interface output drivers

Dynamic power management supporting 60x nap, doze, and sleep modes

Programmable input and output signals with watchpoint capability

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MPC107 PCI Bridge/Memory Controller Hardware Specifications

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General Parameters

•

Built-in PCI bus performance monitor facility

Debug features

— Error injection/capture on data path

— IEEE 1149.1 (JTAG)/test interface

•

Processor interface

— Supports up to two PowerPC microprocessors with 60x bus interface

— Supports various operating frequencies and bus divider ratios

— 32-bit address bus, 64-/32-bit data bus supported at 100 MHz

— Supports full memory coherency

— Supports optional local bus slave

— Decoupled address and data buses for pipelining of 60x accesses

— Store gathering on 60x-to-PCI writes

— Concurrent transactions on 60x and PCI buses supported

1.3 General Parameters

The following list provides a summary of the general parameters of the MPC107:

Technology

Die size

0.29 µm CMOS, five-layer metal

2

50 mm

Transistor count

Logic design

Package

0.96 million

Fully-static

Surface mount 503 flip chip plastic ball grid array (FC-PBGA)

Core power supply

2.5 V ± 5% V DC (nominal; see Table 2 for recommended operating

conditions)

I/O power supply

3.0 to 3.6 V DC

1.4 Electrical and Thermal Characteristics

This section provides the AC and DC electrical specifications and thermal characteristics for the MPC107.

1.4.1 DC Electrical Characteristics

The following sections describe the absolute maximum ratings, recommended operating conditions, DC

electrical specifics, characteristics of the output drivers, power consumption estimates, and thermal

characteristics for the MPC107.

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MPC107 PCI Bridge/Memory Controller Hardware Specifications

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Electrical and Thermal Characteristics

1.4.1.1 Absolute Maximum Ratings

The tables in this section describe the MPC107 DC electrical characteristics. Table 1 provides the absolute

maximum ratings.

Table 1. Absolute Maximum Ratings

Characteristic ¹

Supply voltage—core

Symbol

Range

Unit

Notes

V_DD

GV_DD

BV_DD

OV_DD

AV_DD/LAV_DD

LV_DD

–0.3 to 2.75

–0.3 to 3.6

–0.3 to 2.75

–0.3 to 5.4

–0.3 to 3.6

0 to 105

V

Supply voltage—memory bus drivers

Supply voltage—processor bus drivers

Supply voltage—PCI and standard I/O buffers

Supply voltage—PLLs and DLL

Supply voltage—PCI reference

Input voltage

V

V_in

V

2

Operational die-junction temperature range

Storage temperature range

T_j

°C

T_stg

–55 to 150

Notes:

1. Functional and tested operating conditions are given in Table 2. Absolute maximum ratings are stress ratings only,

and functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device

reliability or cause permanent damage to the device.

2. PCI inputs with LV_DD= 5 V ± 5% V DC may be correspondingly stressed at voltages exceeding LV_DD+ 0.5 V DC.

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MPC107 PCI Bridge/Memory Controller Hardware Specifications

5

Electrical and Thermal Characteristics

1.4.1.2 Recommended Operating Conditions

Table 2 provides the recommended and tested operating conditions for the MPC107. Proper device

operation outside of these conditions is not guaranteed.

Table 2. Recommended Operating Conditions

Recommended

Characteristic

Symbol

Unit

Notes

Value

Supply voltage

V_DD

2.5 ± 5%

3.3 ± 5%

2.5 ± 5%

3.3 ± 0.3

2.5 ± 5%

5.0 ± 5%

3.3 ± 0.3

0 to 3.6 or 5.75

0 to 3.6

V

4

6

Supply voltages for memory bus drivers

Supply voltages for processor bus drivers

GV_DD

BV_DD

I/O buffer supply for PCI and standard

PLL supply voltage

OV_DD

AV_DD

LAV_DD

LV_DD

V

4

5

DLL supply voltage

V

5

PCI reference

V

7, 8

1, 2

3

V

Input voltage

PCI inputs

V_in

T_j

V

All other inputs

V

Die-junction temperature

0 to 105

°C

Notes:

1. PCI pins are designed to withstand LV_DD+ 0.5 V DC when LV_DDis connected to a 5.0-V DC power supply.

2. PCI pins are designed to withstand LV_DD+ 0.5 V DC when LV_DDis connected to a 3.3-V DC power supply.

Cautions:

3. Input voltage (V_in) must not be greater than the supply voltage (V_DD/AV_DD/LAV_DD) by more than 2.5 V at all times,

including during power-on reset.

4. OV_DDmust not exceed V_DD/AV_DD/LAV_DDby more than 1.8 V at any time, including during power-on reset. This

limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences.

5. V_DD/AV_DD/LAV_DDmust not exceed OV_DDby more than 0.6 V at any time, including during power-on reset. This

limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences.

6. BV_DD/GV_DDmust not exceed V_DD/AV_DD/LAV_DDby more than 1.8 V at any time, including during power-on reset.

This limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences.

7. LV_DDmust not exceed V_DD/AV_DD/LAV_DDby more than 5.4 V at any time, including during power-on reset. This

limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences.

8. LV_DDmust not exceed OV_DDby more than 3.6 V at any time, including during power-on reset. This limit may be

exceeded for a maximum of 20 ms during power-on reset and power-down sequences.

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MPC107 PCI Bridge/Memory Controller Hardware Specifications

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Electrical and Thermal Characteristics

Figure 2 shows supply voltage sequencing and separation cautions.

LV_DD@ 5 V

5 V

8

7

Note 1

3.3 V

2.5 V

8

OV_DD/BV_DD/GV_DD/(LV_DD@ 3.3 V - - - -)

V_DD/AV_DD/LAV_DD

7

4, 6

5

100 µs

V_DDStable

PLL

Relock

Time ²

0

Time

Voltage

Regulator

Delay

HRESET

Asserted 255

External Memory

Clock Cycles ²

Power Supply Ramp Up

Reset

Configuration Pins

9 External Memory

Clock Cycles Setup Time ³

VM = 1.4 V

5

HRESET

Maximum Rise Time Must be Less Than

One External Memory Clock Cycle ⁴

VM = 1.4 V

HRESET_CPU

Notes:

1. Numbers associated with waveform separations correspond to caution numbers listed in Table 2.

2. Refer to Table 8 for additional information on PLL relock and reset signal assertion timing requirements.

3. Refer to Table 9 for additional information on reset configuration pin setup timing requirements.

4. HRESET must transition from a logic 0 to a logic 1 in less than one SDRAM_SYNC_IN clock cycle for the

device to be in the non-reset state.

5. HRESET_CPU negates 2¹⁷memory clock cycles after HRESET negates.

Figure 2. Supply Voltage Sequencing and Separation Cautions

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MPC107 PCI Bridge/Memory Controller Hardware Specifications

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Electrical and Thermal Characteristics

Figure 3 shows the undershoot and overshoot voltage for the MPC107 memory interface.

4 V

GV_DD+ 5%

GV_DD

V_IH

GND

GND – 0.3 V

V_IL

GND – 1.0 V

Not to Exceed 10%

of t_{SDRAM_CLK}

Figure 3. Overshoot/Undershoot Voltage

Figure 4 and Figure 5 show the undershoot/overshoot voltage of the PCI interface for 3.3- and 5-V signals,

respectively.

11 ns

(Min)

+7.1 V

Overvoltage

Waveform

7.1 V p-to-p

(Min)

0 V

4 ns

(Max)

4 ns

(Max)

62.5 ns

+3.6 V

Undervoltage

Waveform

7.1 V p-to-p

(Min)

–3.5 V

Figure 4. Maximum AC Waveforms for 3.3-V Signaling

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Electrical and Thermal Characteristics

11 ns

(Min)

+7.1 V

Overvoltage

Waveform

7.1 V p-to-p

(Min)

0 V

4 ns

(Max)

4 ns

(Max)

62.5 ns

+3.6 V

Undervoltage

Waveform

7.1 V p-to-p

(Min)

–3.5 V

Figure 5. Maximum AC Waveforms for 5-V Signaling

1.4.1.3 DC Electrical Specifications

Table 3 provides the DC electrical characteristics for the MPC107.

Table 3. DC Electrical Specifications

At recommended operating conditions (See Table 2)

Characteristics

Input high voltage

Conditions ¹

Symbol

Min

Max

Unit Notes

PCI only

V_IH

V_IL

V_IH

V_IL

0.65 × OV_DD

LV_DD

V

2, 3

Input low voltage

Input high voltage

—

2.0

0.3 × OV_DD

All other pins (GV_DD= 3.3 V)

All other pins (BV_DD= 2.5 V)

—

2

1.7

Input low voltage

All inputs except

PCI_SYNC_IN

GND

0.8

PCI_SYNC_IN input high

voltage

CV_IH

CV_IL

I_L

2.4

GND

—

0.4

±70

±10

—

V

PCI_SYNC_IN input low

voltage

Input leakage current for

pins using DRV_PCI driver @ LV_DD= 4.75 V

0.5 V ≤ V_in≤ 2.7 V

µA

V

4

5

Input leakage current all

others

LV_DD= 3.6 V (GV_DD≤ 3.465 V)

I_L

—

Output high voltage

I_OH= driver dependent

(GV_DD= 3.3 V)

V_OH

2.4

—

Output low voltage

I_OL= driver dependent

(GV_DD= 3.3 V)

V_OL

0.4

V

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MPC107 PCI Bridge/Memory Controller Hardware Specifications

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Electrical and Thermal Characteristics

Table 3. DC Electrical Specifications (continued)

At recommended operating conditions (See Table 2)

Characteristics

Conditions ¹

Symbol

Min

Max

Unit Notes

Output high voltage

I_OH= driver dependent

(BV_DD= 2.5 V)

V_OH

1.85

—

V

5

All outputs except

CPU_CLK[0:2]

I_OH= driver dependent

(BV_DD= 2.5 V)

CPU_CLK[0:2] only

V_OH

2.0

—

V

5

Output low voltage

I

_OL= driver dependent

V_OL

0.4

(BV_DD= 2.5 V)

All outputs except

CPU_CLK[0:2]

I_OL= driver dependent

(BV_DD= 2.5 V)

CPU_CLK[0:2] only

V_OL

—

0.3

7.0

V

5

6

Capacitance

V_in= 0 V, f = 1 MHz

C_in

pF

Notes:

1. These specifications are for the default driver strengths indicated in Table 4.

2. See Figure 17 for pins with internal pull-up resistors.

3. The minimum input high voltage is not compliant with the PCI Local Bus Specification (Rev 2.1), which specifies

0.5 × OV_DDfor minimum input high voltage.

4. Leakage current is measured on input and output pins in the high-impedance state. The leakage current is

measured for nominal OV_DD/LV_DDand V_DDor both OV_DD/LV_DDand V_DDmust vary in the same direction.

5. See Table 4 for the typical drive capability of a specific signal pin based on the type of output driver associated

with that pin as listed in Table 17.

6. Capacitance is periodically sampled rather than 100% tested.

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MPC107 PCI Bridge/Memory Controller Hardware Specifications

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Electrical and Thermal Characteristics

1.4.1.4 Output Driver Characteristics

Table 4 provides information on the characteristics of the output drivers referenced in Table 17. The values

are from the MPC107 IBIS model (v1.1) and are not tested. For additional detailed information, see the

complete IBIS model listing at http://www.motorola.com/semiconductors.

Table 4. Drive Capability of MPC107 Output Pins

Programmable

Supply

Driver Type

Output Impedance

I_OH

I_OL

Unit

Notes

Voltage

(Ω)

DRV_CPU

20

BV_DD= 3.3 V

BV_DD= 2.5 V

BV_DD= 3.3 V

BV_DD= 2.5 V

OV_DD= 3.3 V

GV_DD= 3.3 V

36.6

21.4

18.6

10.8

12.0

6.1

18.1

15.6

9.2

mA

2, 5

3, 6, 7

2, 5

40 (default)

7.9

3, 6, 7

1, 4

DRV_PCI

25

50 (default)

8 (default)

13.3

12.4

6.3

1, 4

DRV_CPU_CLK

DRV_MEM_CTRL

DRV_MEM_CLK

DRV_PCI_CLK

89.0

55.8

36.6

18.6

36.6

18.6

42.3

26.4

18.1

9.2

2, 5

20

2, 5

40

2, 5

DRV_MEM_DATA

20 (default)

40

18.1

9.2

2, 5

Notes:

1. For DRV_PCI, I_OHread from the IBIS listing in the pull-up mode, I(Min) column, at the 0.33-V label by interpolating

between the 0.3- and 0.4-V table entries’ current values which corresponds to the PCI V_OH= 2.97 = 0.9 × OV_DD

(OV_DD= 3.3 V), where table entry voltage = OV_DD– PCI V_OH

2. For all others with GV_DDor BV_DD= 3.3 V, I_OHread from the IBIS listing in the pull-up mode, I(Min) column, at the

0.9-V table entry which corresponds to the V_OH= 2.4 V, where table entry voltage = G/BV_DD– V_OH

.

3. For all others with BV_DD= 2.5 V, I_OHread from the IBIS listing in the pull-up mode, I(Min) column, at the 0.65-V

table entry by interpolating between the 0.6- and 0.7-V table entries’ current values which corresponds to the

V_OH= 1.85 V, where table entry voltage = BV_DD– V_OH

.

4. For DRV_PCI, I_OLread from the IBIS listing in the pull-down mode, I(Min) column, at 0.33 V = PCI V_OL

=

0.1 × OV_DD(OV_DD= 3.3 V) by interpolating between the 0.3-and 0.4-V table entries.

5. For all others with GV_DDor BV_DD= 3.3 V, I_OLread from the IBIS listing in the pull-down mode, I(Min) column, at

the 0.4-V table entry.

6. For all others with BV_DD= 2.5 V, I_OLread from the IBIS listing in the pull-down mode, I(Min) column, at the 0.4-V

table entry.

7. For BV_DD= 2.5 V, the I_OHand I_OLvalues are estimated from the io_mem_data_XX_2.5 and

io_mem_addr_XX_2.5 sections of the IBIS model, where XX = driver output impedance (20 or 40 Ω).

MOTOROLA

MPC107 PCI Bridge/Memory Controller Hardware Specifications

11

Electrical and Thermal Characteristics

1.4.1.5 Power Characteristics

Table 5 provides the preliminary power consumption estimates for the MPC107. Power consumption on the

PLL supply pin (AV ) and the DLL supply pin (LAV ) < 15 mW. This information is based on

DD

characterization data.

Table 5. Power Consumption

PCI_SYNC_IN/Core Frequency (MHz)

25/50

33/33

33/66

66/100

V_DD

Mode

Unit

Notes

V_DD

I/O

V_DD

I/O

V_DD

I/O

Power

Typical

468

176

139

79

923

697

744

718

351

118

93

759

636

693

677

644

235

185

102

1087

800

420

841

933

350

276

138

1122

915

970

939

mW

1, 2

Doze

Nap

Sleep

Notes:

45

1. Power is measured with V_DD= 2.625 V, GV_DD= OV_DD= BV_DD= 3.45 V at 0°C and one DIMM populated in test

system.

2. All clock drivers enabled.

1.4.1.6 Thermal Characteristics

Table 6 provides the package thermal characteristics for the MPC107. Refer to Section 1.7, “System Design

Information,” for more details about thermal management.

Table 6. FC-PBGA Package Thermal Characteristics

Characteristic

Symbol

Value

Unit

Notes

Junction-to-ambient natural convection

(Single-layer board—1s)

R

30

°C/W

1, 2

JA

θ

Junction-to-ambient natural convection

(Four-layer board—2s2p)

R

26

25

22

°C/W

1, 3

JMA

θ

Junction-to-ambient (@200 ft/min)

(Single-layer board—1s)

R

Junction-to-ambient (@200 ft/min)

(Four-layer board—2s2p)

Junction-to-board

Junction-to-case

Notes:

R

20

°C/W

4

5

JB

JC

θ

<0.1

θ

1. Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board)

temperature, ambient temperature, airflow, power dissipation of other components on the board, and board

thermal resistance.

2. Per SEMI G38-87 and JEDEC JESD51-2 with the single-layer board horizontal.

3. Per JEDEC JESD51-6 with the board horizontal.

4. Thermal resistance between the die and the printed-circuit board per JEDEC JESD51-8. Board temperature is

measured on the top surface of the board near the package.

5. Thermal resistance between the die and the case top surface without thermal grease.

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MPC107 PCI Bridge/Memory Controller Hardware Specifications

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Electrical and Thermal Characteristics

1.4.2 AC Electrical Characteristics

This section provides the AC electrical characteristics for the MPC107. After fabrication, functional parts

are sorted by maximum core frequency as shown in Table 7 and Section 1.4.2.1, “Clock AC Specifications,”

and tested for conformance to the AC specifications for that frequency. The core frequency is determined

by the bus (PCI_SYNC_IN) clock frequency and the settings of the PLL_CFG[0:3] signals. Parts are sold

by maximum processor core frequency; see Section 1.9, “Ordering Information.”

Table 7 provides the operating frequency information for the MPC107.

Table 7. Operating Frequency ¹

At recommended operating conditions (See Table 2) with LV = 3.3 V ± 0.3 V

DD

66 MHz

100 MHz

Characteristic ²

Unit

Min

25

Max

Min

Max

Core (memory bus/processor bus) frequency

PCI input frequency (PCI_SYNC_IN)

Notes:

66

25

100

MHz

12.5–66

1. See Section 1.9.2, “Part Numbers Not Fully Addressed by This Document,” for information on the 133-MHz part

offering.

2. The PCI_SYNC_IN frequency and PLL_CFG[0:3] settings must be chosen such that the resulting peripheral

logic/memory bus frequency, CPU (core) frequency, and PLL (VCO) frequencies do not exceed their respective

maximum or minimum operating frequencies. Refer to the PLL_CFG[0:3] signal description in Section 1.6, “PLL

Configuration,” for valid PLL_CFG[0:3] settings and PCI_SYNC_IN frequencies.

1.4.2.1

Clock AC Specifications

Table 8 provides the clock AC timing specifications as defined in Section 1.4.2.2, “Input AC Timing

Specifications.” These specifications are for the default driver strengths indicated in Table 4.

Table 8. Clock AC Timing Specifications

At recommended operating conditions (See Table 2) with LV = 3.3 V ± 0.3 V

DD

Num

Characteristics and Conditions

Min

Max

Unit

Notes

1a Frequency of operation (PCI_SYNC_IN)

1b PCI_SYNC_IN cycle time

12.5

80

—

40

6

66

15

MHz

ns

%

7

1

2,3 PCI_SYNC_IN rise and fall times

2.0

60

4

PCI_SYNC_IN duty cycle measured at 1.4 V

5a PCI_SYNC_IN pulse width high measured at 1.4 V

5b PCI_SYNC_IN pulse width low measured at 1.4 V

9

ns

ps

µs

2

6

9

7

PCI_SYNC_IN jitter

—

<150

500

350

150

100

9a PCI_CLK[0:4] skew (pin-to-pin)

9b SDRAM_CLK[0:3] skew (pin-to-pin)

9c CPU_CLK[0:2] skew (pin-to-pin)

9d SDRAM_CLK[0:3]/CPU_CLK[0:2] jitter

10 Internal PLL relock time

2, 3, 5

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MPC107 PCI Bridge/Memory Controller Hardware Specifications

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Electrical and Thermal Characteristics

Table 8. Clock AC Timing Specifications (continued)

At recommended operating conditions (See Table 2) with LV = 3.3 V ± 0.3 V

DD

Num

Characteristics and Conditions

Min

Max

Unit

Notes

15 DLL lock range with DLL_STANDARD = 1 (default)

16 DLL lock range with DLL_STANDARD = 0

17 Frequency of operation (OSC_IN)

18 OSC_IN cycle time

See Figure 8

See Figure 9

12.5

ns

6

7

4

66

15

5

MHz

ns

80

—

40

—

19 OSC_IN rise and fall times

ns

20 OSC_IN duty cycle measured at 1.4 V

21 OSC_IN frequency stability

Notes:

60

100

%

ppm

1. Rise and fall times for the PCI_SYNC_IN input are measured from 0.4 to 2.4 V.

2. Specification value at maximum frequency of operation.

3. Relock time is guaranteed by design and characterization. Relock time is not tested.

4. Rise and fall times for the OSC_IN input are guaranteed by design and characterization. OSC_IN input rise and

fall times are not tested.

5. Relock timing is guaranteed by design. PLL-relock time is the maximum amount of time required for PLL lock after

a stable V_DDand PCI_SYNC_IN are reached during the reset sequence. This specification also applies when the

PLL has been disabled and subsequently re-enabled during sleep mode. Also note that HRESET must be held

asserted for a minimum of 255 bus clocks after the PLL-relock time during the reset sequence.

6. DLL_STANDARD is bit 7 of the PMC2 register <72>. N is a non-zero integer (1 or 2). T_clkis the period of one

SDRAM_SYNC_OUT clock cycle in ns. t_loopis the propagation delay of the DLL synchronization feedback loop

(PC board runner) from SDRAM_SYNC_OUT to SDRAM_SYNC_IN in ns; 6.25 inches of loop length (unloaded

PC board runner) corresponds to approximately 1 ns of delay. See Figure 8 and Figure 9 for DLL locking ranges.

7. See Table 18 for PCI_SYNC_IN input frequency range for specific PLL_CFG[0:3] settings.

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MPC107 PCI Bridge/Memory Controller Hardware Specifications

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Electrical and Thermal Characteristics

Figure 6 shows PCI_SYNC_IN input clock timing, Figure 7 illustrates how the clock specifications in

Table 8 relate to the MPC107 clocking. Figure 8 and Figure 9 shows the DLL locking range loop delay.

1

5a

5b

2

3

CV_IH

VM

PCI_SYNC_IN

CV_IL

VM = Midpoint Voltage (1.4 V)

Figure 6. PCI_SYNC_IN Input Clock Timing Diagram

MPC107

CPU_CLK[0:2] Specs. 9c, 9d

Specs. 15,16

SDRAM_CLK[0:3]

DLL

Specs. 9b, 9d

Spec. 10

PLL

SDRAM_SYNC_OUT

SDRAM_SYNC_IN

sys_logic_clk

PCI_SYNC_IN

Specs. 1–7

PCI_SYNC_OUT

OSC_IN

Specs. 17–23

Spec. 9a

PCI_CLK[0:4]

Core Logic

Note: Specification numbers are from Table 8.

Figure 7. Clock Subsystem Block Diagram

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Electrical and Thermal Characteristics

50

45

T_clk= 1.8 × T_loop+ 27.9 ns

40

35

30

25

20

15

10

5

T_clk= 2.2 × T_loop+ 11.88 ns

T_clk= 0.6 × T_loop+ 9.27 ns

T_clk= 0.7 × T_loop+ 3.96 ns

0

5

10

15

T_loopPropagation Delay Time (ns)

Figure 8. DLL Locking Range Loop Delay (DLL_STANDARD = 0)

50

45

40

35

30

25

20

15

10

5

T_clk= 0.9 × T_loop+ 13.95 ns

T_clk= 1.1 × T_loop+ 5.94 ns

T_clk= 0.45 × T_loop+ 6.98 ns

T_clk= 0.55 × T_loop+ 2.97 ns

0

5

10

15

T_loopPropagation Delay Time (ns)

Figure 9. DLL Locking Range Loop Delay (DLL_STANDARD = 1)

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Electrical and Thermal Characteristics

1.4.2.2 Input AC Timing Specifications

Table 9 provides the input AC timing specifications. See Figure 10 and Figure 11.

Table 9. Input AC Timing Specifications

At recommended operating conditions (see Table 2) with LV = 3.3 V ± 0.3 V

DD

Num

Characteristic

Min

Max

Unit

Notes

10a PCI input signals valid to PCI_SYNC_IN (input setup)

3.0

2.0

—

ns

2, 3

1, 3

10b Memory interface signals valid to SDRAM_SYNC_IN (input setup)

10c PIC, misc. debug input signals valid to SDRAM_SYNC_IN (input setup)

10d I²C input signals valid to SDRAM_SYNC_IN (input setup)

10e Mode select inputs valid to HRESET (input setup)

2.0

1, 3

2.0

1, 3

9 × t_CLK

2.0

3, 4, 5

1, 3

10f 60x processor interface signals valid to SDRAM_SYNC_IN

(input setup)

11a1 PCI_SYNC_IN (SDRAM_SYNC_IN) to inputs invalid (input hold)

1.0

0.5

—

ns

2, 3

1, 3

11a2 Memory interface signals SDRAM_SYNC_IN to inputs invalid

(input hold)

11a3 60x processor interface signals SDRAM_SYNC_IN to inputs invalid

(input hold)

0

—

ns

1, 3

11b HRESET to mode select inputs invalid (input hold)

1, 3, 5

Notes:

1. All memory, processor, and related interface input signal specifications are measured from the TTL level (0.8 or

2.0 V) of the signal in question to the VM = 1.4 V of the rising edge of the memory bus clock, SDRAM_SYNC_IN.

SDRAM_SYNC_IN is the same as PCI_SYNC_IN in 1:1 mode, but is twice the frequency in 2:1 mode

(processor/memory bus clock rising edges occur on every rising and falling edge of PCI_SYNC_IN). See

Figure 10.

2. All PCI signals are measured from OV_DD/2 of the rising edge of PCI_SYNC_IN to 0.4 × OV_DDof the signal in

question for 3.3-V PCI signaling levels. See Figure 11.

3. Input timings are measured at the pin.

4. t_CLKis the time of one SDRAM_SYNC_IN clock cycle.

5. All mode select input signal specifications are measured from the TTL level (0.8 or 2.0 V) of the signal in question

to the VM = 1.4 V of the rising edge of the HRESET signal. See Figure 12.

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17

Electrical and Thermal Characteristics

Figure 10 shows input-output timing referenced to SDRAM_SYNC_IN and Figure 11 the input-output

timing referenced to PCI_SYNC_IN.

PCI_SYNC_IN

SDRAM_SYNC_IN

(Shown in 2:1 Mode)

VM

10b-d

13b

14b

11a

12b-d

2.0 V

Memory

Inputs/Outputs

0.8 V

Input Timing

Output Timing

VM = Midpoint Voltage (1.4 V)

Figure 10. Input-Output Timing Diagram Referenced to SDRAM_SYNC_IN

OV_DD÷ 2

PCI_SYNC_IN

10a

13a

14a

12a

11a

0.615 × OV

0.285 × OV

DD

PCI

Inputs/Outputs

0.4 × OV

DD

Input Timing

Output Timing

Figure 11. Input-Output Timing Diagram Referenced to PCI_SYNC_IN

Figure 12 shows input timing for mode select signals.

VM

HRESET

10e

11b

2.0 V

0.8 V

Mode Pins

VM = Midpoint Voltage (1.4 V)

Figure 12. Input Timing Diagram for Mode Select Signals

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Electrical and Thermal Characteristics

1.4.2.3 Output AC Timing Specification

Table 10 provides the processor bus AC timing specifications for the MPC107. See Figure 10 and Figure 11.

Table 10. Output AC Timing Specifications

At recommended operating conditions (see Table 2) with LV = 3.3 V ± 0.3 V

DD

Num

Characteristic ^{3, 6}

Min

Max

Unit

Notes

12a PCI_SYNC_IN to output valid, 66 MHz PCI, with SDMA4

pulled-down to logic 0 state (see Figure 11)

—

6.0

ns

2, 4

PCI_SYNC_IN to output valid, 33 MHz PCI, with SDMA4 in the

default logic 1 state (see Figure 11)

—

11.0

ns

2, 4

12b Memory interface signals, SDRAM_SYNC_IN to output valid

—

5.5

ns

1

12b1 Memory interface signal, CKE (100-MHz device),

SDRAM_SYNC_IN to output valid

12b2 Memory interface signal, CKE (66-MHz device), SDRAM_SYNC_IN

to output valid

—

6.0

ns

1

12c PIC, misc. debug signals, SDRAM_SYNC_IN to valid

12d I²C, SDRAM_SYNC_IN to output valid

—

9.0

5.0

5.5

—

ns

1

12e 60x Processor interface signals, SDRAM_SYNC_IN to output valid

—

13a Output hold, 66 MHz PCI, with SDMA4 and SDMA3 pulled down to

logic 0 states (see Table 11)

1.0

2, 4, 5

Output hold, 33 MHz PCI, with SDMA4 in the default logic 1 state

and SDMA3 pulled down to logic 0 state (see Table 11)

2.0

—

ns

2, 4, 5

13b Output hold (for all others)

1

—

14.0

4.0

ns

1

2, 4

1

14a PCI_SYNC_IN to output high impedance (T_offfor PCI)

14b SDRAM_SYNC_IN to output high impedance (for all others)

Notes:

—

1. All memory and related interface output signal specifications are specified from the VM = 1.4 V of the rising edge of

the memory bus clock, SDRAM_SYNC_IN to the TTL level (0.8 or 2.0 V) of the signal in question.

SDRAM_SYNC_IN is the same as PCI_SYNC_IN in 1:1 mode, but is twice the frequency in 2:1 mode

(processor/memory bus clock rising edges occur on every rising and falling edge of PCI_SYNC_IN). See

Figure 10.

2. All PCI signals are measured from OV_DD/2 of the rising edge of PCI_SYNC_IN to 0.285*OV_DDor 0.615*OV_DDof

the signal in question for 3.3-V PCI signaling levels. See Figure 11.

3. All output timings assume a purely resistive 50-Ω load (see Figure 13). Output timings are measured at the pin;

time-of-flight delays must be added for trace lengths, vias, and connectors in the system.

4. PCI bused signals are composed of the following signals: LOCK, IRDY, C/BE[0:3], PAR, TRDY, FRAME, STOP,

DEVSEL, PERR, SERR, AD[0:31], REQ[4:0], GNT[4:0], IDSEL, and INTA.

5. PCI hold times can be varied; see Section 1.4.2.4, “PCI Signal Output Hold Timing,” for information on

programmable PCI output hold times. The values shown for item 13a are for PCI compliance.

6. These specifications are for the default driver strengths indicated in Table 4.

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19

Electrical and Thermal Characteristics

Figure 13 shows the AC test load for the MPC107.

Output Measurements are Made at the Device Pin

Output

Z₀= 50 Ω

OV_DD/2

R_L= 50 Ω

Figure 13. AC Test Load for the MPC107

1.4.2.4 PCI Signal Output Hold Timing

In order to meet minimum output hold specifications relative to PCI_SYNC_IN for both 33 and 66 MHz

PCI systems, the MPC107 has a programmable output hold delay for PCI signals. The initial value of the

output hold delay is determined by the values on the SDMA4 and SDMA3 reset configuration signals.

Further output hold delay values are available by programming the PCI_HOLD_DEL value of the PMCR2

configuration register.

Table 11 describes the bit values for the PCI_HOLD_DEL values in PMCR2.

Table 11. Power Management Configuration Register 2—0x72

Reset

Value

Bit

Name

Description

6–4

PCI_HOLD_DEL

xx0

PCI output hold delay values relative to PCI_SYNC_IN. The initial

values of bits 6 and 5 are determined by the reset configuration pins

SDMA4 and SDMA3, respectively. As these two pins have internal

pull-up resistors, the default value after reset is 0b110.

While the minimum hold times are guaranteed at shown values,

changes in the actual hold time can be made by incrementing or

decrementing the value in these bit fields of this register via software

or hardware configuration. The increment is in approximately

400-picosecond steps. Lowering the value in the 3-bit field decreases

the amount of output hold available.

000 66 MHz PCI. Pull-down SDMA4 configuration pin with a 2-kΩ or

less value resistor. This setting guarantees the minimum output

hold (item 13a) and the maximum output valid (item 12a) times

as specified in Figure 10 are met for a 66-MHz PCI system. See

Figure 14.

001

010

011

100 33 MHz PCI. This setting guarantees the minimum output hold

(item 13a) and the maximum output valid (item 12a) times as

specified in Figure 10 are met for a 33-MHz PCI system. See

Figure 14.

101

110 (Default if reset configuration pins left unconnected)

111

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MPC107 PCI Bridge/Memory Controller Hardware Specifications

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Electrical and Thermal Characteristics

Figure 14 shows the PCI_HOLD_DEL effect on output valid and hold time.

OV_DD÷ 2

PCI_SYNC_IN

12a, 8 ns for 33 MHz PCI

PCI_HOLD_DEL = 100

13a, 2 ns for 33 MHz PCI

PCI_HOLD_DEL = 100

PCI Inputs/Outputs

33 MHz PCI

12a, 6 ns for 66 MHz PCI

PCI_HOLD_DEL = 000

13a, 1 ns for 66 MHz PCI

PCI_HOLD_DEL = 000

PCI Inputs/Outputs

66 MHz PCI

As PCI_HOLD_DEL

Values Decrease

PCI Inputs

and Outputs

As PCI_HOLD_DEL

Values Increase

Output Valid

Output Hold

Note: Diagram not to scale.

Figure 14. PCI_HOLD_DEL Effect on Output Valid and Hold Time

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21

Electrical and Thermal Characteristics

2

1.4.2.5 I C AC Timing Specifications

2

Table 12 provides the I C input AC timing specifications for the MPC107.

Table 12. I²C Input AC Timing Specifications

At recommended operating conditions (see Table 2) with LV = 3.3 V ± 0.3 V

DD

Num

Characteristic

Min

Max

Unit

Notes

1

2

Start condition hold time

4.0

—

CLKs

1, 2

Clock low period (the time before

MPC107 will drive SCL low as a

transmitting slave after detecting SCL

low as driven by an external master)

8.0 + (16 × 2^FDR[4:2]) × (5 –

4({FDR[5],FDR[1]} == b'10) –

3({FDR[5],FDR[1]} == b'11) –

2({FDR[5],FDR[1]} == b'00) –

1({FDR[5],FDR[1]} == b'01))

1, 2, 4, 5

3

4

5

6

SCL/SDA rise time (from 0.5 to 2.4 V)

Data hold time

—

0

1

—

1

ms

ns

2

SCL/SDA fall time (from 2.4 to 0.5 V)

—

5.0

ms

Clock high period (time needed to

either receive a data bit or generate a

START or STOP)

—

CLKs

1, 2, 5

7

8

Data setup time

3.0

4.0

—

ns

3

Start condition setup time (for repeated

start condition only)

CLKs

1, 2

9

Stop condition setup time

4.0

—

CLKs

1, 2

Notes:

1. Units for these specifications are in SDRAM_CLK/CPU_CLK units.

2. The actual values depend on the setting of the digital filter frequency sampling rate (DFFSR) bits in the frequency

divider register I2CFDR. Therefore, the noted timings in this table are all relative to qualified signals. The qualified

SCL and SDA are delayed signals from what is seen in real time on the I²C bus. The qualified SCL, SDA signals

are delayed by the SDRAM_CLK/CPU_CLK clock times DFFSR times two plus one SDRAM_CLK/CPU_CLK

clock. The resulting delay value is added to the value in this table (where this note is referenced). See Figure 16.

3. Timing is relative to the sampling clock (not SCL).

4. FDR[n] refers to the frequency divider register (FDR) I2CFDR bit n.

5. Input clock low and high periods in combination with the FDR value in the frequency divider register (I2CFDR)

determine the maximum I²C input frequency. See Figure 13.

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Electrical and Thermal Characteristics

2

Table 13 provides the I C frequency divider register (I2CFDR) information for the MPC107.

Table 13. MPC107 Maximum I²C Input Frequency

Maximum I²C Input Frequency ¹

FDR Hex ²

Divider ³(Dec)

SDRAM_CLK/ SDRAM_CLK/ SDRAM_CLK/ SDRAM_CLK/

CPU_CLK

@ 25 MHz

CPU_CLK

@ 33 MHz

CPU_CLK

@ 50 MHz

CPU_CLK

@ 100 MHz

20, 21

160, 192

862

555

409

324

1.13 MHz

733

1.72 MHz

1.11 MHz

819

3.44 MHz

2.22 MHz

1.63 MHz

1.29 MHz

22, 23, 24, 25

0, 1

224, 256, 320, 384

288, 320

540

2, 3, 26, 27, 28, 29 384, 448, 480, 512,

640, 768

428

649

4, 5

576, 640

229

177

302

234

458

354

917

709

6, 7, 2A, 2B, 2C, 2D 768, 896, 960, 1024,

1280, 1536

8, 9

1152, 1280

121

92

160

122

243

185

487

371

A, B, 2E, 2F, 30, 31 1536, 1792, 1920,

2048, 2560, 3072

C, D

2304, 2560

62

47

83

62

125

95

251

190

E, F, 32, 33, 34, 35 3072, 3584, 3840,

4096, 5120, 6144

10, 11

4608, 5120

32

24

42

31

64

48

128

96

12, 13, 36, 37, 38,

39

6144, 7168, 7680,

8192, 10240, 12288

14, 15

9216, 10240

16

12

21

16

32

24

64

48

16, 17, 3A, 3B, 3C, 12288, 14336, 15360,

3D

16384, 20480, 24576

18, 19

18432, 20480

8

6

10

8

16

12

32

24

1A, 1B, 3E, 3F

24576, 28672, 30720,

32768

1C, 1D

1E, 1F

Notes:

36864, 40960

49152, 61440

4

3

5

4

8

6

16

12

1. Values are in kHz, unless otherwise specified.

2. FDR Hex and Divider (Dec) values are listed in corresponding order.

3. Multiple Divider (Dec) values will generate the same input frequency, but each Divider (Dec) value will generate a

unique output frequency as shown in Table 14.

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Electrical and Thermal Characteristics

2

Table 14 provides the I C output AC timing specifications for the MPC107.

Table 14. I²C Output AC Timing Specifications

At recommended operating conditions (see Table 2) with LV = 3.3 V ± 0.3 V

DD

Num

Characteristic

Min

Max

Unit

Notes

1

Start condition hold time

(FDR[5] == 0) × (D_FDR/16)/2N + (FDR[5]

== 1) × (D_FDR/16)/2M

—

CLKs

1, 2, 5

2

3

Clock low period

D_FDR/2

—

CLKs

ms

1, 2, 5

3

SCL/SDA rise time (from 0.5 to

2.4 V)

4

Data hold time

8.0 + (16 × 2^FDR[4:2]) × (5 –

4({FDR[5],FDR[1]} == b'10)–

3({FDR[5],FDR[1]} == b'11) –

2({FDR[5],FDR[1]} == b'00) –

1({FDR[5],FDR[1]} == b'01))

—

CLKs

1, 2, 5

5

SCL/SDA fall time (from 2.4 to

0.5 V)

—

<5

ns

4

6

7

Clock high time

D_FDR/2

—

CLKs

1, 2, 5

1, 5

Data setup time (MPC107 as a

master only)

(D_FDR/2) – (Output data hold time)

8

Start condition setup time (for

repeated start condition only)

D_FDR+ (Output start condition hold time)

4.0

—

CLKs

1, 2, 5

1, 2

9

Stop condition setup time

Notes:

1. Units for these specifications are in SDRAM_CLK/CPU_CLK units.

2. The actual values depend on the setting of the digital filter frequency sampling rate (DFFSR) bits in the frequency

divider register I2CFDR. Therefore, the noted timings in this table are all relative to qualified signals. The qualified

SCL and SDA are delayed signals from what is seen in real time on the I²C bus. The qualified SCL, SDA signals

are delayed by the SDRAM_CLK/CPU_CLK clock times DFFS times two plus one SDRAM_CLK/CPU_CLK clock.

The resulting delay value is added to the value in this table where this note is referenced). See Figure 16.

3. Since SCL and SDA are open-drain type outputs, which the MPC107 can only drive low, the time required for SCL

or SDA to reach a high level depends on external signal capacitance and pull-up resistor values.

4. Specified at a nominal 50 pF load.

5. D_FDRis the decimal divider number indexed by FDR[5:0] value. Refer to the I²C Interface chapter’s serial bit clock

frequency divider selections table. FDR[n] refers to the frequency divider register I2CFDR bit n. N is equal to a

variable number that would make the result of the divide (data hold time value) equal to a number less than 16. M

is equal to a variable number that would make the result of the divide (data hold time value) equal to a number less

than 9.

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MPC107 PCI Bridge/Memory Controller Hardware Specifications

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Electrical and Thermal Characteristics

2

Figure 15 through Figure 18 show I C timings.

2

VM

SCL

SDA

6

4

1

Figure 15. I²C Timing Diagram I

3

5

V_H

VM

SCL

SDA

V_L

8

9

Figure 16. I²C Timing Diagram II

DFFSR Filter Clock

SDA

7

Input Data Valid

Note: DFFSR filter clock is the SDRAM_CLK/CPU_CLK clock times DFFSR value.

Figure 17. I²C Timing Diagram III

VM

SCL/SDA_realtime

Delay

SCL/SDA_qualified

VM

Note: The delay is the local memory clock times DFFSR times two plus one local memory clock.

Figure 18. I²C Timing Diagram IV (Qualified Signal)

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Electrical and Thermal Characteristics

1.4.2.6 PIC Serial Interrupt Mode AC Timing Specifications

Table 15 provides the PIC serial interrupt mode AC timing specifications for the MPC107.

Table 15. PIC Serial Interrupt Mode AC Timing Specifications

At recommended operating conditions (see Table 2) with LV = 3.3 V ± 0.3 V

DD

Num

Characteristic

S_CLK frequency

Min

Max

Unit

Notes

1

2

3

4

5

1/14 SDRAM_SYNC_IN

1/2 SDRAM_SYNC_IN

MHz

%

1

S_CLK duty cycle

S_CLK output valid time

Output hold time

40

—

0

60

6

ns

—

ns

S_FRAME, S_RST output valid

time

—

1 sys_logic_clk period + 6

ns

2

6

7

S_INT input setup time to

S_CLK

1 sys_logic_clk period + 2

—

0

ns

S_INT inputs invalid (hold time)

to S_CLK

—

Notes:

1. See the MPC107 PCI Bridge/Memory Controller User’s Manual for a description of the PIC interrupt control

register (ICR) describing S_CLK frequency programming.

2. S_RST, S_FRAME, and S_INT shown in Figure 19 and Figure 20 depict timing relationships to sys_logic_clk and

S_CLK and do not describe functional relationships between S_RST, S_FRAME, and S_INT. See the MPC107

PCI Bridge/Memory Controller User’s Manual for a complete description of the functional relationships between

these signals.

3. The sys_logic_clk waveform is the clocking signal of the internal peripheral logic from the output of the peripheral

logic PLL; sys_logic_clk is the same as SDRAM_SYNC_IN when the SDRAM_SYNC_OUT to SDRAM_SYNC_IN

feedback loop is implemented and the DLL is locked. See the MPC107 PCI Bridge/Memory Controller User’s

Manual for a complete clocking description.

Figure 18 and Figure 19 show the PIC serial interrupt mode output and input timing diagrams, respectively.

VM

sys_logic_clk

3

4

VM

S_CLK

VM

5

4

S_FRAME

S_RST

VM

Figure 19. PIC Serial Interrupt Mode Output Timing Diagram

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MPC107 PCI Bridge/Memory Controller Hardware Specifications

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Electrical and Thermal Characteristics

VM

S_CLK

S_INT

7

6

Figure 20. PIC Serial Interrupt Mode Input Timing Diagram

1.4.2.7 IEEE 1149.1 (JTAG) AC Timing Specifications

Table 16 provides the JTAG AC timing specifications for the MPC107 while in the JTAG operating mode.

Table 16. JTAG AC Timing Specification (Independent of PCI_SYNC_IN)

At recommended operating conditions (see Table 2) with LV = 3.3 V ± 0.3 V

DD

Num

Characteristic ¹

TCK frequency of operation

Min

Max

Unit

Notes

0

40

20

0

25

—

3

MHz

ns

1

TCK cycle time

2

TCK clock pulse width measured at 1.5 V

TCK rise and fall times

3

4

TRST setup time to TCK falling edge

TRST assert time

10

5

—

30

—

15

2

5

6

7

Boundary scan input data setup time

Boundary scan input data hold time

TCK to output data valid

3

4

15

0

8

9

TCK to output high impedance

TMS, TDI data setup time

TMS, TDI data hold time

0

10

5

11

15

0

12

TCK to TDO data valid

13

TCK to TDO high impedance

0

Notes:

1. Timings are independent of the system clock (PCI_SYNC_IN).

2. TRST is an asynchronous signal. The setup time is for test purposes only.

3. Non-test (other than TDI and TMS) signal input timing with respect to TCK.

4. Non-test (other than TDO) signal output timing with respect to TCK.

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Electrical and Thermal Characteristics

Figure 21 shows the JTAG clock input timing diagram.

1

2

VM

TCK

3

VM = Midpoint Voltage

Figure 21. JTAG Clock Input Timing Diagram

Figure 22 shows the JTAG TRST timing diagram.

TCK

4

TRST

5

Figure 22. JTAG TRST Timing Diagram

Figure 23 shows the JTAG boundary scan timing diagram.

TCK

6

7

Data Inputs

Input Data Valid

8

9

Data Outputs

Output Data Valid

Figure 23. JTAG Boundary Scan Timing Diagram

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MPC107 PCI Bridge/Memory Controller Hardware Specifications

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Package Description

Figure 24 shows the test access port timing diagram.

TCK

10

11

TDI, TMS

Input Data Valid

12

TDO

Output Data Valid

13

TDO

Figure 24. Test Access Port Timing Diagram

1.5 Package Description

This section details the MPC107 package parameters, pin assignments, and dimensions.

1.5.1 Package Parameters

The MPC107 uses a 33 mm × 33 mm, 503-pin flip chip plastic ball grid array (FC-PBGA) package. The

plastic package parameters are as provided in the following list.

Package outline

Interconnects

33 mm × 33 mm

503

Pitch

1.27 mm

Solder attach

62 Sn/36 Pb/2 Ag

Solder balls

62 Sn/36 Pb/2 Ag

Solder ball diameter

Maximum module height

Co-planarity specification

Maximum force

0.60–0.90 mm

2.75 mm

0.20 mm

6.0 lbs. total, uniformly distributed over package (5.4 grams/ball)

1.5.2 Pin Assignments and Package Dimensions

Figure 25 shows the top surface, side profile, and pinout for the MPC107, 503 FC-PBGA package.

MOTOROLA

MPC107 PCI Bridge/Memory Controller Hardware Specifications

29

Package Description

Bottom View

Side View

MILLIMETERS

DIM

A

MIN

—

MAX

2.75

0.70

1.20

0.80

0.90

A1

A2

A3

A4

b

0.50

1.00

—

0.82

0.60

D

33 BSC

30.48 BSC

NOTES:

D1

D2

D3

D4

e

1. DIMENSIONS AND TOLERANCING PER

ASME Y14.5M-1994.

—

12.50

—

2. DIMENSIONS IN MILLIMETERS.

3. MAXIMUM SOLDER BALL DIAMETER

MEASURED PARALLEL TO DATUM A.

4. DIMENSIONS DEFINE THE AREA

OCCUPIED BY THE DIE AND UNDERFILL.

ACTUAL SIZE OF THIS AREA MAY BE

SMALLER THAN SHOWN.

3.43

5.00

—

1.27 BSC

E

33 BSC

E1

E2

E3

E4

30.48 BSC

—

14.50

—

3.43

9.00

—

Figure 25. MPC107 Package Dimensions and Pinout Assignments

MPC107 PCI Bridge/Memory Controller Hardware Specifications

30

MOTOROLA

Package Description

1.5.3 Pinout Listings

Table 17 provides the pinout listing for the MPC107, 503 FC-PBGA package.

Table 17. MPC107 Pinout Listing

Supply

Voltage

Output

Notes

Name

Pin Number

Type

Driver Type

60x Processor Interface Signals

A[0:31]

AE22, AE16, AA14, AE17,

I/O

BV_DD

DRV_CPU

4

AD21, AD14, AD20, AB16,

AB20, AB15, AA20, AD13, Y15,

AE12, AD15, AB9, AB14, AA8,

AC13, Y12, Y11, AE15, AE13,

AA16, Y13, AB8, AD12, AE10,

AB13, Y9, Y8, AD9

AACK

ARTRY

BG0

AC7

Output

I/O

BV_DD

DRV_CPU

—

Y7

15

10

AE11

AD11

AB17

Y14

Output

Input

I/O

BG1

BR0

BR1

—

CI

AD16

AC10

AD10

AB10

DRV_CPU

DBG0

DBG1

DBGLB

DH[0:31]

Output

I/O

P1, R1, P2, T4, T1, T3, R4, P6,

U6, V5, V2, T5, U1, R6, W1, V4,

W2, U4, T2, V6, W3, W5, Y1, Y2,

Y4, Y5, AA1, AA2, AA4, AB1,

AB3, AB4

4

DL[0:31]

AA7, W6, AB6, AA6, AB5, AC4,

AD3, AB7, AE1, W4, N6, M1, N3,

N4, N5, N1, M2, R2, V1, P5, P4,

N2, U2, AE4, AE6, AE2, AE3,

AE7, AD5, AB2, AC2, AC1

I/O

BV_DD

DRV_CPU

DP[0:7]

GBL

AE9, AD6, AD8, AD1, AE8, AD7,

AD4, AE5

BV_DD

AD17

Y17

I/O

Input

I/O

BV_DD

DRV_CPU

—

LBCLAIM

TA

AE14

AE21

DRV_CPU

15

TBST

I/O

MOTOROLA

MPC107 PCI Bridge/Memory Controller Hardware Specifications

31

Package Description

Table 17. MPC107 Pinout Listing (continued)

Supply

Output

Driver Type

Name

Pin Number

Type

Notes

Voltage

TEA

AB11

AA10

Output

I/O

BV_DD

DRV_CPU

TS

15

4

TSIZ[0:2]

TT[0:4]

WT

AE19,AD18,AB18

AD19,AC19,AB19,AA19,AA18

AC16

I/O

4

I/O

PCI Interface Signals

AD[31:0]

N23, N21, M20, M21, M22, M24,

I/O

OV_DD

DRV_PCI

4, 11

M25, L20, L22, K25, K24, K23,

K21, J20, J24, J25, H20, F24,

E25, F21, E24, E22, D25, A25,

B25, A23, B23, B22, C22, C25,

D23, D21

C/BE[3:0]

DEVSEL

FRAME

GNT[4:0]

IDSEL

INTA

L24, J22, G22, A24,

I/O

OV_DD

DRV_PCI

—

4, 11

6, 11

4, 11

G23

G20

I/O

T24, P22, P21, R22, N20

Output

Input

Output

I/O

L25

V21

DRV_PCI

—

6, 11, 12

6, 11

6

IRDY

H24

LOCK

G21

Input

I/O

PAR

G24

DRV_PCI

—

11

PERR

G25

I/O

6, 11, 13

10

REQ[4:0]

SERR

W25, V25, U25, T25, T23

Input

I/O

F25

H21

H25

DRV_PCI

6, 11, 12

6, 11

STOP

I/O

TRDY

I/O

Memory Interface Signals

AS

A4

Output

GV_dd

DRV_MEM_CTRL

CAS/DQM[0:7]

A2, B1, A11, A10, B3, C2, F12,

D11

Output

4

CKE

FOE

A12

A13

Output

I/O

GV_dd

DRV_MEM_CTRL

1

1, 2

32

MPC107 PCI Bridge/Memory Controller Hardware Specifications

MOTOROLA

Package Description

Table 17. MPC107 Pinout Listing (continued)

Supply

Output

Notes

Name

MDH[0:31]

Pin Number

Type

Voltage

Driver Type

M6, L4, L6, K2, K4, K5, J4, J6,

H4, H5, G3, G5, G6, F5, F1, E1,

B14, D15, B15, E16, D16, C16,

D18, D17, B17, F18, E19, E20,

B19, B20, B21, A22

I/O

GV_DD

DRV_MEM_DATA

4

MDL[0:31]

M5, L1, L2, K1, K3, J1, J2, H1,

H2, H6, G2, G4, F4, G1, F2, E2,

F14, F15, A16, F17, B16, A17,

A18, A19, B18, E18, D19, F19,

A20, C19, D20, A21

I/O

GV_DD

DRV_MEM_DATA

3, 4

PAR/AR[0:7]

RAS/CS[0:7]

D2, C1, A15, A14, D1, D3, F13,

C13

I/O

GV_DD

DRV_MEM_DATA

DRV_MEM_ADDR

4

E6, C4, D5, E4, C10, F11, B10,

B11

Output

RCS0

D10

B9

B5

D7

A9

A8

D4

I/O

GV_DD

DRV_MEM_ADDR

DRV_MEM_DATA

DRV_MEM_ADDR

1, 2

RCS1

Output

RCS2

RCS3

SDBA0

SDBA1

SDCAS

SDMA [13:0]

1, 2

1

E10, F9, D9, F8, E8, D8, B8, E7,

C7, B7, A7, B6, A6, A5

4, 5

SDRAS

WE

B4

A3

Output

GV_DD

DRV_MEM_ADDR

1

PIC Control Signals

INT

Y22

U24

C24

T21

U20

V22

Output

Input

I/O

OV_DD

DRV_CPU

—

16

IRQ_0/S_INT

IRQ_1/S_CLK

IRQ_2/S_RST

IRQ_3/S_FRAME

IRQ_4/L_INT

DRV_PCI

I/O

MOTOROLA

MPC107 PCI Bridge/Memory Controller Hardware Specifications

33

Package Description

Table 17. MPC107 Pinout Listing (continued)

Supply

Output

Driver Type

Name

Pin Number

Type

Notes

Voltage

I²C Control Signals

SCL

SDA

AB25

AB24

I/O

OV_DD

DRV_CPU

8, 12

Clock Signals

CKO

V20

Output

Input

OV_DD

BV_DD

OV_DD

GV_DD

DRV_PCI

DRV_CPU_CLK

—

CPU_CLK[0:2]

OSC_IN

AA12, AA13, AB12

U22

4

PCI_CLK [0:4]

PCI_SYNC_IN

PCI_SYNC_OUT

SDRAM_CLK [0:3]

SDRAM_SYNC_IN

SDRAM_SYNC_OUT

R25, P24, R24, N24, N25

Output

Input

DRV_MEM_CTRL

—

P20

P25

Output

Input

DRV_MEM_CTRL

—

D14, D13, E12, E14

4

E13

D12

Output

DRV_MEM_CTRL

Miscellaneous Signals

HRESET

HRESET_CPU

MCP

AA23

AB21

AE20

AC25

AE18

M4

Input

Output

Input

OV_DD

BV_DD

OV_DD

BV_DD

—

DRV_CPU

—

10, 12

12, 16

NMI

QACK

Output

Input

DRV_CPU

—

10

QREQ

SRESET

Y18

Output

DRV_CPU

Test/Configuration Signals

PLL_CFG[0:3]

TCK

AC22, AD23, AD22, AE23

Input

Output

Input

Output

OV_DD

GV_DD

OV_DD

—

2,4

W24

Y25

W23

AA25

V24

D6

—

7, 10

TDI

—

TDO

DRV_PCI

TEST

—

7, 10

8

TEST1

TEST2

TMS

—

9

Y24

W22

W21

7,10

TRIG_IN

TRIG_OUT

—

DRV_CPU

10

34

MPC107 PCI Bridge/Memory Controller Hardware Specifications

MOTOROLA

Package Description

Table 17. MPC107 Pinout Listing (continued)

Supply

Output

Notes

Name

Pin Number

Type

Voltage

Driver Type

TRST

AA24

AE24

Input

OV_DD

—

7, 10, 14

—

Power and Ground Signals

AV_DD

GND

Input

—

AA21, AB22, AC11, AC14, AC17,

AC20, AC23, AC3, AC5, AC8,

AD24, AE25, C12, C15, C18,

C21, C23, C3, C6, C9, E3, F10,

F16, F20, F23, F6, G11, G13,

G15, G18, G8, H19, H3, H7, J23,

K20, K6, L19, L3, L7, M23, N19,

N7, P3, R19, R23, R7, T20, T6,

U3, V19, V23, V7, W11, W13,

W15, W18, W8, Y10, Y16, Y19,

Y20, Y3, Y6

Input

GV_DD

B2, C5, C8, C11, C14, C17, C20,

E5, E9, E11, E15, E17, F3, G7,

G9, G12, G14, G17, G19, J3, J5,

J7, L5, M3, M7

Input

—

LAV_DD

LV_DD

F7

Input

—

D22, F22, H22, K22, N22, T22

OV_DD

B24, E21, E23, H23, J19, J21,

L21, L23, M19, P19, P23, R21,

U19, U21, U23, Y23

BV_DD

P7, R3, R5, U5, U7, V3, W7, W9,

W12, W14, W17, AA3, AA5, AA9,

AA11, AA15, AA17, AC6, AC9,

AC12, AC15, AC18, AC21, AD2

Input

—

V_DD

K19, W16, T19, G10, G16, K7,

T7, W10, W19, W20, Y21, AA22,

AB23, AC24, AD25

MOTOROLA

MPC107 PCI Bridge/Memory Controller Hardware Specifications

35

Package Description

Table 17. MPC107 Pinout Listing (continued)

Supply

Output

Driver Type

Name

Pin Number

Type

Notes

Voltage

Manufacturing Pins

FTP[2:3]

MTP[1:2]

Notes:

R20, D24

B12, B13

I/O

OV_DD

GV_DD

DRV_PCI

4, 8

4, 9

DRV_MEM_CTRL

1. This pin has an internal pull-up resistor which is enabled only when the MPC107 is in reset state. The value of the

internal pull-up resistor is not guaranteed, but is sufficient to ensure that a logic 1 is read into configuration bits

during reset.

2. This pin is a reset configuration pin.

3. MDL[0] is a reset configuration pin and has an internal pull-up resistor which is enabled only when the MPC107 is

in the reset state.The value of the internal pull-up resistor is not guaranteed, but is sufficient to ensure that a

logic 1 is read into configuration bits during reset.

4. Multi-pin signals such as AD[0:31] or DL[0:31] have their physical package pin numbers listed in order

corresponding to the signal names. Ex: AD0 is on pin D21, AD1 is on pin D23, ..., AD31 is on pin N23.

5. SDMA[10:1] are reset configuration pins and have internal pull-up resistors which are enabled only when the

MPC107 is in the reset state.The values of the internal pull-up resistors is not guaranteed, but are sufficient to

ensure that logic 1s are read into the configuration bits during reset.

6. Recommend a weak pull-up resistor (2–10 kΩ) be placed on this PCI control pin to LV_DD

.

7. V_IHand V_ILfor these signals are the same as the PCI V_IHand V_ILentries in Table 3.

8. Recommend a weak pull-up resistor (2–10 kΩ) be placed on this pin to OV_DD

9. Recommend a weak pull-up resistor (2–10 kΩ) be placed on this pin to GV_DD

.

10. This pin has an internal pull-up resistor; the value of the internal pull-up resistor is not guaranteed, but is sufficient

to prevent unused inputs from floating.

11. This pin is affected by programmable PCI_HOLD_DEL parameter, see Section 1.4.2.4, “PCI Signal Output Hold

Timing.”

12. This pin is an open drain signal.

13. This pin is a sustained three-state pin as defined by the PCI Local Bus Specification.

14. See Section 1.7.3, “Connection Recommendations,” for additional information on this pin.

15. Recommend a weak pull-up resistor (2–10 kΩ) be placed on this pin to BV_DD

.

16. If BV_DD= 2.5 V ± 5%, this microprocessor interface pin needs to be DC voltage level shifted from OV_DD(3.3 V

± 0.3 V) to 2.5 V ± 5%; this can typically be accomplished with a two resistor voltage divider circuit since the

signal is an output only signal.

36

MPC107 PCI Bridge/Memory Controller Hardware Specifications

MOTOROLA

PLL Configuration

1.6 PLL Configuration

The MPC107 internal PLL is configured by the PLL_CFG[0:3] signals. For a given PCI_SYNC_IN (PCI

bus) frequency, the PLL configuration signals set the core/memory/processor PLL (VCO) frequency of

operation for the PCI-to-core/memory/processor frequency multiplying, if any. All valid PLL

configurations for the MPC107 are shown in Table 18. Range values are shown rounded down to the nearest

whole number (decimal place accuracy removed) for clarity.

Table 18. MPC107 Bridge Controller PLL Configuration

66 MHz Part

100 MHz Part

PCI_

SYNC_IN

Range

PCI_

SYNC_IN

Range

PCI:Core

Ratio

VCO

Multiplier

Ref

PLL_CFG[0:3] ²

Core/Mem/

CPU Range

(MHz)

Core/Mem/

CPU Range

(MHz)

1

0001

0010

0011

0101

1000

1001

1010

1100

1101

1111

25 ⁴–33 ⁵

13 ⁴–16 ⁵

25–33

26–34

25 ⁴–50 ⁵

13 ⁴–25 ⁵

25–50

26–50

1

4

2

4

3

Bypass

5

25 ⁴–33 ⁷

17 ⁴–22 ⁷

34 ⁴–44 ⁷

13 ⁴–16 ⁷

20 ⁴–26 ⁷

50 ⁴–66 ⁶

Clock off ³

50–66

51–66

25 ⁴–50 ⁷

17 ⁴–33 ⁷

33 ⁴–66 ⁶

13 ⁴–25 ⁷

20 ⁴–40 ⁷

50 ⁴–66 ⁶

Clock off ³

50–100

52–100

50–100

50–66

2

3

2

8

9

51–66

1.5

4

2

A

52–64

2

C

D

50–65

2.5

1

2

50–66

2

F

Not usable

Off

Notes:

1. PLL_CFG[0:3] settings not listed (0000, 0100, 0110, 0111, 1011, and 1110) are reserved.

2. In PLL bypass mode, the PCI_SYNC_IN input signal clocks the internal core directly, the PLL is disabled, and the

PCI:core mode is set for 1:1 mode operation. The AC timing specifications given in this document do not apply in

PLL bypass mode.

3. In clock off mode, no clocking occurs inside the MPC107 regardless of the PCI_SYNC_IN input.

4. Limited due to minimum memory VCO (100 MHz).

5. Limited due to maximum memory VCO = (2x maximum memory bus speed).

6. Limited by maximum PCI bus speed (66 MHz).

7. Limited by maximum memory bus speed.

1.7 System Design Information

This section provides electrical and thermal design recommendations for successful application of the

MPC107.

1.7.1 PLL Power Supply Filtering

The AV

and LAV

power signals are provided on the MPC107 to provide power to the peripheral

DD

logic/memory bus PLL and the SDRAM clock delay-locked loop (DLL), respectively. To ensure stability

of the internal clocks, the power supplied to the AV and LAV input signals should be filtered of any

DD

MOTOROLA

MPC107 PCI Bridge/Memory Controller Hardware Specifications

37

System Design Information

noise in the 500-kHz to 10-MHz resonant frequency range of the PLLs. A separate circuit similar to the one

shown in Figure 26 using surface mount capacitors with minimum effective series inductance (ESL) is

recommended for each of the AV and LAV power signal pins. Consistent with the recommendations

DD

of Dr. Howard Johnson in High Speed Digital Design: A Handbook of Black Magic (Prentice Hall, 1993),

multiple small capacitors of equal value are recommended over using multiple values.

The circuits should be placed as close as possible to the respective input signal pins to minimize noise

coupled from nearby circuits. Routing directly as possible from the capacitors to the input signal pins with

minimal inductance of vias is important but proportionately less critical for the LAV pin.

DD

10 Ω

V_DD

AV_DDor LAV_DD

2.2 µF

Low ESL Surface Mount Capacitors

GND

Figure 26. PLL Power Supply Filter Circuit

1.7.2 Decoupling Recommendations

Due to the MPC107 dynamic power management feature, large address and data buses, and high operating

frequencies, the MPC107 can generate transient power surges and high frequency noise in its power supply,

especially while driving large capacitive loads. This noise must be prevented from reaching other

components in the MPC107 system, and the MPC107 itself requires a clean, tightly regulated source of

power. Therefore, it is recommended that the system designer place at least one decoupling capacitor at each

V

, OV , GV , and LV pin of the MPC107. It is also recommended that these decoupling capacitors

DD

DD DD DD

receive their power from separate V , OV , GV , and GND power planes in the PCB, utilizing short

DD

traces to minimize inductance. These capacitors should have a value of 0.1 µF. Only ceramic SMT (surface

mount technology) capacitors should be used to minimize lead inductance, preferably 0508 or 0603,

oriented such that connections are made along the length of the part.

In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB,

feeding the V , OV , GV , BV , and LV planes to enable quick recharging of the smaller chip

DD

capacitors. These bulk capacitors should have a low ESR (equivalent series resistance) rating to ensure the

quick response time necessary. They should also be connected to the power and ground planes through two

vias to minimize inductance. Suggested bulk capacitors: 100–330 µF (AVX TPS tantalum or Sanyo

OSCON).

1.7.3 Connection Recommendations

To ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal

level. Unused active low inputs should be tied to OV . Unused active high inputs should be connected to

DD

GND. All NC (no-connect) signals must remain unconnected.

Power and ground connections must be made to all external V , OV , GV , LV , BV , and GND

DD

pins of the MPC107.

The PCI_SYNC_OUT signal is intended to be routed halfway out to the PCI devices and then returned to

the PCI_SYNC_IN input of the MPC107.

The SDRAM_SYNC_OUT signal is intended to be routed halfway out to the SDRAM devices and then

returned to the SDRAM_SYNC_IN input of the MPC107. The trace length may be used to skew or adjust

38

MPC107 PCI Bridge/Memory Controller Hardware Specifications

MOTOROLA

System Design Information

the timing window as needed. Refer to Motorola Application Note AN1849/D, MPC107 Design Guide, for

型号:	XPC107APX66LD
是否Rohs认证：	不符合
生命周期：	Obsolete
IHS 制造商：	MOTOROLA INC
包装说明：	33 X 33 MM, PLASTIC, BGA-503
Reach Compliance Code：	unknown
HTS代码：	8542.39.00.01
风险等级：	5.83
地址总线宽度：	32
边界扫描：	YES
总线兼容性：	PCI; I2C; 60X PROCESSOR
最大时钟频率：	66 MHz
外部数据总线宽度：	64
JESD-30 代码：	S-PBGA-B503
长度：	33 mm
湿度敏感等级：	1
I/O 线路数量：	64
端子数量：	503
封装主体材料：	PLASTIC/EPOXY
封装代码：	BGA
封装形状：	SQUARE
封装形式：	GRID ARRAY
峰值回流温度（摄氏度）：	225
认证状态：	Not Qualified
座面最大高度：	2.75 mm
最大供电电压：	2.625 V
最小供电电压：	2.375 V
标称供电电压：	2.5 V
表面贴装：	YES
技术：	CMOS
端子形式：	BALL
端子节距：	1.27 mm
端子位置：	BOTTOM
处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	33 mm
Base Number Matches：	1

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