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YDA142

D-3D

DIGITAL INPUT STEREO 9.5W DIGITAL AUDIO POWER AMPLIFIER

■Overview

YDA142 (D-3D) is a 12V single supply voltage, high-efficiency digital audio power amplifier IC.

An audio power amplifier with a maximum output of 9.5W (R_L=8Ω) × 2ch or 19W (R_L=4Ω) × 1ch can be configured with

one chip.

YDA142 has a “Pure Pulse Direct Speaker Drive Circuit” that directly drives speakers while reducing distortion of a pulse

output signal and reducing noise on a signal, and it realizes the highest standard low distortion rate characteristics and low

noise characteristics as compared with those of digital amplifier ICs in the same class. The circuit allows you to design a

circuit with as few external parts as possible depending on use conditions because any filter is no longer required.

It is possible to input a left-justified or right-justified 16bit/8bit digital audio signal of 32kHz, 44.1kHz, or 48kHz.

In addition, YDA142 has a gain setting function in 32-level (analog setting) or 8-level (terminal setting).

YDA142 has Over-current Protection function for speaker output terminals, IC Thermal Protection function, POP Noise

Reduction function, and DC Input Detection function as well as Power-down function and Output Disable function.

■Features

・Maximum Output

9.5 W×2ch (V_DDP=12.0V, R_L=8Ω, THD+N=10%, MONO=L, GAIN[2:0]=H,L,L)

19 W×1ch (V_DDP=12.0V, R_L=4Ω, THD+N=10%, MONO=H, GAIN[2:0]=H,L,L)

・Efficiency

90 % (V_DDP=12.0V, R_L=8Ω, Po=9.5W)

・Distortion Rate (THD+N)

0.05 % (V_DDP=12.0V, R_L=8Ω, Po=1.0W, GAIN[2:0]=H,L,L)

・S/N Ratio

100dB (V_DDP=12.0V, R_L=8Ω, Po=9.5W, GAIN[2:0]=H,L,L)

・Channel Separation Ratio

-78dB (V_DDP=12.0V)

・Supply voltage Range

9.0V to 13.5V

・3-wire Digital Signal Input

Fs: 32kHz/44.1kHz or 48kHz, Bits: 16bit or 18bit

・Gain Setting Function with GAIN[2:0] and GAINA terminal

・Power-down Function with SLEEPN terminal

・Output Mute Function with MUTEN terminal

・Monaural Output Function with MONO terminal

・Protection Functions (Over-current Protection, Thermal Protection, Clock Stop protection, Under-voltage Malfunction

Prevention, DC Input Detection)

・Pop-noise Reduction Function

・Digital Input/BTL(Bridge-Tied Load) output

・Package

Lead-free 52-pin SSOP (YDA142-EZ)

YDA142 CATALOG

CATALOG No.:LSI-4DA142A20

2006.4

YDA142

■Terminal configuration

<52-pin SSOP Top View>

2

YDA142

■Terminal function

Voltage

tolerance

LV

－

No.

Name

VREF

I/O

Function

Analog reference voltage output

Ground terminal for analog circuits

Analog gain setting terminal

Lch Line output terminal

Rch Line output terminal

Normally, use this terminal in no-connection

Ground terminal

1

2

3

4

5

6

7

8

O

GND

I

O

－

AVSS

VSSBGR

GAINA

LINEOUTL

LINEOUTR

NC

－

LV

－

HV

－

PVSSR

PVDDR

OUTPR

PVSSR

OUTMR

PVDDR

PVSSR

NC

MUTEN

MONO

DVSS

SDIN

LRCLK

SCLK

MODE0

MODE1

GAIN0

GAIN1

GAIN2

FSSEL

BITSEL

PVSSL

PVDDL

OUTML

PVSSL

OUTPL

PVDDL

PVSSL

NC

GND

9

Ground terminal

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

Power 12V power supply terminal

O

GND

O

Rch positive side output terminal

Ground terminal

Rch negative side output terminal

－

HV

－

LV

－

LV

－

O

Power 12V power supply terminal

GND

－

I

Ground terminal

Normally, use this terminal in no-connection

Output disable control terminal

Monaural control terminal

Ground terminal for digital circuits

Serial audio data signal input

Serial LR clock signal input

Serial bit clock signal input

Mode setting terminal 0

I

GND

I

Mode setting terminal 1

Volume setting terminal 0

Volume setting terminal 1

Volume setting terminal 2

Sampling frequency setting terminal

16bit/18bit setting terminal

Ground terminal

I

GND

Ground terminal

－

Power 12V power supply terminal

O

GND

O

HV

－

Lch negative side output terminal

Ground terminal

Lch positive side output terminal

－

HV

－

O

Power 12V power supply terminal

GND

－

I

Ground terminal

Normally, use this terminal in no-connection

Power-down control terminal

NC

－

SLEEPN

PROTN

PVDDREG

REFA

HV

LV

O/D

Unusual condition warning output terminal

Power 12V power supply terminal for analog circuits

O

I

5V reference voltage output terminal

5V reference voltage input terminal

DVDD

（Note） I: Input terminal, O: Output terminal, O/D: Open drain output terminal

LV: Terminal for V_REGpower supply voltage range as input voltage range.

HV: Terminal for V_DDPpower supply voltage range as input voltage range.

3

YDA142

■Block diagram

4

YDA142

■Description of operating functions

●Serial Audio Interface

Sampling Frequency (Fs) Selection

Input an audio signal using SCLK, LRCLK, and SDIN terminals. YDA142 supports three sampling frequencies (Fs):

32kHz, 44.1kHz, and 48kHz. Set the FSSEL terminal as follows in accordance with a Fs of a signal to use. At this time, use

a frequency of 64Fs as a SCLK signal.

FSSEL terminal setting

FSSEL

Sampling Frequency (Fs)

44.1kHz, 48kHz

32kHz

L

H

Bit Number Selection

YDA142 supports two bit widths: 16-bit and 18-bit. Set the BITSEL terminal as follows in accordance with a bit width to

use.

BITSEL terminal setting

BITSEL

Input Bit Number

16 bits

L

H

18 bits

Format Selection

YDA142 can select one out of three interface formats: Right-justified MSB first format, Left-justified MSB first format, and

Left-justified (1bit delay) MSB first format. Set the MODE[1:0] as follows in accordance with a digital audio signal format

to use. Fig.1 to Fig.3 shows the details of each format.

MODE[1:0] terminal setting

MODE1

MODE0

Input Signal Format

Right-justified MSB first

Left-justified MSB first

Left-justified (1bit delay) MSB first

Reserved

L

H

L

H

L

H

Right-justified MSB first

Fig.1 Right-justified MSB First Format

5

YDA142

Left-justified MSB first

Fig.2 Left-justified MSB First Format

Left-justified (1bit delay) MSB first

Fig.3 Left-justified (1bit delay) MSB First Format

6

YDA142

●Gain setting function

The output gain for a digital amplifier and LINEOUTL(R) can be set by GAIN[2:0] terminal and GAINA terminal.

Set the GAIN[2:0] as follows in accordance with a gain to use.

With GAIN[2:0]= “L, L, L” the output gain of a digital amplifier and LINEOUTL(R) can be set by a GAINA terminal

voltage. Set the GAINA terminal voltage as follows in accordance with a gain to use.

When the GAINA terminal is not used, it is fixed to GND.

GAIN[2:0] terminal gain setting

GAIN2

GAIN1

GAIN0

Digital Amplifier

Gain

GAINA terminal

priority

2dB

LINEOUTL(R)

Output Gain

GAINA terminal

priority

-15dB

L

H

L

H

L

H

L

H

L

H

L

H

8dB

14dB

20dB

23dB

26dB

29dB

-9dB

-3dB

3dB

6dB

9dB

12dB

GAINA terminal Gain setting

GAINA terminal voltage range

(Voltage ratio to REFA voltage)

Digital Amplifier

Gain

LINEOUTL(R)

Output Gain

15dB

65.6%

64.0%

62.4%

60.8%

59.2%

57.6%

56.0%

54.4%

52.8%

51.2%

49.6%

48.0%

46.4%

44.8%

43.2%

41.6%

40.0%

38.4%

36.8%

35.2%

33.6%

32.0%

30.4%

28.8%

27.2%

25.6%

24.0%

22.4%

20.8%

19.2%

17.6%

0%

to

100.0%

67.2%

65.6%

64.0%

62.4%

60.8%

59.2%

57.6%

56.0%

54.4%

52.8%

51.2%

49.6%

48.0%

46.4%

44.8%

43.2%

41.6%

40.0%

38.4%

36.8%

35.2%

33.6%

32.0%

30.4%

28.8%

27.2%

25.6%

24.0%

22.4%

20.8%

19.2%

32dB

29dB

26dB

23dB

20dB

18dB

16dB

14dB

12dB

10dB

8dB

6dB

4dB

2dB

0dB

-2dB

-4dB

-6dB

-8dB

-10dB

-12dB

-14dB

-16dB

-18dB

-20dB

-23dB

-26dB

-29dB

-32dB

-36dB

-40dB

Mute

12dB

9dB

6dB

3dB

1dB

-1dB

-3dB

-5dB

-7dB

-9dB

-11dB

-13dB

-15dB

-17dB

-19dB

-21dB

-23dB

-25dB

-27dB

-29dB

-31dB

-33dB

-35dB

-37dB

-40dB

-43dB

-46dB

-49dB

-53dB

-57dB

Mute

A full scale of DAC is 1Vrms(2.8Vpp). This is assumed to be 0dB and the gain is set.

For instance, when the gain of a digital amplifier is set to 14dB, and a full-scale signal of DAC is input, the digital amplifier

output becomes 5Vrms(14Vpp).

7

YDA142

●Analog Signal Output

When SLEEPN terminal is “H”, L channel and R channel analog signals are output from LINEOUTL terminal and

LINEOUTR terminal respectively, with an output gain designated by GAIN[2:0] terminal or GAINA terminal with respect

to an input digital signal.

The DC component is superimposed and output from LINEOUTL and LINEOUTR terminal. Therefore, the DC component

is removed with the DC cut capacitor.

●Digital Amplifier Output

When SLEEPN terminal is “H” and MUTEN terminal is “H”, L channel signal is output between OUTPL terminal and

OUTML terminal, with an output gain designated by GAIN[2:0] terminal or GAINA terminal with respect to an input

digital signal. In addition, R channel signal is output between OUTPR terminal and OUTMR terminal. OUTPL and OUTPR

terminal become a positive terminal, and OUTML and OUTMR terminals become a minus terminal, respectively.

LC Filter

YDA142 can be directly connected to a speaker without a LC filter because it adopts a modulation method capable of

reducing speaker loss during no sound sufficiently by utilizing only inductance a speaker has. When a LC filter is not used,

use a speaker with inductance of 20µH or over at a carrier clock frequency of 500kHz.

Use the following filter circuit when a LC filter is connected. At this time, use the following constants in accordance with

speaker's impedance. Using these constants can make a low-pass filter with a cut-off frequency of 50kHz, Q=0.7 or so.

The over current protection function might work by LC resonance when the LC filter is connected and uses, and operate IC

without connecting the speaker.

LC Filter constants

RL

4Ω

8Ω

L1

C1

10µH

22µH

47µH

1.0µF

0.47µF

0.22µF

16Ω

●Control Function

Sleep Function

When SLEEPN terminal is “L”, YDA142 enters Sleep Mode.

The mode stops all the circuit functions including 5V Regulator and minimizes consumption current. At this time, the

output stage of the digital amplifier is disabled and LINEOUTL and LINEOUTR terminals get undefined. And, PROTN

terminal becomes “High-Z”.

Mute Function

When MUTEN terminal is “L”, YDA142 enters Mute Mode.

In this mode, the output stage of the digital amplifier is disabled and LINEOUTL and LINEOUTR terminals output audio

signals normally.

8

YDA142

Monaural Function

When MONO terminal is “H”, YDA142 enters Monaural Mode.

In this mode, L channel input signal is output.

The mode can output up to 19W power into a 4Ω load resistor by short-circuiting between OUTPL and OUTPR terminals

and between OUTML and OUTMR terminals.

In addition, LINEOUTL terminal outputs L channel input signals but LINEOUTR terminal gets undefined.

Switch between Monaural Mode and Stereo Mode during SLEEP Mode or a power shutdown state.

●Protection Function

YDA142 has the following protection functions: Over-current Protection function, Thermal Protection function, Clock Stop

Protection function, Under-voltage Malfunction Prevention function, and DC Input Detection function.

Over-current Protection Function

This is a function to make the Over-current Protection Mode (disables the output stage of a digital amplifier in conjunction

with “L” output to PROTN terminal) by detecting a short-circuiting (Ground short/Power supply short/Short between

terminals) in the output stage of a digital amplifier.

This mode can be cancelled by power supply shutdown or SLEEPN terminal “L” setting.

In addition, the mode can be automatically resumed after the over-current detection by connecting PROTN terminal to

SLEEPN terminal.

Thermal Protection Function

This is a function to make the Thermal Protection Mode (disables the output stage of a digital amplifier in conjunction with

“L” output to PROTN terminal) by detecting extraordinary high temperature on YDA142. This mode can be cancelled by

sufficient temperature decrease, power supply shutdown, or SLEEPN terminal “L” setting.

In addition, the mode can be automatically resumed after the high temperature detection by connecting PROTN terminal

to SLEEPN terminal.

Clock Stop Protection Function

This is a function to make the Clock Stop Protection Function (disables the output stage of a digital amplifier) when a

SCLK signal frequency of the digital interface becomes a frequency lower than Stop Detection Frequency (F_UFP).

The mode can be cancelled by returning the carrier clock frequency to the normal value.

Under-voltage Malfunction Prevention Function

This is a function to make the Under Voltage Protection Function (disables the output stage of a digital amplifier in

conjunction with setting “High-Z” state to PROTN terminal) when a voltage at 12V power supply terminal (PVDDREG)

becomes lower than the Under Voltage Detection Threshold Voltage (V_UVPL) or a voltage at 5V power supply terminal

(DVDD) becomes lower than the Under Voltage Detection Threshold Voltage (V_UVAL).

The built-in 5V regulator is also disabled when a voltage at 12V power supply terminal becomes lower than the Threshold

Voltage V_UVPL

.

The mode can be cancelled when “L” is set to SLEEPN terminal or a voltage of each power supply terminal becomes

higher than the Threshold Voltage (V_UVPH, V_UVAH).

9

YDA142

DC Input Detection Function

This is a function to make the DC Input Protection Mode (disables digital amplifier output stage) when a digital input signal

of the DC input detection voltage level (V_DCIN) or more continues over the DC input detection time (T_DCIN) without change

of polarity.

DC Input Protection Mode is cancelled when “L” is set to SLEEPN terminal or a digital input signal becomes lower than

V

_DCINor its polarity is changed.

●5V Regulator Function

YDA142 outputs 5V (V_REG) to REFA terminal when SLEEPN terminal is “H”. Connect a capacitor of 0.1µF or over to

REFA terminal for stabilization.

Connect the REFA terminal to DVDD terminal on a board.

And, don’t connect the REFA terminal to other terminals except DVDD terminal and YDA142 input terminals.

●Pop-noise Reduction Function

Pop-noise Reduction Function works when powered on, when shut down, when SLEEP ON/OFF is switched, or when

Mute ON/OFF is switched.

●Power dissipation

The power dissipation of YDA142 is limited by ｊunction temperature rating (125℃) and package thermal resistance

(15.4℃/W: 4-layer board).

The power dissipation and junction temperature can be found by the following formula.

When used, take care so that the power dissipation and junction temperature do not exceed the absolute maximum ratings.

・Formula for the power dissipation

Ploss = (Pout × Rpn / Rl) × 2 + Idc × Vdc

9.0

8.0

Ploss

Pout

Rpn

Rl

: Power Dissipation (W)

: Output Power (W)

: 0.66 (constant)

: Load Resistance (Ω)

: 0.035(constant/at V_DDP=12V)

0.028(constant/at V_DDP=9V)

0.038(constant/at V_DDP=13.5V)

: Supply Voltage (V)

7.0

6.0

5.0

4.0

3.0

2.0

1.0

0.0

Idc

Vdc

0

10

20

30

40

50

60

70

80

90

・Formula for the junction temperature

Tj = Ploss × θja + Ta

Ploss

θja

Ta

: Power Dissipation (W)

: 15.4(constant/package thermal resistance (℃/W), 4-layer board)

: Ambient temperature (℃)

●Package thermal resistance

The package (52SSOP) for YDA142 has a Thermal Pad for radiation on the surface. Use this Thermal Pad by soldering on

a board.

The package’s thermal resistance is 15.4℃/W (4-layer board). This thermal resistance is a value measured under the

following conditions: board size 136mm×85mm, 1st layer and 4th layer copper foil board density 154%, 2nd layer and 3rd

layer copper foil board density 200%, no wind. In addition, the lower side pattern of the Thermal Pad is connected to all the

layers in a board by through holes (φ0.4).

10

YDA142

■Example of application circuit

ID

Value

1μF/16V

Element

Multilayer ceramic capacitor

Chip Resistor

C1

C2,C3

C4

C5

0.1μF/16V

1μF/25V

C6,C7,C8,C9

R1

4.7μF/25V

100kΩ, 1/16W

11

YDA142

■Electrical characteristics

Note 6)

●Absolute Maximum Ratings

Item

Symbol

V_DDP

V_IN1

Min.

-0.3

Max.

14.0

Unit

V

Note 1,2,3)

Power Supply Terminal (VDDP) voltage range

SLEEPN, PROTN terminal voltage range

Control line terminal voltage range ^{Note 4)}

Input/Output terminal voltage range ^{Note 5)}

Power Dissipation (Ta=25℃, 4-layer board)

Power Dissipation (Ta=70℃, 4-layer board)

Junction Temperature

V_SS-0.3

V_DDP+0.3

V_REG+0.3

6.4

V

V_IN3

V_IN4

V

P_D25

W

℃

P_D70

3.6

T_JMAX

T_STG

125

Storage Temperature

-50

125

Note 1) VSS means AVSS, VSSBGR, DVSS, PVSSR, and PVSSL. Keep all the VSS terminals at the same potential.

Note 2) The voltage is based on V_SS=0V.

Note 3) The power supply terminal (VDDP) means PVDDREG, PVDDR, and PVDDL terminal.

Note 4) The control input/output terminal means MUTEN, MONO, GAIN[2:0], MODE[1:0], BITSEL, FSSEL, SCLK, LRCLK, and SDIN terminal.

Note 5) The input/output terminal means VREF and GAINA terminal.

Note 6) Absolute Maximum Ratings is values which must not be exceeded to guarantee device reliability and life, and when using a device in excess

even a moment, it may immediately cause damage to device or may significantly deteriorate its reliability.

●Recommended operating condition

Item

Symbol

V_DDP

T_a

Min.

9.0

Typ.

12.0

25

Max.

13.5

85

Unit

V

Note 7)

Supply Voltage

Operating Ambient Temperature

Speaker Impedance (Stereo)

-40

℃

Ω

R_LS

7.5

8

Speaker Impedance (Mono)

R_LM

3.75

4

Ω

Note 7) All the voltages are based on V_SS=0V.

12

YDA142

●DC Characteristics (V_SS=0V, V_DDP=12V±0.5V, Ta=0℃ to 85℃, unless otherwise specified)

Item

REFA output terminal voltage

Symbol

V_REG

V_DVDD

V_OLP

Min.

4.5

Typ.

Max.

5.5

Unit

V

5

DVDD input terminal voltage

4.5

5.5

V

PROTN terminal Low level output voltage (I_OL=1.6mA)

SLEEPN terminal High level input voltage

SLEEPN terminal Low level input voltage

Control line input terminal High Level input voltage

Control line input terminal Low Level input voltage

PVDDREG terminal Startup threshold voltage

PVDDREG terminal Shut-down threshold voltage

DVDD terminal Startup threshold voltage

DVDD terminal Shut-down threshold voltage

DC input detection voltage level

0.4

V

V_IH1

2.2

V

V_IL1

0.8

V

V_IH2

V

V_IL2

V

V_UVPH

V_UVPL

V_UVAH

V_UVAL

V_DCIN

I_SLEEP

I_MUTE

I_DDD

8.0

7.6

3.7

3.3

18

1

V

dBFS

µA

mA

Consumption current (SLEEP Mode)

Consumption current (Mute Mode)

20

40

Consumption current (Silent, without filter)

●AC Characteristic (V_SS=0V, V_DDP=12V±0.5V, Ta=0℃ to 85℃, unless otherwise specified)

Item

Carrier Clock Frequency (Fs=44.1kHz)

Carrier Clock Frequency (Fs=48kHz, 32kHz)

Clock stop detection SCLK signal frequency

DC input detection time

Symbol

F_CK

Min.

Typ.

470

500

400

2

Max.

Unit

kHz

s

F_CK

F_UFP

T_DCIN

T_CYC

T_LRS

T_LRH

T_SDS

T_SDH

1.8

250

60

3.7

SCLK cycle time

600

ns

LRCLK setup time

ns

LRCLK hold time

25

ns

SDIN setup time

60

ns

SDIN hold time

25

ns

13

YDA142

●Analog Characteristics (V_SS=0V, V_DDP=12V, Ta=25℃, Frequency:1kHz, unless otherwise specified)

Item

Conditions

R_L=8Ω

Symbol

Min.

Typ.

9.5

Max.

Unit

W

Maximum output (Stereo)

(THD+N=10%)

P_O

Maximum output (Mono)

(THD+N=10%)

R_L=4Ω

19.0

20

W

dB

%

Voltage Gain (GAIN[2:0]=H,L,L)

Total Harmonic Distortion Rate (Stereo)

(BW: 20kHz)

A_V

R_L=8Ω, P_O=5W

0.05

THD+N

Total Harmonic Distortion Rate (Mono)

(BW: 20kHz)

R_L=4Ω, P_O=9.5W

0.1

%

Signal /Noise Ratio

R_L=8Ω, P_O=9.5W,

SNR

100

dB

(BW: 20kHz A-Filter)

Channel Separation Ratio

Maximum Efficiency

GAIN[2:0]=H,L,L

CS

η

-78

90

dB

%

R_L=8Ω, P_O=9.5W

Output offset voltage

V_O

±20

mV

Note) All the values of analog characteristics were obtained by using our evaluation circumstance.

Depending upon parts and pattern layout to use, characteristics may be changed.

8Ω resistor and 30µH coil are used as an output load in order to obtain various digital amplifier characteristics.

14

YDA142

■Typical characteristics examples

●Digital Amplifier Characteristics (V_DDP=12V, Ta=25℃, R_L=8Ω+30µH, Frequency=1kHz）

Input signal frequency vs THD+N

(Po=3.1W, with 20kHz filter)

Input level vs THD+N

(Freq=1kHz, with 20kHz filter)

100

10

100

10

Lch

Rch

1

0.1

0.01

0.1

0.01

100

1000

10000

100000

-60

-50

-40

-30

-20

-10

0

Input level [dBFS]

FREQ [Hz]

Frequency Response

Noise FFT

0

25

24

23

22

21

20

19

18

17

16

15

Lch

Rch

-20

-40

Rch

-60

-80

-100

-120

-140

-160

10

100

1000

10000

100000

10

100

1000

10000

100000

FREQ [Hz]

Power supply voltage vs Maximum output power

(THD+N=10%, GAIN[2:0]=HHH)

POWER vs Efficiency

14

100

8Ω

16Ω

90

80

70

60

50

40

30

20

10

0

12

10

8

6

4

2

8Ω

16Ω

0

8

9

10

11

12

13

14

15

0

2

4

6

8

10

12

Power supply voltage [V]

POWER [W]

Power supply voltage vs Maximum output power [MONO]

(THD+N=10%, GAIN[2:0]=HHH)

Input level vs THD+N [MONO]

(Freq=1kHz, with 20kHz filter, RL=4ohm)

100

30

NO.1

NO.2

4Ω

8Ω

25

20

15

10

5

16Ω

10

1

0.1

0.01

0

-60

-50

-40

-30

-20

-10

0

8

9

10

11

12

13

14

15

Input level [dBFS]

Power supply voltage [V]

15

YDA142

■Package outline

16

YDA142

17

YDA142

Notice ^{The specifications of this product are subject to improvement changes without prior notice.}

型号:	YDA139-WZ
生命周期：	Obsolete
零件包装代码：	BGA
包装说明：	VFBGA,
针数：	25
Reach Compliance Code：	unknown
ECCN代码：	EAR99
HTS代码：	8542.33.00.01
风险等级：	5.84
商用集成电路类型：	AUDIO AMPLIFIER
增益：	26 dB
JESD-30 代码：	S-XBGA-B25
长度：	2.564 mm
信道数量：	2
功能数量：	1
端子数量：	25
最高工作温度：	85 °C
最低工作温度：	-20 °C
标称输出功率：	2.5 W
封装主体材料：	UNSPECIFIED
封装代码：	VFBGA
封装形状：	SQUARE
封装形式：	GRID ARRAY, VERY THIN PROFILE, FINE PITCH
认证状态：	Not Qualified
座面最大高度：	1 mm
最大供电电压 (Vsup)：	5.25 V
最小供电电压 (Vsup)：	2.7 V
表面贴装：	YES
温度等级：	OTHER
端子形式：	BALL
端子节距：	0.5 mm
端子位置：	BOTTOM
宽度：	2.564 mm
Base Number Matches：	1

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