YMF724F-V应用文章市场行情现货热卖使用介绍供应商报价-中国IC网-芯三七

YMF724F

DS-1

OVERVIEW

YMF724F (DS-1) is a high performance audio controller for the PCI Bus. DS-1 consists of two separated

functional blocks. One is the PCI Audio block and the other is the Legacy Audio block. PCI Audio block

allows Software Driver to handle maximum of 73 concurrent audio streams with the Bus Master DMA engine.

The PCI Audio Engine converts the sampling rate of each audio stream and the streams are mixed without

utilizing the CPU or causing system latency. By using the Software Driver from YAMAHA, PCI Audio

provides 64-voice XG wavetable synthesizer with Reverb and variation. It also supports DirectSound hardware

accelerator, Downloadable Sound (DLS) and DirectMusic accelerator.

Legacy Audio block supports FM Synthesizer, Sound Blaster Pro, MPU401 UART mode and Joystick

function in order to provide hardware compatibility for numerous PC games on real DOS without any software

driver. To achieve legacy DMAC compatibility on the PCI, DS-1 supports both PC/PCI and Distributed DMA

protocols. DS-1 also supports Serialized IRQ for legacy IRQ compatibility.

DS-1 supports the connection to AC’97 which provides high quality DAC, ADC and analog mixing.

In addition, it supports consumer IEC958, Audio Digital Interface (SPDIF) output, for high-quality, external

audio amplification.

FEATURES

• PCI 2.1 Compliant

• Supports PC/PCI and Distributed DMA for legacy

DMAC (8237) emulation

• PC’97/PC’98 specification Compliant

• PCI Bus Power Management rev. 1.0 Compliant

(Support D0, D2 and D3 state)

• PCI Bus Master for PCI Audio

True Full Duplex Playback and Capture with

different Sampling Rate

• Supports Serialized IRQ

• Supports YAMAHA AC-3 device (YMF727 :

AC3F2) interface to enable AC-3 decode

• Supports Consumer IEC958 Output (SPDIF) port

• Supports AC’97 Interface (AC-Link)

• Hardware Volume Control

Maximum 64-voice XG capital Wavetable

Synthesizer including GM compatibility

DirectSound Hardware Acceleration

DirectMusic Hardware Acceleration

Downloadable Sound (DLS) level-1

• Legacy Audio compatibility

• EEPROM Interface

• Single Crystal operation (24.576MHz)

• 5V Power supply for I/O. 3.3V Power supply for

Internal core logic

• 144-pin LQFP (YMF724F-V)

FM Synthesizer

Hardware Sound Blaster Pro compatibility

MPU401 UART mode MIDI interface

Joystick

CORPORATION

YAMAHA

YMF724F CATALOG

^CATS^ALe^Op^Gte^Nm^o.:b^LSe^Ir^-42^M1^F,⁷²1⁴9^F9²8⁰

January 14, 1999

YMF724F

Logos

GENERAL MIDI logo is a trademark of Association of Musical Electronics Industry (AMEI),

and indicates GM system level 1 Compliant.

XG logo is a trademark of YAMAHA Corporation.

SONDIUS-XG logo is a trademark that Stanford University in the United States and

YAMAHA Corporation hold jointly.

Sensaura logo is a trademark of Central Research Laboratories Limited.

1. GM system level 1

GM system level 1 is a world standard format about MIDI synthesizer which provides voice arrangements

and MIDI functions.

2. XG

XG is a format about MIDI synthesizer that is proposed by YAMAHA, and keeps the upper compatibility of

GM system level 1. The good points are the voice arrangements kept extensively, a large number of the

voices, modification of the voices, 3 kinds of effects, and so on.

3. SONDIUS-XG

Products bearing the SONDIUS-XG logo are licensed under patents of Stanford University and YAMAHA

Corporation as listed on <http://www.sondius-xg.com>. The SONDIUS-XG produces acoustic sound

outputs by running a virtual simulation of the actual acoustic instrument operation. Therefore, it provides

much more real-world acoustic sound outputs fundamentally different from the Wavetable sound generator

that simply processes the recorded acoustic sound sources only. The SONDIUS-XG adds the technology

of virtual acoustic sound to the XG format.

4. Sensaura

Sensaura is a technology which provides 3D positional audio and moving effect by HRTF (Head Related

Transfer Function) with 2 speakers or headphone. This feature makes it possible to enjoy invariable and

unchangeable sound feelings in all-positional area covering as wide as 360 degrees.

January 14, 1999

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YMF724F

PIN CONFIGURATION

YMF724F-V

GP4

GP5

1

2

3

4

5

6

7

8

108

107

106

105

104

103

102

101

100

99

XRST#

ACS#

ACDO

ACDI

ASCLK

ASDO

ABCLK

ALRCK

VSS

GP6

GP7

RXD

TXD

ROMDO/VOLDW#

ROMSK/VOLUP#

VDD5

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

VSS

VDD3

VSS

IRQ5

IRQ7

IRQ9

IRQ10

IRQ11

INTA#

VSS

RST#

VDD5

PVSS

PCICLK

PVDD

98

VDD3

VDD5

PVDD

NC

PCREQ#

PCGNT#

SERIRQ#

AD0

97

96

95

94

93

92

91

90

89

88

87

86

85

84

83

82

81

80

79

AD1

PVSS

AD2

AD3

AD4

PVSS

AD5

GNT#

REQ#

AD31

AD30

AD29

PVSS

AD28

AD27

AD26

PVSS

AD25

AD6

AD7

PVSS

PVDD

CBE0#

AD8

78

77

76

75

74

73

AD9

PVSS

AD10

AD11

AD12

AD24

144 Pin LQFP Top View

January 14, 1999

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YMF724F

PIN DESCRIPTION

1. PCI Bus Interface (53-pin)

name

PCICLK

I/O

Type

Size

function

I

P

PCI Clock

Reset

RST#

I

P

AD[31:0]

C/BE[3:0]#

PAR

IO

I

Ptr

Pstr

P

Address / Data

Command / Byte Enable

Parity

FRAME#

IRDY#

Frame

Initiator Ready

Target Ready

Stop

TRDY#

STOP#

IDSEL

ID Select

DEVSEL#

REQA#

GNTA#

PCREQ#

PCGNT#

PERR#

IO

O

Pstr

P

Device Select

PCI Request

I

P

PCI Grant

O

Ptr

Pstr

Pod

Ptr

PC/PCI Request

PC/PCI Grant

Parity Error

I

IO

O

SERR#

System Error

Interrupt signal output for PCI bus

Serialized IRQ.

INTA#

O

SERIRQ#

IO

2. AC’97 Interface (6-pin)

Name

I/O

Type

Size

function

CRST#

O

T

C

6mA

-

Reset signal for AC’97

CMCLK

Master Clock of AC link (24.576MHz) and

AC3F2

CBCLK

CSDO

CSDI

I

O

I

T

-

AC-link: Bit Clock for AC’97 audio data

AC-link: AC’97 Serial audio output data

AC-link: AC’97 Serial audio input data

AC-link: Synchronized signal

6mA

-

CSYNC

O

6mA

January 14, 1999

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YMF724F

3. YMF727(AC3F2) Interface (9-pin)

name

I/O

type

size

function

XRST#

ACS#

O

I

C

T

2mA

3mA

6mA

3mA

-

Reset for local device

Chip select for AC3F2

ASCLK

ACDO

ACDI

T

Clock for Serial control data transfer of AC3F2

Serial control data output of AC3F2

Serial control data input of AC3F2

L/R clock for Serial audio data of AC3F2

Bit clock for Serial audio data of AC3F2

Serial audio data output to AC3F2

Mixed Serial audio data input of AC3F2

T

Tup

T

ALRCK

ABCLK

ASDO

ASDI

O

I

3mA

6mA

3mA

-

T

Tup

4. SPDIF Interface (1-pin)

name

I/O

O

type

T

Size

function

DIT

3mA

Digital audio interface output (48kHz)

5. Legacy Device Interface (16-pin)

name

I/O

O

type

Ttr

Size

function

IRQ5

12mA Interrupt5 of Legacy Audio

It is directly connected to the interrupt signal of

System I/O chip.

IRQ7

O

I

Ttr

A

12mA Interrupt7 of Legacy Audio

12mA Interrupt9 of Legacy Audio

12mA Interrupt10 of Legacy Audio

12mA Interrupt11 of Legacy Audio.

IRQ9

IRQ10

IRQ11

GP[3:0]

GP[7:4]

GREF

RXD

-

Game Port

I

Tup

A

-

Game Port

I

-

Reference for Game Port

MIDI Data Receive

MIDI Data Transfer

I

Tup

T

TXD

O

3mA

January 14, 1999

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YMF724F

6. Miscellaneous (15-pin)

name

ROMCS

I/O

O

type

T

Size

function

3mA

Chip select for external EEPROM

Serial clock for external EEPROM

or Hardware Volume (Up)

ROMSK / VOLUP#

ROMDO / VOLDW#

ROMDI / TEST2#

IO

I

Tup

3mA

-

Serial data output for external EEPROM

or Hardware Volume (Down)

Serial data input for external EEPROM or Test pin

(Do not connect externally when EEPROM is not.)

24.576 MHz Crystal

XI24

I

O

I

C

-

2mA

-

XO24

24.576 MHz Crystal

TEST[7:4,1:0]#

TEST3#

Tup

-

Test pins (Do not connect externally)

Test pin (Connect to ground)

IO

-

3mA

-

LOOPF[1:0]

Capacitor of PLL

Note) Hardware volume and EEPROM interface can not be used at the same time. When both hardware

volume and EEPROM are not used, do not connect these pins externally.

7. Power Supply (39-pin)

name

PVDD[5:0]

I/O

type

Size

function

-

Power supply for PCI Bus Interface (+5.0)

Ground for PCI Bus Interface

Power supply for PLL Filter (+3.3)

Ground for PLL Filter

PVSS[14:0]

LVDD

LVSS

VDD3[3:0]

VDD5[3:0]

VSS[7:0]

Power supply (+3.3V)

Power supply (+5.0V)

Ground

TYPE

T : TTL

A : Analog

C : CMOS

P : PCI

Ptr : Tri-State PCI

Ttr : Tri-State TTL

Tup : Pull up (Max. 300kohm) TTL

Pstr : Sustained Tri-Sate PCI

Pod : Open Drain PCI

January 14, 1999

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YMF724F

BLOCK DIAGRAM

PC-PCI /

D-DMA /

S-IRQ

Legacy Audio

AC'97

SB Pro

FM

MPU401

Joystick

Rate Converter

/ Mixer

Interface

SPDIF

(output)

PCI Bus

Interface

BUS Master

PCI Audio

DMA Controller

XG Synthesizer

Direct Sound Acc.

Wave In/Out

AC3F2

Interface

Memory

January 14, 1999

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YMF724F

SYSTEM DIAGRAM

January 14, 1999

-8-

YMF724F

FUNCTION OVERVIEW

1. PCI INTERFACE

DS-1 supports the PCI bus interface and complies to PCI revision 2.1.

1-1. PCI Bus Command

DS-1 supports the following PCI Bus commands.

1-1-1. Target Device Mode

C/BE[3:0]#

Command

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Interrupt Acknowledge (not support)

Special Cycle (not support)

I/O Read

I/O Write

reserved

Memory Read

Memory Write

reserved

Configuration Read

Configuration Write

Memory Read Multiple (not support)

Dual Address Cycle (not support)

Memory Read Line (not support)

Memory Write and Invalidate (not support)

DS-1 does not assert DEVSEL# when accessed with commands that are indicated as (not supported) or

reserved.

1-1-2. Master Device Mode

C/BE[3:0]#

Command

0

1

0

1

Memory Read

Memory Write

# #

When DS-1 becomes a Master Device, it generates only memory write and read cycle commands.

January 14, 1999

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YMF724F

1-2. PCI Configuration Register

In addition to the Configuration Register defined by PCI Revision 2.1, DS-1 provides proprietary PCI

Configuration Registers in order to control legacy audio function, such as FM Synthesizer, Sound Blaster Pro,

MPU401 and Joystick. These additional registers are configured by BIOS or the configuration software

from YAMAHA Corporation.

The following shows the overview of the PCI Configuration Register.

Offset

00-03h

04-07h

08-0Bh

0C-0Fh

10-13h

14-2Bh

2C-2Fh

30-33h

34-37h

38-3Bh

3C-3Fh

40-43h

44-47h

48-4Bh

4C-4Fh

50-53h

54-57h

58-5Bh

5C-FFh

b[31..24]

b[23..16]

b[15..8]

b[7..0]

Device ID

Status

Vendor ID

Command

Base Class Code

Reserved

Sub Class Code

Header Type

Programming IF

Latency Timer

Revision ID

Reserved

PCI Audio Memory Base Address

Reserved

Subsystem ID

Subsystem Vendor ID

Reserved

Cap Pointer

Maximum Latency

Minimum Grant

Interrupt Pin

Interrupt Line

Extended Legacy Audio Control

Subsystem ID Write

DS-1 Power Control

Reserved

Legacy Audio Control

Subsystem Vendor ID Write

DS-1 Control

D-DMA Slave Configuration

Power Management Capabilities

Reserved

Next Item Pointer

Capability ID

Power Management Control / Status

ACPI Mode

Reserved

Reserved registers are hardwired to “0”. All data written to these registers are discarded. The values

read from these registers are all zero.

DS-1 can be accessed by using any bus width, 8-bit, 16-bit or 32-bit.

January 14, 1999

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YMF724F

00 - 01h: Vendor ID

Read Only

Default: 1073h

Access Bus Width: 8, 16, 32-bit

b15

b14

b13

b12

b11

b10

b9

b8

b7

b6

b5

b4

b3

b2

b1

b0

Vendor ID

b[15:0] ........Vendor ID

This register contains the YAMAHA Vendor ID registered in Revision 2.1. This register is hardwired to

1073h.

02 - 03h: Device ID

Read Only

Default: 000Dh

Access Bus Width: 8, 16, 32-bit

b15

b14

b13

b12

b11

b10

b9

b8

b7

b6

b5

b4

b3

b2

b1

b0

Device ID

b[15:0] ........Device ID

This register contains the Device ID of DS-1. This register is hardwired to 000Dh.

04 - 05h: Command

Read / Write

Default: 0000h

Access Bus Width: 8, 16, 32-bit

b15

b14

b13

b12

b11

b10

b9

-

b8

b7

-

b6

b5

-

b4

-

b3

-

b2

b1

b0

-

SER

PER

BME

MS

b1................MS: Memory Space

This bit enables DS-1 to response to Memory Space Access.

“0”: DS-1 ignores Memory Space Access.

“1”: DS-1 responds to Memory Space Access.

(default)

b2................BME: Bus Master Enable

This bit enables DS-1 to act as a master device on the PCI bus.

“0”: Do not set DS-1 to be the master device.

“1”: Set DS-1 to be the master device.

(default)

b6................PER: Parity Error Response

This bit enables DS-1 responses to Parity Error.

“0”: DS-1 ignores all parity errors.

“1”: DS-1 performs error operation when DS-1 detects a parity error.

January 14, 1999

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YMF724F

b8................SER: SERR# Enable

This bit enables DS-1 to drive SERR#.

“0”: Do not drive SERR#.

(default)

“1”: Drives SERR# when DS-1 detects an Address Parity Error on normal target cycle or a Data Parity

Error on special cycle.

06 - 07h: Status

Read / Write Clear

Default: 0210h

Access Bus Width: 8, 16, 32-bit

b15

b14

b13

b12

b11

b10

b9

b8

b7

-

b6

-

b5

-

b4

b3

-

b2

-

b1

-

b0

-

DPE SSE RMA RTA

STA

DEVT

DPD

CAP

b4................CAP: Capability

(Read Only)

This bit indicates that DS-1 supports the capability register. This bit is read only. When 58-59h :

ACPI Mode register, ACPI bit is “0”, the bit is “1”. When ACPI bit is “1”, the bit is “0”.

b8................DPD: Data Parity Error Detected

This bit indicates that DS-1 detects a Data Parity Error during a PCI master cycle.

b[10:9] ........DEVT: DEVSEL Timing

This bit indicates that the decoding speed of DS-1 is Medium.

b11..............STA: Signaled Target Abort

This bit indicates that DS-1 terminates a transaction with Target Abort during a target cycle.

b12..............RTA: Received Target Abort

This bit indicates that a transaction is terminated with Target Abort while DS-1 is in the master memory

cycle.

b13..............RMA: Received Master Abort

This bit indicates that a transaction is terminated with Master Abort while DS-1 is in the master memory

cycle.

b14..............SSE: Signaled System Error

This bit indicates that DS-1 asserts SERR#.

b15..............DPE: Detected Parity Error

This bit indicates that DS-1 detects Address Parity Error or Data Parity Error during a transaction.

January 14, 1999

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YMF724F

08h: Revision ID

Read Only

Default: 03h

Access Bus Width: 8, 16, 32-bit

b7

b6

b5

b4

b3

b2

b1

b0

Revision ID

b[7:0] ..........Revision ID

This register contains the revision number of DS-1. This register is hardwired to 03h.

09h: Programming Interface

Read Only

Default: 00h

Access Bus Width: 8, 16, 32-bit

b7

b6

b5

b4

b3

b2

b1

b0

Programming Interface

b[7:0] ..........Programming Interface

This register indicates the programming interface of DS-1. This register is hardwired to 00h.

0Ah: Sub-class Code

Read Only

Default: 01h

Access Bus Width: 8, 16, 32-bit

b7

b6

b5

b4

b3

b2

b1

b0

Sub-class Code

b[7:0] ..........Sub-class Code

This register indicates the sub-class of DS-1. This register is hardwired to 01h. DS-1 belongs to the

Audio Sub-class.

0Bh: Base Class Code

Read Only

Default: 04h

Access Bus Width: 8, 16, 32-bit

b7

b6

b5

b4

b3

b2

b1

b0

Base Class Code

b[7:0] ..........Base Class Code

This register indicates the base class of DS-1. This register is hardwired to 04h. DS-1 belongs to the

Multimedia Base Class.

January 14, 1999

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YMF724F

0Dh: Latency Timer

Read / Write

Default: 00h

Access Bus Width: 8, 16, 32-bit

b7

b6

b5

b4

b3

b2

b1

b0

Latency Timer

b[7:0] ..........Latency Timer

When DS-1 becomes a Bus Master device, this register indicates the initial value of the Master Latency

Timer.

0Eh: Header Type

Read Only

Default: 00h

Access Bus Width: 8, 16, 32-bit

b7

b6

b5

b4

b3

b2

b1

b0

Header Type

b[7:0] ..........Header Type

This register indicates the device type of DS-1. This is hardwired to 00h.

10 - 13h: PCI Audio Memory Base Address

Read / Write

Default: 00000000h

Access Bus Width: 8, 16, 32-bit

b15

MBA

b31

b14

b13

b12

b11

b10

b9

-

b8

-

b7

-

b6

-

b5

-

b4

-

b3

-

b2

-

b1

-

b0

-

b30

b29

b28

b27

b26

b25

b24

b23

b22

b21

b20

b19

b18

b17

b16

MBA (higher)

b[31:15] ......MBA: Memory Base Address

This register indicates the physical Memory Base address of the PCI Audio registers in DS-1. The base

address can be located anywhere in the 32-bit address space. Data in the DS-1 register is not

prefetchable.

DS-1 needs 32768-bytes of memory address space.

January 14, 1999

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YMF724F

2C-2Dh: Subsystem Vendor ID

Read Only

Default: 1073h

Access Bus Width: 8, 16, 32-bit

b15

b14

b13

b12

b11

b10

b9

b8

b7

b6

b5

b4

b3

b2

b1

b0

Subsystem Vendor ID

b[15:0] ........Subsystem Vendor ID

This register contains the Subsystem Vendor ID. In general, this ID is used to distinguish adapters or

systems made by different IHVs using the same chip by the same vendor. This register is read only.

To write the IHV’s Vendor ID, use 44-45h (Subsystem Vendor ID Write Register). IHVs must change

this ID to their Vendor ID in the BIOS POST routine.

In case of the system such as Sound Card which BIOS can not control, this ID can be changed by

connecting EEPROM externally. Then, Subsystem Vendor ID Write Register is invalid.

In case EEPROM is not externally, the default value is the YAMAHA's Vendor ID, 1073h.

2E-2Fh: Subsystem ID

Read Only

Default: 000Dh

Access Bus Width: 8, 16, 32-bit

b15

b14

b13

b12

b11

b10

b9

b8

b7

b6

b5

b4

b3

b2

b1

b0

Subsystem ID

b[15:0] ........Subsystem ID

This register contains the Subsystem ID. In general, this ID is used to distinguish adapters or systems

made by different IHVs using the same chip by the same vendor. This register is read only. To write

the IHV's Device ID, use 46-47h (Subsystem ID Write Register). IHVs must change this ID to their ID

in the BIOS POST routine.

In case of the system such as Sound Card which BIOS can not control, this ID can be changed by

connecting EEPROM externally. Then, Subsystem ID Write Register is invalid.

In case EEPROM is not externally, the default value is the YAMAHA's Device ID, 000Dh.

34h: Capability Register Pointer

Read Only

Default: 50h

Access Bus Width: 8, 16, 32-bit

b7

b6

b5

b4

b3

b2

b1

b0

Capability Register Pointer

b[7:0] ..........Capability Register Pointer

This register indicates the offset address of the Capabilities register in the PCI Configuration register

when 58-59h: ACPI Mode register, ACPI bit is “0”. DS-1 provides PCI Bus Power Management

registers as the capabilities. The Power Management registers are mapped to 50h - 57h in the PCI

Configuration register, and this register indicates “50h”.

When ACPI bit is “1”, this register indicates “00h”.

January 14, 1999

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YMF724F

3Ch: Interrupt Line

Read / Write

Default: 00h

Access Bus Width: 8, 16, 32-bit

b7

b6

b5

b4

b3

b2

b1

b0

Interrupt Line

b[7:0] ..........Interrupt Line

This register indicates the interrupt channel that INTA# is assigned to.

3Dh: Interrupt Pin

Read Only

Default: 01h

Access Bus Width: 8, 16, 32-bit

b7

b6

b5

b4

b3

b2

b1

b0

Interrupt Pin

b[7:0] ..........Interrupt Pin

DS-1 supports INTA# only. This register is hardwired to 01h.

3Eh: Minimum Grant

Read Only

Default: 05h

Access Bus Width: 8, 16, 32-bit

b7

b6

b5

b4

b3

b2

b1

b0

Minimum Grant

b[7:0] ..........Minimum Grant

This register indicates the length of the burst period required by DS-1.

This register is hardwired to 05h.

3Fh: Maximum Latency

Read Only

Default: 19h

Access Bus Width: 8, 16, 32-bit

b7

b6

b5

b4

b3

b2

b1

b0

Maximum Latency

b[7:0] ..........Maximum Latency

This register indicates how often DS-1 generates the Bus Master Request.

This register is hardwired to 19h.

January 14, 1999

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YMF724F

40 - 41h: Legacy Audio Control

Read / Write

Default: 907Fh

Access Bus Width: 8, 16, 32-bit

b15

b14

b13

b12

b11

b10

b9

b8

b7

b6

b5

b4

b3

b2

b1

b0

LAD SIEN

MPUIRQ

SBIRQ

SDMA

I/O

MIEN MEN GPEN FMEN SBEN

b0................SBEN: Sound Blaster Enable

This bit enables the mapping of the Sound Blaster Pro block in the I/O space specified by the SBIO bits,

when LAD is set to “0”. The FM Synthesizer registers can be accessed via SB I/O space, while the SB

block is enabled, even if FMEN is set to “0”.

“0”: Disable the mapping of the SB block to the I/O space

“1”: Enable the mapping of the SB block to the I/O space

(default)

b1................FMEN: FM Synthesizer Enable

This bit enables the mapping of the FM Synthesizer block in the I/O space specified by the FMIO bits,

when LAD is set to “0”. FM Synthesizer registers can be accessed via SB I/O space, while the SB block

is enabled, even if FMEN is set to “0”.

“0”: Disable the mapping of the FM Synthesizer block to the FMIO space

“1”: Enable the mapping of the FM Synthesizer block to the FMIO space

(default)

After setting FMEN to “1”, about 100 msec is necessary before accessing these I/O space.

b2................GPEN: Gameport Enable

This bit enables the mapping of the Joystick block in the I/O space specified by the JSIO bits, when LAD

is set to “0”.

“0”: Disable the mapping of the Joystick block

“1”: Enable the mapping of the Joystick block

(default)

b3................MEN: MPU401 Enable

This bit enables the mapping of the MPU401 block in the I/O space specified by the MPUIO bits, when

LAD is set to “0”.

“0”: Disable the mapping of the MPU401 block

“1”: Enable the mapping of the MPU401 block

(default)

b4................MIEN: MPU401 IRQ Enable

This bit enables the interrupt service of MPU401, when LAD is set to “0” and MEN is set to “1”.

MPU401 generates an interrupt signal when it receives any kind of MIDI data from the RXD pin.

“0”: The MPU401 block can not use the interrupt service.

“1”: The MPU401 block can use interrupt signals determined by the MPUIRQ bits.

(default)

b5................I/O: I/O Address Aliasing Control

This bit selects the number of bits to decode for the I/O address of each block.

“0”: 16-bit address decode

“1”: 10-bit address decode

(default)

January 14, 1999

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YMF724F

b[7:6] ..........SDMA: Sound Blaster DMA-8 Channel Select

These bits select the DMA channel for the Sound Blaster Pro block.

“0”:

“1”:

“2”:

“3”:

DMA ch0

DMA ch1

reserved

(default)

DMA ch3

b[10:8] ........SBIRQ: Sound Blaster IRQ Channel Select

These bits select the interrupt channel for the Sound Blaster Pro block.

“0”:

“1”:

“2”:

“3”:

“4”:

IRQ5

IRQ7

IRQ9

IRQ10

IRQ11

(default)

“5” - “7”: reserved.

b[13:11] ......MPUIRQ: MPU401 IRQ Channel Select

When MIEN is set to “1”, these bits select the interrupt channel for the MPU401 block.

“0”:

“1”:

“2”:

“3”:

“4”:

IRQ5

IRQ7

IRQ9

IRQ10

IRQ11

(default)

“5” - “7”: reserved

Same interrupt channels can be assigned to SBIRQ and MPUIRQ.

b14..............SIEN: Serialized IRQ enable

DS-1 supports 3 types of interrupt protocols: PCI interrupt (INTA#), Legacy interrupt (IRQs) and

Serialized IRQ. The interrupt protocol is selected with IMOD and SIEN as follows.

The interrupt channels for IRQs and Serialized IRQ are determined by SBIRQ and MPUIRQ,. Only one

protocol can be used at once.

SIEN

IMOD

Interrupt protocol

0

1

0

1

*

Legacy interrupt (IRQs)

PCI interrupt (INTA#)

Serialized IRQ

(default)

b15..............LAD: Legacy Audio Disable

This bit disables the Legacy Audio block.

“0”: Enables the Legacy Audio block

“1”: Disables the Legacy Audio block

(default)

When this bit is set to “1”, DS-1 does not respond to the I/O Target transaction for legacy I/O address on

the PCI bus.

January 14, 1999

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YMF724F

42 - 43h: Extended Legacy Audio Control

Read / Write

Default: 0000h

Access Bus Width: 8, 16, 32-bit

b15

b14

b13

b12

b11

b10

b9

-

b8

b7

b6

b5

b4

b3

b2

SBIO

b1

b0

IMOD

SBVER

SMOD

-

MAIM

JSIO

MPUIO

FMIO

b[1:0] ..........FMIO: FM I/O Address allocation

These bits determine the base I/O address for the of the FM Synthesizer block (FMBase).

FM Synthesizer block uses 4 bytes in the I/O address space.

“0”:

“1”:

“2”:

“3”:

388h

398h

3A0h

3A8h

(default)

b[3:2] ..........SBIO: SB I/O Address allocation

These bits determine the base I/O address for the Sound Blaster Pro block (SBBase). This block uses 16

bytes in the I/O address space.

“0”:

“1”:

“2”:

“3”:

220h

240h

260h

280h

(default)

b[5:4] ..........MPUIO: MPU I/O Address allocation

These bits determine the base I/O address for the MPU401 block (MPUBase). This block uses 2 bytes

in the I/O address space.

“0”:

“1”:

“2”:

“3”:

330h

300h

332h

334h

(default)

b[7:6] ..........JSIO: Joystick I/O Address allocation

These bits determine the base I/O address for the Joystick block (JSBase). This block uses 1 byte in the

I/O address space.

“0”:

“1”:

“2”:

“3”:

201h

202h

204h

205h

(default)

b8................MAIM: MPU401 Acknowledge Interrupt Mask

This bit determine whether interrupt is asserted when the acknowledge, which is occurred by changing

MPU401 mode form default to UART, is returned.

“0”: Interrupt is asserted when the acknowledge is returned.

“1”: Interrupt is masked when the acknowledge is returned.

(default)

January 14, 1999

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YMF724F

b[12:11] ......SMOD: SB DMA mode

These bits determine the protocol to achieve the DMAC(8237) function on the PCI bus.

“0”:

“1”:

“2”:

“3”

PC/PCI

(default)

reserved

Distributed DMA

reserved

b[14:13] ......SBVER: SB Version Select

These bits set the version of the SB Pro DSP. The value set in these bits is returned by sending the E1h

DSP command.

“0”:

“1”:

“2”:

“3”:

ver 3.01

ver 2.01

ver 1.05

reserved

(default)

b15..............IMOD: Legacy IRQ mode

DS-1 supports 3 types of interrupt protocols: PCI interrupt (INTA#), Legacy interrupt (IRQs) and

Serialized IRQ. The interrupt protocol is selected with IMOD and SIEN as follows.

SIEN

IMOD

Interrupt protocol

0

1

0

1

*

Legacy interrupt (IRQs)

PCI interrupt (INTA#)

Serialized IRQ

(default)

44-45h: Subsystem Vendor ID Write Register

Read / Write

Default: 1073h

Access Bus Width: 16-bit

b15

b14

b13

b12

b11

b10

b9

b8

b7

b6

b5

b4

b3

b2

b1

b0

Subsystem Vendor ID Write

b[15:0] ........Subsystem Vendor ID Write Register

This register sets the Subsystem Vendor ID that is read from 2C-2Dh (Subsystem Vendor ID register).

The default value is the YAMAHA Vendor ID, 1073h. IHVs must change this ID to their Vendor ID in

the BIOS POST routine.

In case EEPROM connects externally, this register is invalid, and do not reflect to Subsystem Vendor ID.

January 14, 1999

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YMF724F

46-47h: Subsystem ID Write Register

Read / Write

Default: 000Dh

Access Bus Width: 16-bit

b15

b14

b13

b12

b11

b10

b9

b8

b7

b6

b5

b4

b3

b2

b1

b0

Subsystem ID Write

b[15:0] ........Subsystem ID Write Register

This register sets the Subsystem ID that is read from 2E-2Fh (Subsystem ID register).

The default value is the DS-1 Device ID, 000Dh. IHVs must change this ID to their ID in the BIOS

POST routine.

In case EEPROM connects externally, this register is invalid, and do not reflect to Subsystem ID.

48-49h: DS-1 Control Register

Read / Write

Default: 0001h

Access Bus Width: 8, 16, 32-bit

b15

b14

b13

b12

b11

b10

b9

-

b8

-

b7

-

b6

-

b5

-

b4

-

b3

-

b2

-

b1

b0

-

XRST CRST

b0................CRST: AC’97 Software Reset Signal Control

This bit controls the CRST# signal.

“0”: Inactive (CRST#=High)

“1”: Active (CRST#=Low)

(default)

b1................XRST: Local Device Software Reset Signal Control

This bit controls the XRST# signal.

“0”: Inactive (XRST#=High)

“1”: Active (XRST#=Low)

(default)

4A-4Bh: DS-1 Power Control Register

Read / Write

Default: 0000h

Access Bus Width: 8, 16, 32-bit

b15

b14

b13

b12

b11

b10

b9

b8

b7

-

b6

-

b5

b4

b3

b2

b1

b0

PR7

PR6

PR5

PR4

PR3

PR2

PR1

PR0

PSN PSL1 PSL0 DPLL1 DPLL0 DMC

b0................DMC: Disable Master Clock Oscillation

Setting this bit to “1” disables the oscillation of the Master Clock (24.576 MHz).

“0”: Normal

“1”: Disable

(default)

b1................DPLL0: Disable PLL0 Clock Oscillation

Setting this bit to “1” disables the oscillation of PLL for the Legacy Audio function.

“0”: Normal

“1”: Disable

(default)

January 14, 1999

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YMF724F

b2................DPLL1: Disable PLL1 Clock Oscillation

Setting this bit to “1” disables the oscillation of PLL for the PCI Audio function.

“0”: Normal

“1”: Disable

(default)

b3................PSL0: Power Save Legacy Audio Block 0

Setting this bit to “1” stops providing the clock with the Legacy Audio function block 0. This block

includes FM Synthesizer and SB Pro engines.

“0”: Normal

(default)

“1”: Power Save

b4................PSL1: Power Save Legacy Audio Block 1

Setting this bit to “1” stops providing the clock with the Legacy Audio function block 1. This block

includes MPU401 and Joystick.

“0”: Normal

(default)

“1”: Power Save

b5................PSN: Power Save PCI Audio block

Setting this bit to “1” stops providing the clock with the PCI Audio function block. This block includes

PCI Audio, SRC, AC3F2 I/F, AC’97 I/F, H/W Vol. and SPDIF.

“0”: Normal

(default)

“1”: Power Save

b8................PR0: AC’97 Power down Control 0

This bit controls the power state of the ADC and Input Mux in AC’97.

“0”: Normal

(default)

“1”: Power down

b9................PR1: AC’97 Power down Control 1

This bit controls the power state of the DAC in AC’97.

“0”: Normal

(default)

“1”: Power down

b10..............PR2: AC’97 Power down Control 2

This bit controls the power state of the Analog Mixer (Vref still on) in AC‘97. This power state retains

the Reference Voltage of AC’97.

“0”: Normal

(default)

“1”: Power down

b11..............PR3: AC’97 Power down Control 3

This bit controls the power state of the Analog Mixer (Vref off) in AC’97. This power state removes

Reference Voltage of AC’97.

“0”: Normal

(default)

“1”: Power down

January 14, 1999

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YMF724F

b12..............PR4: AC’97 Power down Control 4

This bit controls the power state of the AC-link in AC’97.

“0”: Normal

(default)

“1”: Power down

b13..............PR5: AC’97 Power down Control 5

Setting this bit to “1” disables the internal clock of AC’97. In case AC’97 is used with DS-1, the master

clock is supplied from DS-1. Therefore, when the clock of AC’97 is stopped completely, set both PR5

and PSN bits to “1”.

“0”: Normal

“1”: Disable

(default)

b[15:14] ......AC’97 Power down Control 6 and 7

These bits control PR6 and PR7 status of the power control register in AC’97.

PSL0

Legacy func. 0

Master

PLL0

FM Synthesizer

SB Pro

(24.576MHz)

33.87MHz

DMC

DPLL0

PSL1

PSN

Legacy func. 1

MPU401

Joystick

PCI func. 0

PLL1

AC3F2 I/F

AC'97 I/F

H/W Vol.

PCI Audio

SRC

49.152MHz

DPLL1

SPDIF

PCI func. 1

PCICLK

(33MHz)

PCI I/F

PC/PCI

D-DMA

S-IRQ

- Set DPLL0, DPLL1, PSL0, PSL1 and PSN bits to “1”, when DMC bit is set to “1”.

- Set PSL0 and PSL1 bits to “1”, when DPLL0 bit is set to “1”.

- Set PSN bit to “1”, when DPLL1 bit is set to “1”.

January 14, 1999

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YMF724F

4C-4Dh: D-DMA Slave Configuration

Read / Write

Default: 0000h

Access Bus Width: 8, 16, 32-bit

b15

b14

b13

b12

b11

b10

b9

b8

b7

b6

b5

b4

b3

b2

b1

b0

Base Address

EA

TS

CE

b0................CE: Channel Enable

This bit enables the Distributed DMA function.

“0”: Disable Distributed DMA (default)

“1”: Enable Distributed DMA

b[2:1] ..........TS: Transfer Size

These bits indicate the size of the DMA transfer. Since DS-1 supports only 8-bit DMA transfer, the bits

are hardwired to 00b.

b3................EA: Extended Address

DS-1 does not support extended address mode. This bit is hardwired to 0b.

b[15:4] ........Base Address : D-DMA Slave Base Address

These bits indicate the D-DMA slave base address.

50h: Capability ID

Read Only

Default: 01h

Access Bus Width: 8, 16, 32-bit

b7

b6

b5

b4

b3

b2

b1

b0

Capability ID

b[7:0] ..........Capability ID: Capability Identifier

This register indicates that the new capability register is for Power Management control. This register is

hardwired to 01h.

January 14, 1999

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YMF724F

51h: Next Item Pointer

Read Only

Default: 00h

Access Bus Width: 8, 16, 32-bit

b7

b6

b5

b4

b3

b2

b1

b0

Next Item Pointer

b[7:0] ..........Next Item Pointer

DS-1 does not provide other new capability besides Power Management. This register is hardwired to

00h.

52-53h: Power Management Capabilities

Read Only

Default: 0401h

Access Bus Width: 8, 16, 32-bit

b15

b14

b13

b12

b11

b10

b9

b8

-

b7

-

b6

-

b5

-

b4

-

b3

-

b2

b1

b0

-

D2S

D1S

Version

b[2:0] ..........Version

These bits contain the revision number of the Power Management Interface Specification. They are

hardwired to 001b.

b9................D1S: D1 Support

This bit indicates whether DS-1 support “D1” of the power state. Only when EEPROM connects

externally, this bit can be set to “1”, and D1 state can support. When EEPROM does not connect

externally, use ACPI mode (58-59h: ACPI Mode Register, ACPI bit) to support D1 state.

The default value is “0”.

b10..............D2S: D2 Support

This bit indicates that DS-1 support “D2” of the power state. It is hardwired to “1”.

January 14, 1999

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YMF724F

54-55h: Power Management Control / Status

Read / Write

Default: 0000h

Access Bus Width: 8, 16, 32-bit

b15

b14

b13

b12

b11

b10

b9

-

b8

-

b7

-

b6

-

b5

-

b4

-

b3

-

b2

-

b1

b0

-

PS

b[1:0] ..........PS: Power State

These bits determine the power state of DS-1. DS-1 supports the following power states:

“0”:

“1”:

“2”:

“3”:

D0

D1

(not supported)

D2

D3_hot

When the power state is changed from D3_hotto D0, DS-1 resets the PCI Configuration register 00-3Fh.

DS-1 transits to D0 Uninitialized state.

Though the power state of this register is changed, the power consumption of DS-1 is not changed. To

support low power, Windows driver controls DS-1 Power Control Register.

DS-1 can support the power state of D0, D1, D2 and D3 with ACPI. In this case, set ACPI bit (58-59h:

ACPI Mode Register) to “1” to disable Capabilities of PCI Bus Power Management.

58-59h: ACPI Mode

Read / Write

Default: 0000h

Access Bus Width: 8, 16, 32-bit

b15

b14

b13

b12

b11

b10

b9

-

b8

-

b7

-

b6

-

b5

-

b4

-

b3

-

b2

-

b1

-

b0

-

ACPI

b0................ACPI: ACPI Mode Select

This bit select either PCI Bus Power Management or ACPI Mode for power management of DS-1.

“0”: PCI Bus Power Management is used. CAP bit (06-07h: Status Register) and Capabilities Pointer

(34h) are enabled. (default)

“1”: ACPI Mode is used. CAP bit and Capabilities Pointer are hardwired “0”, and disabled.

January 14, 1999

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YMF724F

2. ISA Compatible Device

DS-1 contains the following functions to maintain the compatibility with the past ISA Sound Devices.

These devices are considered Legacy devices and the functions are referred to as Legacy Audio.

Legacy Audio is independent from PCI Audio and can be used simultaneously.

The configuration is set in the Legacy Audio Control Register in the PCI Configuration Register space.

Basically, these registers are configured by the BIOS.

Also, logical device IDs are assigned to the devices to support Plug and Play. Yamaha defines the following

logical IDs.

To control the device with the BIOS, the logical device IDs must be defined in the PnP BIOS extended ROM

space. The logical IDs are determined by how it is configured. IDs and configuration are as follows.

Functions used (Block)

Logical Device ID

FM ^(*)

O

MPU401

SB Pro ^(*)

O

Joystick

O

YMH0100

YMH0101

O

* The blocks pertain to the following.

FM:

Points to the FM synthesizer mapped to AdLibBase (0x0388).

Points to the Voice Playback section only.

SB Pro:

These devices are independent from each other, and can be Enabled/Disabled individually. However, both

AdLib and Sound Blaster must be disabled to disable the internal FM Synthesizer. Disabling just AdLib

only masks the access.

The driver by Yamaha supports only logical device ID, YMH0100. For YMH0101, use the driver provided

by Microsoft.

January 14, 1999

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YMF724F

DS-1 supports PC/PCI and D-DMA protocols to emulate the DMA of SB Pro on the PCI. In addition, DS-1

supports the old type of interrupts used by ISA and the Serialized IRQ protocol.

Yamaha recommends the combination of PC/PCI and Serialized IRQ. The system block diagram when

using Intel chip set is shown below.

North

Brigde

(430TX/440BX)

PCI

Address/Data

Control

PCREQ#

PCGNT#

IRQ5

IRQ7

IRQ9

IRQ10

IRQ11

South

Bridge

(PIIX4E)

DS-1

SERIRQ#

Select either protocols

The PCI-to-ISA bridge needs to support PC/PCI. IRQ is directly connected to the IRQ input pins on the

PCI-to-ISA bridge.

January 14, 1999

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YMF724F

2-1. FM Synthesizer Block

FM Synthesizer Block is register compatible with YMF289B. However, Power Management register

has been deleted because it is now controlled by the PCI Configuration Register.

The following shows the FMBase I/O map of FM Synthesizer.

FMBase

(R)

Status Register port

Address port for Register Array 0

Data port

FMBase

(W)

FMBase+1

FMBase+2

FMBase+3

(R/W)

(W)

Address port for Register Array 1

Data port

(R/W)

The default FMBase value is 0x0388.

The following shows the FM Synthesizer Block registers.

2-1-1. Status Register

FM Synthesizer Status Register (RO):

Address

xxh

D7

D6

D5

D4

-

D3

-

D2

D1

-

D0

IRQ

FT1

FT2

BUSY

January 14, 1999

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YMF724F

2-1-2. FM Synthesizer Data Register

FM Synthesizer Data Register Array 0 (R/W):

Address

D7

D6

D5

D4

D3

D2

D1

D0

00-01h

02h

LSI TEST

TIMER 1

TIMER 2

03h

04h

RST

-

MT1

NTS

VIB

MT2

-

ST2

-

ST1

-

08h

20-35h^(*1)

40-55h^(*2)

60-75h^(*3)

80-95h^(*4)

A0-A8h

B0-B8h

BDh

AM

EGT

KSR

MULT

KSL

TL

AR

SL

DR

RR

F-NUM (L)

-

DAM

*6

-

DVB

*6

KON

RHY

CHR

-

BLOCK

SD

F-NUM (H)

BD

CHL

-

TOM

FB

TC

HH

C0-C8h

E0-F5h^(*5)

CNT

-

WS

FM Synthesizer Data Register Array 1 (R/W)

Address

D7

D6

D5

D4

D3

D2

D1

*

D0

00-01h

04h

LSI TEST

CONNECTION SEL

-

05h

-

*

NEW

20-35h^(*1)

40-55h^(*2)

60-75h^(*3)

80-95h^(*4)

A0-A8h

B0-B8h

C0-C8h

E0-F5h^(*5)

AM

VIB

EGT

KSR

MULT

KSL

TL

AR

SL

DR

RR

F-NUM (L)

-

*6

-

*6

-

KON

CHR

-

BLOCK

F-NUM (H)

CHL

-

FB

CNT

-

WS

*1 : 26h, 27h, 2Eh and 2Fh do not exist.

*2 : 46h, 47h, 4Eh and 4Fh do not exist.

*3 : 66h, 67h, 6Eh and 6Fh do not exist.

*4 : 86h, 87h, 8Eh and 8Fh do not exist.

*5 : E6h, E7h, EEh and EFh do not exist.

*6 : The bits exist, but do not function.

January 14, 1999

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YMF724F

2-2. Sound Blaster Pro Block

This block emulates the DSP commands of Sound Blaster and Sound Blaster Pro. Only playback

functions are supported (record functions are not supported). However, to maintain compatibility for

games, it is designed so that every DSP command receives a correct response.

The DMA transfer of this block uses PC/PCI or D-DMA protocol.

The following shows the SBBase I/O map of SB Pro.

SBBase

(R)

FM Synthesizer Status port

SBBase

(W)

(R/W)

(W)

(R/W)

(W)

(R/W)

(W)

(R)

FM Synthesizer Address port for Register Array 0

FM Synthesizer Data register

FM Synthesizer Address port for Register Array 1

FM Synthesizer Data port

SBBase+1h

SBBase+2h

SBBase+3h

SBBase+4h

SBBase+5h

SBBase+6h

SBBase+8h

SBBase+9h

SBBase+Ah

SBBase+Ch

SBBase+Eh

SB Mixer Address port

SB Mixer Data port

SB DSP Reset port

FM Synthesizer Status port

(W)

(R/W)

(R)

FM Synthesizer Address port for Register Array 0

FM Synthesizer Data port

DSP Read Data port

(R)

DSP Write-buffer status port

DSP Write Command/Data port

DSP Read-buffer status port

(W)

(R)

January 14, 1999

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YMF724F

2-2-1. DSP Command

The following shows the list of DSP Commands that are supported by the SB Pro engine. Both SB and

SB Pro commands are supported.

CMD Support Function

10h

14h

16h

17h

1Ch

1Fh

20h(*1)

24h(*1)

2Ch(*1)

30h

31h

34h

35h

36h(*2)

37h(*2)

38h

40h

48h

74h

75h

76h

77h

7Dh

7Fh

80h

90h

o

8bit direct mode single byte digitized sound output

8bit single-cycle DMA mode digitized sound output

8bit to 2bit ADPCM single-cycle DMA mode digitized sound output

8bit to 2bit ADPCM single-cycle DMA mode digitized sound output with ref. byte

8bit auto-init DMA mode digitized sound output

8bit to 2bit ADPCM auto-init DMA mode digitized sound output with ref. byte

8bit direct mode single byte digitized sound input

8bit single-cycle DMA mode digitized sound input

8bit auto-init DMA mode digitized sound input

Polling mode MIDI input

o

Interrupt mode MIDI input

UART polling mode MIDI I/O

UART interrupt mode MIDI I/O

UART polling mode MIDI I/O with time stamping

UART interrupt mode MIDI I/O with time stamping

MIDI output

Set digitized sound transfer Time Constant

Set DSP block transfer size

8bit to 4bit ADPCM single-cycle DMA mode digitized sound output

8bit to 4bit ADPCM single-cycle DMA mode digitized sound output with ref. byte

8bit to 3bit ADPCM single-cycle DAM mode digitized sound output

8bit to 3bit ADPCM single-cycle DMA mode digitized sound output with ref. byte

8bit to 4bit ADPCM auto-init DMA mode digitized sound output with ref. byte

8bit to 3bit ADPCM auto-init DMA mode digitized sound output with ref. byte

Pause DAC for a duration

8bit high-speed auto-init DMA mode digitized sound output

8bit high-speed single-cycle DMA mode digitized sound output

8bit high-speed auto-init DMA mode digitized sound input

8bit high-speed single-cycle DMA mode digitized sound input

Set input mode to mono

Set input mode to stereo

Pause 8bit DMA mode digitized sound I/O

Turn on speaker

Turn off speaker

Continue 8bit DMA mode digitized sound I/O

Get speaker status

Exit 8bit auto-init DMA mode digitized sound I/O

Get DSP version number

o

91h

98h(*1)

99h(*1)

A0h(*1)

A8h(*1)

D0h

D1h(*3)

D3h(*3)

D4h

D8h

DAh

E1h

Note:

(*1) The SB Block responds correctly to the commands for recording and also executes the DMA transfer.

80h is always transferred.

(*2) Only output is supported for this command.

(*3) This command only changes Speaker Status (D8h).

Undocumented commands other than the ones listed above are also supported.

January 14, 1999

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YMF724F

2-2-2. Sound Blaster Pro Mixer

The following shows the register map of the Mixer section of Sound Blaster Pro.

Address

00h

b7

b6

b5

b4

b3

b2

b1

b0

Remark

Reset

04h

Voice Volume L

-

"1"

-

Voice Volume R

"1"

0Ah

0Ch

0Eh

22h

-

MIC Volume*

Input Source*

St. SW

Ifilter*

-

"1"

Ofilter*

-

SB Pro Mixer

Master Volume L

MIDI Volume L

CD Volume L*

Line Volume L*

Master Volume R

MIDI Volume R

CD Volume R*

Line Volume R*

"1"

26h

"1"

28h

"1"

2Eh

F0h

F1h

F8h

"1"

SBPDA

-

SS

SM

SE

SBPDR

Suspend / Resume

IRQ Status

SCAN DATA

-

SBI

The registers marked with * exist, but do not function.

DS-1 does not have the circuit that corresponds to the SB Mixer. Therefore, the volume settings on the

SB Mixer are converted to the DSP coefficients of DS-1 or to AC’97 register values.

The conversion for each case is described below.

®

(1) SB Mixer

DSP

The volume of master, MIDI and Voice, are applied to this case.

When the SB register is set, a 14-bit coefficient value is determined from the following conversion table

and used as the DSP coefficient. The attenuation value of Master Volume, MIDI, and voice are summed

together to obtain the coefficient.

These volumes cannot be controlled from PCI Audio block.

January 14, 1999

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YMF724F

(1) Volume for MIDI

MIDI Vol. (26h)

0

1

2

3

4

5

6

7

mute

0000h

mute

0000h

mute

0000h

mute

0000h

mute

0000h

mute

0000h

mute

0000h

mute

0000h

mute

0000h

-52dB

0029h

-42dB

0082h

-36dB

0103h

-32dB

019Bh

-30dB

0206h

-28dB

028Ch

-26dB

0335h

mute

0000h

-42dB

0082h

-32dB

019Bh

-26dB

0335h

-22dB

0515h

-20dB

0666h

-18dB

080Eh

-16dB

0A24h

mute

0000h

-32dB

019Bh

-22dB

0515h

-16dB

0A24h

-12dB

1013h

-10dB

143Dh

-8dB

mute

0000h

-30dB

0206h

-20dB

0666h

-14dB

0CC5h

-10dB

143Dh

-8dB

mute

0000h

-28dB

028Ch

-18dB

080Eh

-12dB

1013h

-8dB

mute

0000h

-26dB

0335h

-16dB

0A24h

-10dB

143Dh

-6dB

0

1

2

3

4

5

6

7

0000h

-36dB

0103h

-26dB

0335h

-20dB

0666h

-16dB

0A24h

-14dB

0CC5h

-12dB

1013h

-10dB

143Dh

197Ah

-6dB

2013h

-4dB

197Ah

-6dB

2013h

-4dB

2861h

-2dB

197Ah

-6dB

2013h

-4dB

2861h

-2dB

32D6h

0dB

2013h

2861h

32D6h

3FFFh

The default is Master = 4, MIDI = 4 (-12dB).

(2) Volume for Voice

Voice Vol. (04h)

0

1

2

3

4

5

6

7

mute

0000h

mute

0000h

mute

0000h

mute

0000h

mute

0000h

mute

0000h

mute

0000h

mute

0000h

mute

0000h

-56dB

0019h

-46dB

0052h

-40dB

00A3h

-36dB

0103h

-34dB

0146h

-32dB

019Bh

-30dB

0206h

mute

0000h

-46dB

0052h

-36dB

0103h

-30dB

0206h

-26dB

0335h

-24dB

0409h

-22dB

0515h

-20dB

0666h

mute

0000h

-34dB

0146h

-24dB

0409h

-18dB

080Eh

-14dB

0CC5h

-12dB

1013h

-10dB

143Dh

-8dB

mute

0000h

-32dB

019Bh

-22dB

0515h

-16dB

0A24h

-12dB

1013h

-10dB

143Dh

-8dB

mute

0000h

-30dB

0206h

-20dB

0666Eh

-14dB

0CC5h

-10dB

143Dh

-8dB

0

1

2

3

4

5

6

7

0000h

-40dB

00A3h

-30dB

0206h

-24dB

0409h

-20dB

0666h

-18dB

080Eh

-16dB

0A24h

-14dB

0CC5h

0000h

-36dB

0103h

-26dB

0335h

-20dB

0666h

-16dB

0A24h

-14dB

0CC5h

-12dB

1013h

-10dB

143Dh

197Ah

-6dB

197Ah

-6dB

2013h

-4dB

187Ah

2013h

2861h

The default is Master = 4, Voice = 4 (-16dB).

®

(2) SB Mixer

AC’97

The volume of CD, Line and MIC are applied to this case. AC’97 volume are not updated automatically

when these values are changed. Thus, the SB Mixer values need to be written to the AC’97 register with

the software.

January 14, 1999

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YMF724F

2-2-3. SB Suspend / Resume

The SB block can read the internal state as to support Suspend and Resume functions. The internal state

is made up of 218 flip flops. To read the state, these states are shifted in order and read 8 bits at a time

from the SCAN DATA register.

These registers are mapped to the SB Mixer space (see SB Mixer Register map). The registers have the

following functions.

F0h: Scan In/ Out Control

Read / Write

Default: 00h

b7

b6

b5

b4

-

b3

b2

b1

b0

SBPDA

SBPDR

-

SS

SM

SE

b0................SBPDR: Sound Blaster Power Down Request

This bit stops the internal state of the Sound Blaster block.

“0”: Normal

“1”: Stop

(default)

b1................SE: Scan Enable

This bit Shifts the internal state by 1 bit. Setting a “1” followed by a “0” shifts the internal state.

b2................SM: Scan Mode

This bit sets whether to read or write the state.

“0”: Write

“1”: Read

(default)

b3................SS: Scan Select

This bit gives permission to read or write the internal data to the SCAN DATA register.

“0”: Normal operation (Do not allow read or write).

“1”: Allow read and write.

(default)

b7................SBPDA: Sound Blaster Power Down Acknowledgement

This bit indicates that the SB Block is ready to read or write to the internal state after setting SBPDR.

This bit is read only.

“0”: Read/Write not possible

“1”: Read/ Write possible

January 14, 1999

-35-

YMF724F

F1h: Scan In/ Out Data

Read / Write

Default: 00h

b7

b6

b5

b4

b3

b2

b1

b0

SCAN DATA

b[7:0] ..........SCAN DATA

This is the data port for reading and writing the internal state.

F8h: Interrupt Flag Register

Read Only

Default: 00h

b7

b6

b5

b4

-

b3

-

b2

-

b1

-

b0

-

SBI

b0................SBI: SB Interrupt Flag

This bit indicates that the SB DSP occurs the interrupt. This bit is read only. Thus, read the SB DSP

read port to clearing the interrupt and this bit. Then, the value of the read port is invalid.

January 14, 1999

-36-

YMF724F

2-3. MPU401

This block is for transmitting and receiving MIDI data. It is compatible with UART mode of “MPU401”.

Full duplex operation is possible using the 16-byte FIFO for each direction, transmitting and receiving.

The following shows the MPUBase I/O map for MPU401.

MPUBase

(R/W)

(R)

MIDI Data port

MPUBase + 1h

Status Register port

Command Register port

(W)

port

D7

D6

D5

D4

D3

D2

D1

D0

+0h

Data

Command

+1h (W)

+1h (R)

/DSR

/DRR

-

2-4. Joystick

JSBase

(R/W)

port

+0h

D7

D6

D5

D4

D3

D2

D1

D0

JBB2

JBB1

JAB2

JAB1

JBCY

JBCX

JACY

JACX

JACX...

JACY...

JBCX...

JBCY...

JAB1...

JAB2...

JBB1...

JBB2...

Joystick A, Coordinate X

Joystick A, Coordinate Y

Joystick B, Coordinate X

Joystick B, Coordinate Y

Joystick A, Button 1

Joystick A, Button 2

Joystick B, Button 1

Joystick B, Button 2

January 14, 1999

-37-

YMF724F

3. DMA Emulation Protocol

The former synthesizer LSI for the ISA bus such as the Sound Blaster used the DMA controller (8237: ISA

DMAC) on the system to transfer the sound data from/to the host.

For DS-1, however, ISA DMAC must be used to transfer the sound data to the Sound Blaster Pro Block of

the Legacy Audio Block.

Because signals to connect to the ISA DMAC are generally not available on the PCI bus, there are two ways

proposed from the industry to emulate the ISA DMAC on the PCI bus. One is PC/PCI and the other is D-

DMA.

DS-1 supports both protocols for transferring SB Pro sound data on the PCI bus.

3-1. PC/PCI

DS-1 provides two signals, PCREQ# and PCGNT# to realize the PC/PCI. The format of the signals is

shown below. DS-1 asserts PCREQ# and sets PCREQ# to “HIGH” using the PCICLK corresponding to the

DMA channel it is going to use.

In addition, DS-1 determines whether the next PCI I/O cycle is its own from the channel information that is

encoded in PCGNT#.

0ns

100ns

200ns

300ns

400ns

PCICLK

REQ#

start

CH0 CH1 CH2 CH3

CH4 CH5

CH6 CH7

GNT#

start

bit0

bit1 bit2

PCGNT# is encoded as follows.

GNT# Encoding

GNT# Bits

bit2

bit1

bit0

DMA Channel 0

DMA Channel 1

DMA Channel 2

DMA Channel 3

Reserved

0

1

0

1

0

1

0

1

0

1

0

1

0

1

DMA Channel 5

DMA Channel 6

DMA Channel 7

DS-1 supports only 8-bit DMA channels (DMA Channel 0-3). It also only supports Single DMA transfer.

January 14, 1999

-38-

YMF724F

3-2. D-DMA

DS-1 provides the following registers to support D-DMA. D-DMA Slave Configuration Register (4C-4Dh)

of the PCI Configuration register is used to set the Base address of the Slave Address.

Slave Address

Base + 0h

Base + 1h

Base + 2h

Base + 3h

Base + 4h

Base + 5h

Base + 6h

Base + 7h

Base + 8h

Base + 9h

Base + Ah

Base + Bh

Base + Ch

Base + Dh

Base + Eh

Base + Fh

R/W

W

R

Register Name

Base Address 0-7

Current Address 0-7

Base Address 8-15

Current Address 8-15

Base Address 16-23

Current Address 16-23

Base Address 24-31

Current Address 24-31

Base Word Count 0-7

Current Word Count 0-7

Base Word Count 8-15

Current Word Count 8-15

Base Word Count 16-23

Current Word Count 16-23

Reserved

W

R

W

R

W

R

W

R

W

R

W

R

N/A

W

R

Command

Status

W

N/A

W

N/A

R/W

Request

Reserved

Mode

Reserved

Master Clear

Reserved

Multi-Channel Mask

These registers can be accessed by 8-bit or 16-bit bus width.

DS-1 supports 8-bit DMA transfer only.

January 14, 1999

-39-

YMF724F

4. Interrupt Routing

DS-1 supports three types of interrupts, interrupt signal on the PCI bus (INTA#), interrupt signal on the ISA

bus (IRQ[5,7,9,10,11]), and Serialized IRQ.

The IRQs on DS-1 are routed as shown below.

PCI Audio

INTA#

INTA

SIEN=0, IMOD=1

SIEN=0, IMOD=0

IRQ

Sound Blaster Pro

IRQ5

IRQ7

SIEN=1, IMOD=*

Select Signal

ISA IRQ

IRQ9

SBIRQ[2:0]

IRQ10

IRQ11

SIEN=0, IMOD=1

SIEN=0, IMOD=0

IRQ

MPU401

SIEN=1, IMOD=*

SIEN, IMOD

Select Signal

SERIRQ#

SERIRQ

MPUIRQ[2:0]

PCI Audio can only use INTA#, but the Sound Blaster Pro and MPU401 blocks of the Legacy Audio Block

can use any of the three protocols.

The protocol can be switched using 40-43h (Legacy Audio Control Register) of the PCI Configuration

Register.

4-1. Serialized IRQ

Serialized IRQ is a method to encode IRQs of 15 channels into one signal.

DS-1 provides the SERIRQ# pin to support Serialized IRQ.

Only one channel out of the 5 channels, IRQ5, IRQ7, IRQ9, IRQ10, and IRQ11, can be encoded into the

IRQ/Data frame of Serialized IRQ.

The IRQ channel is selected using 40h-43h (Legacy Audio Control Register) of the PCI Configuration

Register.

5. Digital Audio Interface

DS-1 only supports SPDIF output conforming to IEC958. The only supported Fs is 48 kHz. It can be

selectable from the Dolby Digital (AC-3) encoded data or the result of Digital Mixing.

January 14, 1999

-40-

YMF724F

6. Hardware Volume Control

The hardware volume control determines the AC’97 master volume without using any software control using

the external circuit listed below.

Two pins, VOLUP# for increasing the volume and VOLDW# for decreasing the volume, are used.

Push SW

1k

VOLUP#

Push SW

1k

VOLDW#

1000p

DS-1 provides a shadow register for the AC’97 master volume. When the software accesses the AC’97

Master Volume, it is always reflected in the shadow register.

The value of the shadow register is incremented by 1.5dB on the rising edge of the signal input to the

VOLUP# pin. If it is already set to the maximum value, it does not change. The value set in the shadow

register automatically updates the AC’97 master volume register through the AC-Link.

The value of the shadow register is decremented by 1.5dB on the rising edge of the signal input to the

VOLDW# pin. If it is already set to the minimum value, it does not change. The value set in the shadow

register automatically updates the AC’97 master volume register through the AC-Link.

Also, when both VOLUP#, VOLDW# pins are at LOW level, the MUTE bit of the shadow address is enabled

and the Master Volume Mute bit of the AC’97 register is automatically set through the AC-Link. When a

rising edge is detected on either VOLUP# or VOLDW#, the MUTE bit is reset through the AC-Link. The

Master Volume is set to the value before the Mute.

If the AC-Link is BUSY (when controlling the register from the AC’97 Control Register), the value in the

shadow register is set to AC’97 on the next frame. The AC’97 Control Register is set to BUSY in this case.

When the master volume changes or is muted due to VOLUP#, VOLDW#, an interrupt is generated at the

host.

The interrupt is used to notify the driver that the Master Volume has been changed from the outside.

January 14, 1999

-41-

YMF724F

ELECTRICAL CHARACTERISTICS

1. Absolute Maximum Ratings

Item

Symbol

Min.

Max.

Unit

Power Supply Voltage 1 (PVDD, VDD5)

Power Supply Voltage 2 (VDD3, LVDD)

Input Voltage 1 (PVDD, VDD5)

Input Voltage 2 (VDD3, LVDD)

Operating Ambient Temperature

Storage Temperature

V_DD5

V_DD3

V_IN5

V_IN3

T_OP

-0.5

-0.3

-0.5

-0.3

0

7.0

4.6

V

V_DD5+0.5

V_DD3+0.3

70

V

°C

T_STG

-50

125

Note : PVSS=LVSS=VSS=0[V]

2. Recommended Operating Conditions

Item

Symbol

Min.

Typ.

Max.

Unit

Power Supply Voltage 1 (PVDD, VDD5)

Power Supply Voltage 2 (VDD3, LVDD)

Operating Ambient Temperature

V_DD5

V_DD3

T_OP

4.75

3.00

0

5.00

3.30

25

5.25

3.60

70

V

°C

Note : PVSS=LVSS=VSS=0[V]

January 14, 1999

-42-

YMF724F

3. DC Characteristics

Item

Symbol

Condition

Min.

Typ.

Max.

Unit

High Level Input Voltage 1

Low Level Input Voltage 1

High Level Input Voltage 2

Low Level Input Voltage 2

High Level Input Voltage 3

Low Level Input Voltage 3

High Level Input Voltage 4

Low Level Input Voltage 4

Input Leakage Current

V_IH1

V_IL1

V_IH2

V_IL2

V_IH3

V_IL3

V_IH4

V_IL4

I_IL

*1

*2

*3

*4

2.2

-0.5

2.2

V_DD5+0.5

0.8

V

V_DD5+0.5

0.6

V

-0.5

2.2

V

0.8

V

0.7V_DD5

V

0.2V_DD5

10

V

0< V_IN< V_DD5

*5, I_OH1= -1mA

*5, I_OL1= 3mA

*6, I_OH2= -2mA

*6, I_OL2= 6mA

*7, I_OH3= -4mA

*7, I_OL3= 12mA

*8, I_OH4= -80µA

*8, I_OL4= 2mA

-10

2.4

µA

V

High Level Output Voltage 1

Low Level Output Voltage 1

High Level Output Voltage 2

Low Level Output Voltage 2

High Level Output Voltage 3

Low Level Output Voltage 3

High Level Output Voltage 4

Low Level Output Voltage 4

Input Pin Capacitance

V_OH1

V_OL1

V_OH2

V_OL2

V_OH3

V_OL3

V_OH4

V_OL4

C_IN

0.55

V

2.4

V

V_DD5-1.0

V

0.4

15

10

60

145

2

V

5

pF

µA

mA

Clock Pin Capacitance

C_CLK

C_IDSEL

I_OL

IDSEL Pin Capacitance

Output Leakage Current

Power Supply Current 1

(Normal Operation)

5

-10

PVDD+VDD5

VDD3

Power Supply Current 2

(Power Save)

*9, PVDD+VDD5

*9, VDD3

0.5

6

10

Note : Top = 0~70°C, PVDD=5.0±0.25[V], VDD5=5.0±0.25[V], VDD3=3.3±0.3[V], LVDD=3.3±0.3[V], C_L=50 pF

*1: Applicable to all PCI Iuput/Output pins and Iunput pins except PCICLK and RST# pin.

*2: Applicable to RST# pin.

*3: Applicable to CBCLK, CSDI, ACDI, ASDI, GP[7:4], RXD, VOLUP#, VOLDW#, ROMDI and TEST[7:0]#

pins.

*4: Applicable to XI24 pin.

*5: Applicable to AD[31:0], C/BE[3:0]#, PAR, REQ#, PCREQ#, SERIRQ#, TXD, ALRCK, ASDO, ACDO, ACS#,

ROMSK, ROMDO, ROMCS and DIT pins.

*6: Applicable to FRAME#, IRDY#, TRDY#, STOP#, DEVSEL#, PERR#, SERR#, ABCLK, ASCLK, CRST#,

CSYNC and CSDO pins.

*7: Applicable to IRQ5, IRQ7, IRQ9, IRQ10, IRQ11 and INTA# pins.

*8: Applicable to CMCLK, XRST# and XO24 pins.

*9: DS-1 Power Control Register, DMC=DPLL0=DPLL1=PSN=PSL0=PSL1=“1”, PCICLK (33MHz) is stopped.

January 14, 1999

-43-

YMF724F

4. AC Characteristics

4-1. Master Clock (Fig.1)

Item

Symbol

Min.

Typ.

Max.

Unit

XI24 Cycle Time

XI24 High Time

XI24 Low Time

t_XICYC

t_XIHIGH

t_XILOW

-

40.69

-

ns

16

-

24

Note : Top = 0-70°C, PVDD=5.0±0.25 V, VDD5=5.0±0.25 V, VDD3=3.3±0.3 V, LVDD=3.3±0.3 V

3.5 V

2.5 V

XI24

1.0 V

t

XIHIGH

XILOW

t

XICYC

Fig.1: XI24 Master Clock timing

4-2. Reset (Fig.2)

Item

Symbol

Min.

Typ.

Max.

Unit

Reset Active Time after Power Stable

Power Stable to Reset Rising Edge

Reset Slew Rate

t_RST

t_RSTOFF

-

1

-

ms

10

50

mV/ns

Note : Top = 0-70°C, PVDD=5.0±0.25 V, VDD5=5.0±0.25 V, VDD3=3.3±0.3 V, LVDD=3.3±0.3 V, C_L=50 pF

4.75 V

PVDD, VDD5

3.0 V

LVDD, VDD3

t_RSTOFF

t_RST

RST#

0.6 V

Fig.2: PCI Reset timing

January 14, 1999

-44-

YMF724F

4-3. PCI Interface (Fig.3, 4)

Item

Symbol

Condition

Min.

Typ.

Max.

Unit

PCICLK Cycle Time

PCICLK High Time

PCICLK Low Time

PCICLK Slew Rate

t_PCYC

t_PHIGH

t_PLOW

-

30

11

1

-

ns

-

ns

4

V/ns

ns

t_PVAL

(Bused signal)

2

11

12

-

PCICLK to Signal Valid Delay

t_PVAL(PTP)(Point to Point)

2

ns

Float to Active Delay

Active to Float Delay

t_PON

2

ns

t_POFF

-

28

-

ns

t_PSU

t_PSU(PTP)

t_PH

(Bused signal)

7

ns

Input Setup Time to PCICLK

Input Hold Time for PCICLK

*10 (Point to Point)

*11 (Point to Point)

10

12

0

ns

-

ns

Note : Top = 0-70°C, PVDD=5.0±0.25 V, VDD5=5.0±0.25 V, VDD3=3.3±0.3 V, LVDD=3.3±0.3 V, C_L=50 pF

*10: This characteristic is applicable to REQ# and PCREQ# signal.

*11: This characteristic is applicable to GNT# and PCGNT# signal.

2.2 V

1.5 V

PCICLK

0.8 V

t

PLOW

PHIGH

t

PCYC

Fig.3: PCI Clock timing

1.5 V

PCICLK

t_PVAL

1.5 V

OUTPUT

t_PON

Tri-State

OUTPUT

t_PSU

t_PH

t_POFF

1.5 V

INPUT

Fig.4: PCI Bus Signals timing

January 14, 1999

-45-

YMF724F

4-4. AC’97 / AC3F2 Master Clock (Fig.5)

Item

Symbol

Min.

Typ.

Max.

Unit

CMCLK Cycle Time

CMCLK High Time

CMCLK Low Time

CMCLK Rising Time

CMCLK Falling Time

t_CMCYC

t_CMHIGH

t_CMLOW

t_CMR

-

8

-

40.69

-

ns

4.6

2.1

t_CMF

-

Note : Top = 0-70°C, PVDD=5.0±0.25 V, VDD5=5.0±0.25 V, VDD3=3.3±0.3 V, LVDD=3.3±0.3 V, C_L=50 pF

t

CMR

CMF

3.5 V

2.5 V

0.4 V

CMCLK

t

CMHIGH

t

CMLOW

CMCYC

Fig.5: Master Clock timing for AC’97 and AC3F2

4-5. AC-link (Fig.6)

Item

Symbol

Condition

Min.

Typ.

Max.

Unit

CBCLK Cycle Time

t_CBICYC

t_CBIHIGH

t_CBILOW

t_CSYCYC

t_CSYHIGH

t_CSYLOW

t_CVAL

-

35

-

81.4

40.7

20.8

1.3

19.5

-

45

-

ns

µs

CBCLK High Time

CBCLK Low Time

CSYNC Cycle Time

CSYNC High Time

-

CSYNC Low Time

-

CBCLK to Signal Valid Delay

Output Hold Time for CBCLK

Input Setup Time to CBCLK

Input Hold Time for CBCLK

Warm Reset Width

*12

*13

-

20

-

t_COH

0

-

t_CISU

15

5

-

t_CIH

-

1.3

-

Note) Top = 0-70°C, PVDD=5.0±0.25 V, VDD5=5.0±0.25 V, VDD3=3.3±0.3 V, LVDD=3.3±0.3 V, C_L=50 pF

*12: This characteristic is applicable to CSYNC and CSDO signal.

*13: This characteristic is applicable to CSDI signal.

January 14, 1999

-46-

YMF724F

t_CBICYC

2.2 V

1.5 V

CBCLK

0.8 V

t_CBIHIGH

t_CBILOW

t_COH

t_CSYLOW

t_CVAL

2.2 V

1.5 V

0.8 V

SYNC

t_CSYHIGH

t_CSYCYC

t_CVAL

t_COH

2.2 V

0.8 V

CSDO

t_CISU

t_CIH

2.2 V

0.8 V

CSDI

Fig.6: AC-link timing

4-6 AC3F2 Interface (Fig.7, 8)

Item

Symbol

t_ASCCYC

Condition

Min.

Typ.

Max.

Unit

ASCLK Cycle Time

-

325

-

180

50

-

ns

ASCLK High Time

t_ASCHIGH

140

-

ASCLK Low Time

t_ASCLOW

-

ASCLK to Signal Valid Delay

Output Hold Time for ASCLK

Input Setup Time to ASCLK

Input Hold Time for ASCLK

ABCLK Cycle Time

t_ACVAL*14

-

t_ACOH

t_ACISU

*14

*15

-10

20

10

-

t_ACIH

-

t_ABICYC

t_ABIHIGH

t_ABILOW

325

-

ABCLK High Time

140

-

180

50

-

ABCLK Low Time

ABCLK to Signal Valid Delay

Output Hold Time for ABCLK

Input Setup Time to ABCLK

Input Hold Time for ABCLK

t_ASVAL*16

t_ASOH

t_ASISU

t_ASIH

*16

*17

-10

20

10

-

Note) Top = 0-70°C, PVDD=5.0±0.25 V, VDD5=5.0±0.25 V, VDD3=3.3±0.3 V, LVDD=3.3±0.3 V, C_L=50 pF

*14: This characteristic is applicable to ACS and ACDO signal.

*15:This characteristic is applicable to ACDI signal.

*16: This characteristic is applicable to ASDO and ALRCK signal.

*17: This characteristic is applicable to ASDI signal.

January 14, 1999

-47-

YMF724F

t_ASCCYC

2.2 V

1.5 V

ASCLK

0.8 V

t_ASCLOW

t_ASCHIGH

t_ACVAL

t_ACOH

2.2 V

0.8 V

ACS, ACDO

t_ACISU

t_ACIH

2.2 V

ACDI

0.8 V

Fig.7: AC3F2 Control Interface timing

t_ABICYC

2.2 V

1.5 V

ABCLK

ASDO, ALRCK

ASDI

0.8 V

t_ABILOW

t_ABIHIGH

t_ASVAL

t_ASOH

2.2 V

0.8 V

t_ASISU

t_ASIH

2.2 V

0.8 V

Fig.8: AC3F2 Audio Interface timing

January 14, 1999

-48-

YMF724F

EXTERNAL DIMENSIONS

YMF724F-V

22.00±0.40

20.00±0.30

108

73

109

72

144

37

1

36

0.20±0.10

P-0.50TYP

(1.00)

0-10˚

LEAD THICKNESS : 0.15+0.10

-0.06

0.50±0.20

The shape of the molded corner may slightly different from the shape in this diagram.

The figure in the parenthesis ( ) should be used as a reference.

Plastic body dimensions do not include burr of resin.

UNIT : mm

Note : The LSIs for surface mount need especial consideration on storage and soldering conditions.

For detailed information, please contact your nearest agent of Yamaha.

January 14, 1999

-49-

YMF724F

IMPORTANT NOTICE

1. Yamaha reserves the right to make changes to its Products and to this document without

notice. The information contained in this document has been carefully checked and is

believed to be reliable. However, Yamaha assumes no responsibilities for inaccuracies and

makes no commitment to update or to keep current the information contained in this

document.

2. These Yamaha Products are designed only for commercial and normal industrial

applications, and are not suitable for other uses, such as medical life support equipment,

nuclear facilities, critical care equipment or any other application the failure of which could

lead to death, personal injury or environmental or property damage. Use of the Products in

any such application is at the customer's sole risk and expense.

3. YAMAHA ASSUMES NO LIABILITY FOR INCIDENTAL, CONSEQUENTIAL OR

SPECIAL DAMAGES OR INJURY THAT MAY RESULT FROM MISAPPLICATION OR

IMPROPER USE OR OPERATION OF THE PRODUCTS.

4. YAMAHA MAKES NO WARRANTY OR REPRESENTATION THAT THE PRODUCTS

ARE SUBJECT TO INTELLECTUAL PROPERTY LICENSE FROM YAMAHA OR

ANYTHIRD PARTY, AND YAMAHA MAKES NO WARRANTY OR REPRESENTATION

OF NON-INFRINGEMENT WITH RESPECT TO THE PRODUCTS. YAMAHA

SPECIFICALLY EXCLUDES ANY LIABILITY TO THE CUSTOMER OR ANY THIRD

PARTY ARISING FROM OR RELATED TO THE PRODUCTS' INFRINGEMENT OF ANY

THIRD PARTY'S INTELLECTUAL PROPERTY RIGHTS, INCLUDING THE PATENT,

COPYRIGHT, TRADEMARK OR TRADE SECRET RIGHTS OF ANY THIRD PARTY.

5. EXAMPLES OF USE DESCRIBED HEREIN ARE MERELY TO INDICATE THE

CHARACTERISTICS AND PERFORMANCE OF YAMAHA PRODUCTS. YAMAHA

ASSUMES NO RESPONSIBILITY FOR ANY INTELLECTUAL PROPERTY CLAIMS OR

OTHER PROBLEMS THAT MAY RESULT FROM APPLICATIONS BASED ON THE

EXAMPLES DESCRIBED HEREIN. YAMAHA MAKES NO WARRANTY WITH RESPECT

TO THE PRODUCTS, EXPRESS OR IMPLIED, INCLUDING, BUT NOT LIMITED TO THE

WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR USE AND

TITLE.

Note) The specifications of this product are subject to improvement change without prior notice.

YAMAHA CORPORATION

Address inquires to :

AGENCY

Semi-conductor Sales Department

- Head Office

203, MatsunokiJima, Toyooka-mura.

Iwata-gun, Shizuoka-ken, 438-0192

Tel. +81-539-62-4918 Fax. +81-539-62-5054

2-17-11, Takanawa, Minato-ku, Tokyo, 108-8568

Tel. +81-3-5488-5431 Fax. +81-3-5488-5088

1-13-17, Namba Naka, Naniwa-ku,

- Tokyo Office

- Osaka Office

Osaka City, Osaka, 556-0011

Tel. +81-6-6633-3690 Fax. +81-6-6633-3691

YAMAHA System Technology.

- U.S.A. Office

100 Century Center Court, San Jose, CA 95112

Tel. +1-408-467-2300 Fax. +1-408-437-8791

January 14, 1999

-50-

型号:	YMF724F-V
是否无铅：	含铅
是否Rohs认证：	不符合
生命周期：	Obsolete
零件包装代码：	QFP
包装说明：	LFQFP,
针数：	144
Reach Compliance Code：	unknown
HTS代码：	8542.39.00.01
风险等级：	5.82
其他特性：	IT CAN ALSO OPERATE IN THE RANGE OF 4.75 TO 5.25V
商用集成电路类型：	CONSUMER CIRCUIT
JESD-30 代码：	S-PQFP-G144
长度：	20 mm
湿度敏感等级：	1
功能数量：	1
端子数量：	144
最高工作温度：	70 °C
最低工作温度：
封装主体材料：	PLASTIC/EPOXY
封装代码：	LFQFP
封装形状：	SQUARE
封装形式：	FLATPACK, LOW PROFILE, FINE PITCH
峰值回流温度（摄氏度）：	225
认证状态：	Not Qualified
座面最大高度：	1.7 mm
最大压摆率：	205 mA
最大供电电压 (Vsup)：	3.6 V
最小供电电压 (Vsup)：	3 V
表面贴装：	YES
温度等级：	COMMERCIAL
端子形式：	GULL WING
端子节距：	0.5 mm
端子位置：	QUAD
处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	20 mm
Base Number Matches：	1

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