YMU762-QE2原理图各脚功能电路原理芯片引脚定义引脚图及功能-中国IC网-芯三七

YMU762

MA-3

Mobile Audio 3

Outline

MA-3 is a synthesizer LSI for mobile phones that realize advanced game sounds.

This LSI has a built-in speaker amplifier, and thus, is an ideal device for outputting sounds that are used by mobile

phones in addition to game sounds and ringing melodies that are replayed by a synthesizer.

The synthesizer section adopts “stereophonic hybrid synthesizer system” that are given advantages of both FM

synthesizers and Wave Table synthesizers to allow simultaneous generation of up to thirty two FM voices and eight

Wave Table voices.

Since FM synthesizer is able to present countless voices by specifying parameters with only several tens of bytes,

memory capacity and communication band can be saved, and thus, the device exhibits the features in operating

environment of mobile phones such as allowing distribution of arbitrary melodies with voices.

On the other hand, Wave Table synthesizer can pronounce the voice built in ROM and arbitrary ADPCM/PCM voices

from sequencer by the download of the melody with voices etc..

MA-3 has a built-in hardware sequencer that helps to realize complex play without heavily loading the host CPU.

The device also has a built-in circuit for controlling vibrators and LEDs synchronizing with play of music.

Features

MA-3 has features as described below.

■

Simultaneous generation of up to 40 tones: FM + Wave Table stereophonic hybrid synthesizer.

Polyphonic synthesizer specification.

Has built-in default voices for FM and Wave Table synthesizers in the ROM, and the voices can be downloaded to

RAM.

Fundamental waveforms for FM and algorithm are improved compared with YMU759 (MA-2), and voice

parameters of detune etc. are added.

■

Stream replay with ADPCM / PCM (shared use of Wave Table section).

Software interrupt mechanism for external synchronization.

Equipped with 8 bit parallel I/F for control from CPU.

Equipped with speaker amplifier and equalizer circuit.

Equipped with vibration control circuit, and LED lighting control circuit.

Has built-in PLL to support inputting of master clock up to 20 MHz.

Contains a 16-bit stereophonic D/A converter.

Equipped with a stereophonic output terminal for headphone.

Supports power down mode.

Digital power supply: 2.7V to 3.3V (Typ 3.0V)

Analog power supply: 2.7V to 4.5V (Typ 3.6V)

32-pin QFN plastic package. The plating of pins is lead-free. (YMU762-QZ)

YAMAHA CORPORATION

YMU762 CATALOG

CATALOG No.:LSI-4MU762A50

2005. 1

YMU762

Pin configuration

25 24 23 22 21 20 19 18 17

16

D1

D0

SPVSS

26

27

28

29

15

14

13

SPVDD

EQ3

/WR

/CS

EQ2

12

A0

EQ1

30

11

10

/RD

IOVDD

HPOUT-R

HPOUT-L/MONO

31

32

1

2

3

4

5

6

7

8

9

<32pin QFN Top View>

2

YMU762

Functions of pins

No.

Pin name

I/O

Power supply

Function

Clock input ( 2 MHz to 20 MHz)

External LED control (Drive Capability = 4 mA)

Interrupt output (Drive Capability = 1 mA)

Hardware reset input

1

2

3

4

5

CLKI

LED

/IRQ

/RST

N.C

Ish

O

Ish

─

IOVDD

─

No Connection (during regular operations)

Connection of capacitor for built-in PLL

Connect a series connection of 1000 pF capacitor and 3.3 kΩ resistor

between this pin and VSS(*).

6

PLLC

A

VDD

(*)Directly connect VSS used here and VSS of 8^thpin.

Power supply (Typ +3.0V)

7

8

9

VDD

VSS

─

A

─

Connect 0.1 µF and 4.7 µF capacitors between this pin and VSS.

Ground

Analog reference voltage

Connect 0.1 µF capacitor between this pin and VSS.

VREF

VDD

HPOUT-L /

MONO

HPOUT-R

EQ1

10

A

VDD

Headphone output Lch (Can be used as MONO output)

11

12

13

14

A

VDD

Headphone output Rch

Equalizer pin 1

Equalizer pin 2

Equalizer pin 3

EQ2

EQ3

Speaker amplifier analog power supply (Typ +3.6V)

Connect 0.1 µF and 4.7 µF capacitors between this pin and SPVSS.

Speaker amplifier analog ground

Speaker connection pin 1

15

SPVDD

─

16

17

18

SPVSS

SPOUT1

SPOUT2

─

A

─

SPVDD

Speaker connection pin 2

19

20

21

22

23

24

25

26

27

28

29

30

31

MTR

D7

D6

D5

D4

D3

D2

D1

D0

O

I/O

I

IOVDD

External motor control pin (Drive Capability = 4 mA)

CPU I/F data bus 7

CPU I/F data bus 6

CPU I/F data bus 5

CPU I/F data bus 4

CPU I/F data bus 3

CPU I/F data bus 2

CPU I/F data bus 1

CPU I/F data bus 0

CPU I/F write enable

CPU I/F chip select

CPU I/F address signal

CPU I/F read enable

(Drive Capability = 1 mA)

/WR

/CS

A0

I

/RD

Pin power supply (Typ +3.0V)

32

IOVDD

─

Be sure to apply potential equivalent to 7^thpin (directly connect on the

board).

A : Analog pin

Ish : Schmitt input

3

YMU762

Block diagram

SPVSS

SPVDD

↑

Analog power

Supply dedicated

To speaker amp

HPOUT-L

/MONO

HPOUT-R

Select

Sequencer

PLLC

CLKI

VSS

VDD

IOVDD

4

YMU762

Outline of blocks

This section outlines functions of blocks contained in this device and flow of signals.

Register

Voice ROM

Headphone

Output

FIFO

Instantaneous write path

FM+WaveTable

Synthesizer

EQ

amp.

DAC

FIFO

Sequencer

Delayed write path

Speaker

amp.

SRAM

Buffer

Instantaneous read path

CPU interface

CPU interface is an 8-bit parallel type.

- ”Instantaneous write path” that enables Write command immediately (equipped with 64byte FIFO),

- ”Delayed write path” that enables Write command after elapse of specified time, and

- Instantaneous read path

are available.

Hardware sequencer and FIFO

The sequencer is a block that controls time and register access.

The structure of sequence data includes “time information data + MA-3 register control data”, for which 512 byte FIFO

is provided. The sequence data is written into delayed write path.

FM+Wave Table synthesizer

This device contains a Polyphonic synthesizer that adopts FM +Wave Table stereophonic hybrid system that generates

up to 40 tones.

The FM synthesizer has two operation modes; “16-Voice 4 operation mode” and “32-Voice 2 operation mode” which

can be changed to each other freely (except during tone generation).

Since waveform for FM operation can be set arbitrarily, the device is able to create voices that are more complex than

by conventional devices.

Wave Table synthesizers is able to generate eight voices simultaneously, and supports 8 bit PCM and 4 bit ADPCM

data format. The sampling frequency is 48 kHz. Stream replaying is also available, realizing interchangeability with

ADPCM replay capability of MA-2.

Voice ROM and SRAM

This device stores voice parameters (GM 128 voices + DRUM 40 voices) for FM and waveform data for Wave Table in

the ROM. SRAM is used when downloading arbitrary FM voice parameter and waveform data for Wave Table. It is

also used as waveform data buffer at stream replay with PCM/ADPCM.

DAC

Converts digital signal from a synthesizer into analog signal. The data length is 16 bit.

IRQ and TIMER

This device supports FIFO, two hardware TIMERs, and interrupt output with software interrupt.

Headphone output

This device supports stereophonic analog output for the headphone. Monaural output is available.

5

YMU762

EQ amplifier

The filter response and gain of the amplifier can be changed by adjusting external parts such as resistors and/or

capacitors.

Speaker amplifier

A speaker amplifier of which maximum out is 580 mW at SPVDD=3.6V is built in this device.

A control that adjusts the output level of the amplifier is provided in the previous stage of the amplifier.

LED and vibrator control block

LEDs and vibrator can be controlled synchronizing with a play. Control asynchronous with play is also possible.

Clock generating block

This devices supports clock input ranging from 2 MHz to 20 MHz. (Stop = 0 Hz is possible at power down.)

This block increases the frequency of inputted clock with various frequency by using PLL to create clocks with fixed

frequency that are needed in the device.

6

YMU762

Electrical Characteristics

Absolute maximum rating

Item

Symbol

SPVDD

Min.

-0.3

Max.

6.0

Unit

V

SPVDD pin, power supply voltage

(Speaker amplifier section)

VDD pin, power supply voltage

IOVDD pin, power supply voltage

SPOUT1, SPOUT2 pin, applied voltage

Analog input voltage

VDD

IOVDD

V_INSP

V_INA

-0.3

4.2

V

SPVDD+0.3

VDD+0.3

IOVDD+0.3

1197

V

Digital input voltage

V_IND

V

Permissible loss (*)

Pd

mW

°C

Storage temperature

T_STG

-50

125

Note: VSS = SPVSS = 0V

(*) : Top= 25 °C, and glass epoxy PCB (30mm × 100mm × 1.0mm) is installed.

Operation with Top= 25 °C or higher degrees the permissible loss at the rate of 12mW per 1 °C.

Recommended operating conditions

Item

Symbol

SPVDD

Min.

2.7

Typ.

3.6

Max.

4.5

Unit

V

SPVDD operating voltage

(Speaker amplifier section)

VDD operating voltage

IOVDD operating voltage

Operating ambient temperature

VDD

IOVDD

T_OP

2.7

-20

3.0

25

3.3

85

V

°C

Note: VSS = SPVSS = 0V

Make VDD and IOVDD into same electric potential (Connect them directly on the circuit board).

DC characteristics

Item

Symbol

Condition

Min.

0.7 × IOVDD

Typ.

0.5

Max.

Unit

Input voltage “H” level

Input voltage “L” level

Output voltage “H” level

Output voltage “L” level

Schmitt width

Input leakage current

Input capacity

V_IH

V_IL

V_OH

V_OL

Vsh

IL

V

0.2 × IOVDD

I_OH= (*) 0.8 × IOVDD

I_OL= (*)

V

0.4

V

-10

10

µA

pF

CI

Note: T_OP=-20 to 85°C, VDD, IOVDD=3.0±0.3V, Capacitor load=50 pF

(*) : /IRQ, D0 ~ D7 are I_OH= –1 mA, I_OL= +1 mA

LED, MTR

are I_OH= –4 mA, I_OL= +4 mA

7

YMU762

AC characteristics

/RST, CLKI

Item

Symbol

T_RSTW

T_RSTS

1 / Tfreq

Tr / Tf

Th / Tfreq

Min.

100

0

Typ.

50

Max.

Unit

µs

MHz

ns

%

/RST “L” pulse width

/RST (indefinite → L) setup time

CLKI frequency

0

20

30

70

CLKI rise / fall time

CLKI duty factor

30

Note: T_OP=-20 to 85°C, VDD, IOVDD=3.0±0.3V, Capacitor load=50 pF

The input to Clock can be stopped (=0Hz) during reset period and power down state (DP0=1).

However, the input level is to be H or L, and input of intermediate level is prohibited.

90%

VDD, IOVDD

30%

T_RSTW

/RST

V_IL= 0.2*IOVDD

T_RSTS

The reset width is defined as the time from the moment VDD or IOVDD has risen to 90%.

/RST has to be settled at “L” level at the time VDD or IOVDD has risen to 30%.

T_r

T_f

T_h

V_IH= 0.7*IOVDD

0.5*IOVDD

V_IL= 0.2*IOVDD

CLKI

T_freq

Measurement point

V_IH= 0.7*IOVDD

V_IL= 0.2*IOVDD

V_OH= 0.8*IOVDD

V_OL= 0.2*IOVDD

8

YMU762

CPU interface

(Write cycle)

Item

Symbol

Min

Max.

Unit

Address setup time

Address hold time

Chip select setup time

Chip select hold time

Write pulse width

Data setup time

T_ADS

T_ADH

T_CSS

T_CSH

T_WW

T_WDS

T_WDH

50

0

50

0

50

30

0

ns

Data hold time

T_OP=-20 to 85°C, VDD,IOVDD=3.0±0.3V, Capacitor load=50 pF

(Read cycle)

Item

Symbol

Min

Max.

Unit

Address setup time

Address hold time

Chip select setup time

Chip select hold time

Read pulse width

Read data access time

Data hold time

T_ADS

T_ADH

T_CSS

T_CSH

T_RW

T_ACC

T_RDH

80

0

80

0

80

ns

70

30

0

T_OP=-20 to 85°C, VDD,IOVDD=3.0±0.3V, Capacitor load=50 pF

Write cycle

A0

TADS

TCSS

TADH

TCSH

/CS

TWW

/WR

TWDS

TWDH

Invalid

Valid

Invalid

D0 -D7

Note : Under the conditions of T_CSH≥ 0ns,

T_ADH,T_WDH

T_ADS,T_WDS

:

Defined with respect to the point where the rise of /WR has reached 0.7*IOVDD.

Defined with respect to the point where the rise of /WR has reached 0.2*IOVDD.

9

YMU762

Read cycle

A0

TADS

TCSS

TADH

TCSH

/CS

/RD

TRW

TACC

TRDH

D0 -D7

Valid

Note : Under the conditions of T_CSH≥ 0ns,

T_ADH, T_RDH

T_ADS, T_CSS

T_ACC

:

Defined with respect to the point where the rise of /RD has reached 0.7*IOVDD.

Defined with respect to the point where the rise of /RD has reached 0.2*IOVDD.

Defined with respect to the point where any of /CS , /RD and A0 has changed later.

Time to the point where D0-D7 pins become high impedance.

T_RDH

Power consumption

Item

Min.

Typical

25

4

210

1

Max.

10

Unit

Load current of VDD+ IOVDD (at regular operation)

At SPVDD side no tone

At SPVDD side 8ohm load 400mW output

Power down mode (VDD + IOVDD+SPVDD) (*)

mA

µA

Note: T_OP=-20 to 85°C, VDD, IOVDD=3.0±0.3V, SPVDD=3.6V

(*) : Measurement condition : /CS input pin is fixed to V_IH=VDD.

10

YMU762

Analog characteristics

Conditions of T_OP=25°C, VDD, IOVDD=3.0V and SPVDD=3.6V apply to all items.

SP amplifier

Item

Min.

Typical

Max.

Unit

Gain setting (fixed)

±2

8

times

Ω

Min. load resistance (RL)

Max. output voltage amplitude (RL=8Ω)

Max. output power (RL=8Ω, THD+N≤1.0%)

THD + N (RL=8Ω, f=1 kHz, output = 400mW)

Noise at no signal (A-filter: weighting filter)

PSRR (f=1 kHz)

Amplitude center potential (VSEL2, VSEL1 =0, 0)

(VSEL2, VSEL1 =0, 1)

6.0

Vp-p

mW

%

580

0.025

-90

dBV

dB

90

0.6×VDD

0.5×VDD

0.67×VDD

10

V

(VSEL2, VSEL1 =1, 0)

V

Differential Output Voltage

50

mV

EQ amplifier

Item

Gain settable range

Max. output voltage amplitude

THD + N (f=1 kHz)

Noise at no signal (A-filter)

Input impedance

Min.

Typical

Max.

30

Unit

dB

Vp-p

%

dBV

MΩ

kΩ

2.7

-90

0.05

10

20

Feedback resistance between EQ2 and EQ3

SP Volume

Item

Volume setting range

Volume step width

THD + N (f=1 kHz)

Min.

-30

Typical

1

Max.

0

Unit

dB

%

0.05

EQ Volume

Item

Volume setting range

Volume step width

Noise at no signal (A-filter)

Max. output current

Max. output voltage amplitude

Output impedance

Min.

-30

Typical

Max.

0

Unit

dB

dBV

µA

Vp-p

Ω

1

-90

120

1.5

300

600

11

YMU762

HP Volume

Item

Min.

-30

Typical

Max.

0

Unit

dB

dBV

µA

Vp-p

Ω

Volume setting range

Volume step width

Noise at no signal (A-filter)

Max. output current

Max. output volt. amplitude

Output impedance

1

-90

120

1.5

300

600

VREF

Item

Min.

Typical

0.5×VDD

Max.

Unit

V

VREF voltage

DAC

Min.

Typical

Max.

Unit

Resolution

16

Bit

Vp-p

%

dBV

dB

Full scale output volt.

THD+N (f= 1 kHz)

Noise at no signal (A-filter)

1.5

0.5

-80

+0.5

-85

Frequency response (f=50Hz to 20 kHz)

-3.0 (*)

(*): Reduction of response in high frequency range caused by aperture effect

12

YMU762

External dimensions of package

13

YMU762

Notice ^{The specifications of this product are subject to improvement changes without prior notice.}

型号:	YMU762-QZ
是否Rohs认证：	符合
生命周期：	Obsolete
零件包装代码：	QFN
包装说明：	VQCCN,
针数：	32
Reach Compliance Code：	unknown
HTS代码：	8542.39.00.01
风险等级：	5.83
其他特性：	IT ALSO REQUIRES 2.7V TO 3.3V SUPPLY
商用集成电路类型：	TONE/MUSIC SYNTHESIZER
JESD-30 代码：	R-PQCC-N32
长度：	6.2 mm
功能数量：	1
端子数量：	32
片上内存类型：	ROM; SRAM; FIFO
最高工作温度：	85 °C
最低工作温度：	-20 °C
封装主体材料：	PLASTIC/EPOXY
封装代码：	VQCCN
封装形状：	RECTANGULAR
封装形式：	CHIP CARRIER, VERY THIN PROFILE
认证状态：	Not Qualified
座面最大高度：	1 mm
最大供电电压 (Vsup)：	4.5 V
最小供电电压 (Vsup)：	2.7 V
表面贴装：	YES
温度等级：	OTHER
端子形式：	NO LEAD
端子节距：	0.5 mm
端子位置：	QUAD
宽度：	5.2 mm
Base Number Matches：	1

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