A-Data
Pin Description
PIN
CLK
CKE
NAME
System Clock
Clock Enable
FUNCTION
Active on the positive edge to sample all inputs.
ADS8608A8A
Masks system clock to freeze operation from the next clock cycle. CKE
should be enabled at least on cycle prior new command. Disable input
buffers for power down in standby
/CS
Chip Select
Disables or Enables device operation by masking or enabling all input
except CLK, CKE and L(U)DQM
A0~A12
Address
Row / Column address are multiplexed on the same pins.
Row address : A0~A12
Column address : A0~A9
BS0~BS1 Banks Select
Selects bank to be activated during row address latch time.
Selects bank for read / write during column address latch time.
DQ0~DQ7 Data
/RAS
/CAS
/WE
Row Address Strobe
Column Address Strobe
Write Enable
Data inputs / outputs are multiplexed on the same pins.
Latches row addresses on the positive edge of the CLK with /RAS low
Latches Column addresses on the positive edge of the CLK with /CAS low
Enables write operation and row recharge.
Power and Ground for the input buffers and the core logic.
Power supply for output buffers.
This pin is recommended to be left No Connection on the device.
VCC/VSS Power Supply/Ground
V
CCQ
/V
SSQ
Data Output Power/Ground
NC
No Connection
Block Diagram
CLK
CKE
Address
Clock
Generator
Bank3
Bank2
Bank1
Row Decoder
Mode
Register
Address
Buffer
&
Refresh
Counter
Bank0
Amplifier
DQM
Command Decoder
/RAS
/CAS
/WE
Control Logic
/CS
Data Latch
Column
Address
Buffer
&
Refresh
Counter
Column Decoder
Data Control Circuit
DQ
Rev 1.0 December, 2001
2
A-DATA [ A-DATA TECHNOLOGY ]
