V-Data
Pin Description
PIN
CLK
CKE
NAME
System Clock
Clock Enable
FUNCTION
Active on the positive edge to sample all inputs.
VDS4616A4A
Masks system clock to freeze operation from the next clock cycle. CKE
should be enabled at least on cycle prior new command. Disable input
buffers for power down in standby
/CS
Chip Select
Disables or Enables device operation by masking or enabling all input
except CLK, CKE and L(U)DQM
A0~A10
Address
Row / Column address are multiplexed on the same pins.
Row address : A0~A10
Column address : A0~A7
DQ0~DQ15 Data
L(U)DQM Data Mask
/RAS
/CAS
/WE
Row Address Strobe
Column Address Strobe
Write Enable
Data inputs / outputs are multiplexed on the same pins.
Makes data output Hi-Z,
Latches row addresses on the positive edge of the CLK with /RAS low
Latches Column addresses on the positive edge of the CLK with /CAS low
Enables write operation and row recharge.
Power and Ground for the input buffers and the core logic.
Power supply for output buffers.
This pin is recommended to be left No Connection on the device.
VDD/VSS Power Supply/Ground
V
DDQ
/V
SSQ
Data Output Power/Ground
NC
No Connection
Block Diagram
CLK
CKE
Address
Clock
Generator
Bank B
Row Decoder
Mode
Register
Address
Buffer
&
Refresh
Counter
Bank A
Amplifier
DQM
Command Decoder
/RAS
/CAS
/WE
Control Logic
/CS
Input & Output
Buffer
Data Latch
Column
Address
Buffer
&
Refresh
Counter
Column Decoder
Data Control Circuit
DQ
Rev 1 December, 2001
2
A-DATA [ A-DATA TECHNOLOGY ]
