Ai338
1.4 Pin Arrangement
V
OUT
8
NC
7
NC
6
GND
5
V
φ1
4
V
φ2
3
V
φ3
2
V
φ4
1
PD
VCCD
HCCD
9
10
11
12
13
14
15
16
V
DD
GND V
SUB
PT
V
RG
NC
H
φ1
H
φ2
1.5 Pin Descriptions
Pin
1
2
3
4
5
6
7
8
Symbol
ΦV4
ΦV3
ΦV2
ΦV1
GND
NC
NC
VO
Description
Vertical register transfer clock 4
Vertical register transfer clock 3
Vertical register transfer clock 2
Vertical register transfer clock 1
Ground
No connection
No connection
CCD output signal
Pin
9
10
11
12
13
14
15
16
Symbol
VDD
GND
ΦSUB
PT
ΦRG
NC
ΦH1
ΦH2
Description
Output amplifier drain bias
Ground
Substrate (Overflow drain) bias
Protection bias
Reset gate clock
No connection
Horizontal register transfer clock 1
Horizontal register transfer clock 2
1.6 Absolute Maximum Ratings
Relative to GND
Symbols
Min.
VDD
- 0.2
- 7.5
Reference
- 0.2
- 0.2
- 0.2
- 7.0
- 7.0
- 0.2
12.0
29.0
5.0
14.0
7.0
15.0
Max.
15.0
0.2
(Unit : V)
PT
GND
ΦRG
ΦSUB
ΦH1, ΦH2
ΦV1
ΦV2, ΦV3, ΦV4
VO
A1 PROs Co., Ltd.
2
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