switched connections have already been
established.
By integrating both switching and
interprocessor communications, the
IMP8980D allows systems to use distrib-
uted processing and to switch voice or data
in an ST-BUS architecture.
Hardware Description
Serial data at 2048 kbit/s is received at
the eight ST-BUS inputs (STi0 to STi7),
and serial data is transmitted at the eight
ST-BUS outputs (STo0 to STo7). Each
serial input accepts 32 channels of digital
data, each channel containing an 8-bit
word which may represent a PCM-encoded
analog/voice sample as provided by a
codec.
This serial input word is converted into
parallel data and stored in the 256 X 8
Data Memory. Locations in the Data
Memory are associated with particular
channels on particular ST-BUS input
streams. These locations can be read by the
microprocessor which controls the chip.
Locations in the Connection Memory,
which is split into high and low parts, are
associated with particular ST-BUS output
streams. When a channel is due to be
transmitted on an ST-BUS output, the
data for the channel can either be switched
from an ST-BUS input or it can originate
from the microprocessor. If the data is
switched from an input, then the contents
of the Connection Memory Low location
associated with the output channel is used
to address the Data Memory. This Data
Memory address corresponds to the
channel on the input ST-BUS stream on
which the data for switching arrived. If the
data for the output channel originates
from the microprocessor (Message Mode),
then the contents of the Connection
Memory Low location associated with the
output channel are output directly, and
this data is output repetitively on the
channel once every frame until the
microprocessor intervenes.
The Connection Memory data is
received, via the Control Interface, at D7
to D0. The Control Interface also receives
address information at A5 to A0 and
2
© IMP, Inc.
handles the microprocessor control signals
CS, DTA, R/W and DS. There are two
parts to any address in the Data Memory
or Connection 2-7 Memory. The higher
order bits come from the Control Register,
which may be written to or read from via
the Control Interface. The lower order bits
come from the address lines directly.
The Control Register also allows the
chip to broadcast messages on all ST-BUS
outputs (i.e., to put every channel into
Message Mode), or to split the memory so
that reads are from the Data Memory and
writes are to the Connection Memory Low.
The Connection Memory High determines
whether individual output channels are in
Message Mode, and allows individual
output channels to go into a high-
impedance state, which enables arrays of
IMP8980D s to be constructed. It also
controls the CSTo pin.
All ST-BUS timing is derived from the
C4i and F0i signals.
Software Control
The address lines on the Control
Interface give access to the Control
Register directly or, depending on the
contents of the Control Register, to the
High or Low sections of the Connection
Memory or to the Data Memory.If address
line A5 is low, then the Control Register is
addressed regardless of the other address
lines (see
Figure 3).
If A5 is high, then the
address lines A4-A0 select the memory
location corresponding to channel 0-31 for
the memory and stream selected in the
Control Register.
The data in the Control Register
consists of mode control bits, memory
select bits, and stream address bits (see
Figure 4). The memory select bits allow the
Connection Memory High or Low or the
Data Memory to be chosen, and the
stream address bits define one of the
ST-BUS input or output streams.
Bit 7 of the Control Register allows split
memory operation - reads are from the
Data Memory and writes are to the
Connection Memory Low.
The other mode control bit, bit 6, puts
every output channel on every output
IMP8980D DS-5-00
A1PROS [ A1 PROS CO., LTD. ]
