AAT3215
150mA CMOS High Performance LDO
Figure 2 shows the preferred method for the bypass
and output capacitor connections. For low output
noise and highest possible power supply ripple
rejection performance, it is critical to connect the
bypass and output capacitor directly to the LDO reg-
ulator ground pin. This method will eliminate any
load noise or ripple current feedback through the
LDO regulator.
Evaluation Board Layout
The AAT3215 evaluation layout follows the recom-
mend printed circuit board layout procedures and
can be used as an example for good application
layouts (see Figures 3, 4, and 5).
Note: Board layout shown is not to scale.
ILOAD
IIN
VIN
VOUT
VIN
LDO
Regulator
EN
BYP
GND
IGND
DC INPUT
CBYP
COUT
RLOAD
CIN
CBYP
IRIPPLE
IBYP + noise
GND
LOOP
GND
RTRACE
RTRACE
RTRACE
RTRACE
ILOAD return + noise and ripple
Figure 1: Common LDO Regulator Layout with CBYP Ripple Feedback Loop.
ILOAD
IIN
VIN
EN
VOUT
BYP
VIN
DC INPUT
GND
LDO
Regulator
GND
IGND
CBYP
COUT
RLOAD
CIN
IBYP only
IRIPPLE
RTRACE
RTRACE
RTRACE
RTRACE
ILOAD return + noise and ripple
Figure 2: Recommended LDO Regulator Layout.
14
3215.2006.05.1.6
AAT [ ADVANCED ANALOG TECHNOLOGY, INC. ]
