ACE24C16A_11 参数 Datasheet PDF下载

ACE24C16A

Two-wire Serial EEPROM

Figure 6．Output Acknowledge

Device Addressing

The 16K EEPROM devices all require an 8-bit device address word following a start condition to

enable the chip for a read or write operation (refer to Figure 7).

The device address word consists of a mandatory one, zero sequence for the first four most

significant bits as shown. This is common to all the EEPROM devices.

The next 3 bits used for memory page addressing and are the most significant bits of the data word

address which follows.

The eighth bit of the device address is the read/write operation select bit. A read operation is initiated if

this bit is high and a write operation is initiated if this bit is low.

Upon a compare of the device address, the EEPROM will output a zero. If a compare is not made, the

chip will return to a standby state.

Write Operations

Byte Write

A write operation requires an 8-bit data word address following the device address word and

acknowledgment. Upon receipt of this address, the EEPROM will again respond with a zero and then

clock in the first 8-bit data word. Following receipt of the 8-bit data word, the EEPROM will output a

zero and the addressing device, such as a microcontroller, must terminate the write sequence with a

stop condition. At this time the EEPROM enters an internally timed write cycle, t

WR,

to the nonvolatile

memory. All inputs are disabled during this write cycle and the EEPROM will not respond until the write

is complete (refer to Figure 8).

Page Write

The 16 devices are capable of 16-byte page writes.

A page write is initiated the same as a byte write, but the microcontroller does not send a stop

condition after the first data word is clocked in. Instead, after the EEPROM acknowledges receipt of the

first data word, the microcontroller can transmit up to seven more data words. The EEPROM will

respond with a zero after each data word received. The microcontroller must terminate the page write

sequence with a stop condition (refer to Figure 9).

VER 1.4

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