40MX and 42MX Automotive FPGA Families
D00
D01
D10
D11
S1
S0
Y
D
CLR
Q
OUT
D00
D01
D10
D11
S1
S0
Y
D
GATE
Q
OUT
Up to 7-Input Function Plus D-Type Flip-Flop with Clear
Up to 7-Input Function Plus Latch
D00
D0
Y
D1
S
D
GATE
CLR
Q
OUT
D01
D10
D11
S1
S0
Y
OUT
Up to 4-Input Function Plus Latch with Clear
Up to 8-Input Function (Same as C-Module)
Figure 1-3 •
42MX S-Module Implementation
7 Inputs
Hard-Wire to I/O
Programmable
Inverter
Feedback to Array
Figure 1-4 •
A42MX24 and A42MX36 D-Module Implementation
Dual-Port SRAM Modules
The A42MX36 device contains dual-port SRAM modules,
which are arranged in 256-bit blocks and can be
configured as 32x8 or 64x4. SRAM modules can be
cascaded together to form memory spaces of user-
definable width and depth. A block diagram of the
A42MX36 dual-port SRAM block is shown in
The A42MX36 SRAM modules are true dual-port
structures containing independent read and write ports.
Each SRAM module contains six bits of read and write
addressing (RDAD[5:0] and WRAD[5:0], respectively) for
64x4-bit blocks. When configured in byte mode, the
highest order address bits (RDAD5 and WRAD5) are not
used. The read and write ports of the SRAM block
contain independent clocks (RCLK and WCLK) with
programmable polarities offering active HIGH or LOW
implementation. The SRAM block contains eight data
inputs (WD[7:0]) and eight outputs (RD[7:0]), which are
connected to segmented vertical routing tracks.
The A42MX36 dual-port SRAM blocks provide an optimal
solution for high-speed buffered applications requiring
FIFO and LIFO queues. The ACTgen Macro Builder within
Actel's Designer software provides capability to quickly
design memory functions with the SRAM blocks.
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ACTEL [ Actel Corporation ]
