40MX and 42MX Automotive FPGA Families
Clock Networks
The 40MX devices have one global clock distribution
network (CLK). A signal can be put on the CLK network
by being routed through the CLKBUF buffer.
In 42MX devices, there are two low-skew, high-fanout
clock distribution networks, referred to as CLKA and
CLKB. Each network has a clock module (CLKMOD) that
can select the source of the clock signal from any of the
following (Figure
•
•
•
Externally from the CLKA pad, using CLKBUF
buffer
Externally from the CLKB pad, using CLKBUF
buffer
Internally from the CLKINTA input, using CLKINT
buffer
CLKB
CLKA
From
Pads
•
Internally from the CLKINTB input, using CLKINT
buffer
The clock modules are located in the top row of I/O
modules. Clock drivers and a dedicated horizontal clock
track are located in each horizontal routing channel.
Clock input pads in both 40MX and 42MX devices can
also be used as normal I/Os, bypassing the clock
networks.
The A42MX36 device has four additional register control
resources, called quadrant clock networks (Figure
Each quadrant clock provides a local, high-fanout
resource to the contiguous logic modules within its
quadrant of the device. Quadrant clock signals can
originate from specific I/O pins or from the internal array
and can be used as a secondary register clock, register
clear, or output enable.
CLKINB
CLKINA
CLKMOD
S0
S1
Internal
Signal
CLKO(17)
Clock
Drivers
CLKO(16)
CLKO(15)
CLKO(2)
CLKO(1)
Clock Tracks
Figure 1-7 •
Clock Networks of 42MX Devices
QCLKA
Quad
Clock
Modul
QCLK1
QCLK3
Quad
Clock
Modul
QCLKC
QCLKD
*QCLK3IN
S0 S1
S1 S0
QCLKB
*QCLK1IN
Quad
Clock
Modul
*QCLK2IN
S0 S1
QCLK2
QCLK4
Quad
Clock
Modul
*QCLK4IN
S1 S0
Note:
*QCLK1IN, QCLK2IN, QCLK3IN, and QCLK4IN are internally-generated signals.
Figure 1-8 •
Quadrant Clock Network of A42MX36 Devices
1 -4
v3.1
ACTEL [ Actel Corporation ]
