IGLOOe Low-Power Flash FPGAs
inherent low power static and dynamic capabilities of the IGLOOe device. Refer to
for an
illustration of entering/exiting Flash*Freeze mode.
Flash*Freeze
Mode
Control
Actel IGLOOe
FPGA
Flash*Freeze Pin
Figure 1-2 •
IGLOOe Flash*Freeze Mode
VersaTiles
The IGLOOe core consists of VersaTiles, which have been enhanced beyond the ProASIC
PLUS®
core
tiles. The IGLOOe VersaTile supports the following:
•
•
•
•
All 3-input logic functions—LUT-3 equivalent
Latch with clear or set
D-flip-flop with clear or set
Enable D-flip-flop with clear or set
Refer to
for VersaTile configurations.
LUT-3 Equivalent
X1
X2
X3
D-Flip-Flop with Clear or Set
Data
CLK
CLR
Y
D-FF
Enable D-Flip-Flop with Clear or Set
Data
CLK
Enable
CLR
D-FF
Y
LUT-3
Y
Figure 1-3 •
VersaTile Configurations
User Nonvolatile FlashROM
Actel IGLOOe devices have 1 kbit of on-chip, user-accessible, nonvolatile FlashROM. The FlashROM
can be used in diverse system applications:
•
•
•
•
•
•
•
•
Internet protocol addressing (wireless or fixed)
System calibration settings
Device serialization and/or inventory control
Subscription-based business models (for example, set-top boxes)
Secure key storage for secure communications algorithms
Asset management/tracking
Date stamping
Version management
The FlashROM is written using the standard IGLOOe IEEE 1532 JTAG programming interface. The
core can be individually programmed (erased and written), and on-chip AES decryption can be used
selectively to securely load data over public networks, as in security keys stored in the FlashROM for
a user design.
v1.2
1-5
ACTEL [ Actel Corporation ]
