IGLOO PLUS Device Family Overview
Bank 0
CCC
*
RAM Block
4,608-Bit Dual-Port
SRAM or FIFO Block*
Bank 1
Bank 3
I/Os
VersaTile
Bank 3
Bank 1
ISP AES
Decryption*
User Nonvolatile
FlashRom
Flash*Freeze
Technology
Charge
Pumps
Bank 2
*
Not supported by AGLP030 devices
Figure 1-1 •
IGLOO PLUS Device Architecture Overview with Four I/O Banks (AGLP030, AGLP060, and
AGLP125)
Flash*Freeze Technology
The IGLOO PLUS device has an ultra-low-power static mode, called Flash*Freeze mode, which
retains all SRAM and register information and can still quickly return to normal operation.
Flash*Freeze technology enables the user to quickly (within 1 µs) enter and exit Flash*Freeze mode
by activating the Flash*Freeze pin while all power supplies are kept at their original values. In
addition, I/Os and global I/Os can still be driven and can be toggling without impact on power
consumption, clocks can still be driven or can be toggling without impact on power consumption,
and the device retains all core registers, SRAM information, and I/O states. I/Os can be individually
configured to either hold their previous state or be tristated during Flash*Freeze mode.
Alternatively, they can be set to a certain state using weak pull-up or pull-down I/O attribute
configuration. No power is consumed by the I/O banks, clocks, JTAG pins, or PLL, and the device
consumes as little as 5 µW in this mode.
Flash*Freeze technology allows the user to switch to Active mode on demand, thus simplifying the
power management of the device.
The Flash*Freeze pin (active low) can be routed internally to the core to allow the user's logic to
decide when it is safe to transition to this mode. Refer to
for an illustration of
1 -4
v1.3
ACTEL [ Actel Corporation ]
