ProASIC
PLUS
Flash Family FPGAs
Predicted Global Routing Delay
Table 2-43 •
Worst-Case Commercial Conditions
1
V
DDP
= 3.0 V, V
DD
= 2.3 V, T
J
= 70°C
Max.
Parameter
t
RCKH
t
RCKL
t
RCKH
t
RCKL
Notes:
1. The timing delay difference between tile locations is less than 15 ps.
2. Highly loaded row 50%.
3. Minimally loaded row.
Table 2-44 •
Worst-Case Military Conditions
V
DDP
= 3.0V, V
DD
= 2.3V, T
J
= 125°C for Military/MIL-STD-883
Parameter
t
RCKH
t
RCKL
t
RCKH
t
RCKL
Description
Input Low to High (high loaded row of 50%)
Input High to Low (high loaded row of 50%)
Input Low to High (minimally loaded row)
Input High to Low (minimally loaded row)
Max.
1.1
1.0
0.8
0.8
Units
ns
ns
ns
ns
Input Low to High
2
Input High to Low
2
Input Low to High
3
Input High to Low
3
Description
Std.
1.1
1.0
0.8
0.8
Units
ns
ns
ns
ns
Note:
* The timing delay difference between tile locations is less than 15 ps.
Global Routing Skew
Table 2-45 •
Worst-Case Commercial Conditions
V
DDP
= 3.0 V, V
DD
= 2.3 V, T
J
= 70°C
Max.
Parameter
t
RCKSWH
t
RCKSHH
Description
Maximum Skew Low to High
Maximum Skew High to Low
Std.
270
270
Units
ps
ps
Table 2-46 •
Worst-Case Commercial Conditions
V
DDP
= 3.0V, V
DD
= 2.3V, T
J
= 125°C for Military/MIL-STD-883
Parameter
t
RCKSWH
t
RCKSHH
Description
Maximum Skew Low to High
Maximum Skew High to Low
Max.
270
270
Units
ps
ps
2 -5 0
v5.9
ACTEL [ Actel Corporation ]
