ProASIC
PLUS
Flash Family FPGAs
Module Delays
A
B
C
Y
A
B
C
Y
50%50%
50% 50%
50%50%
50%
50%
50%
50%
50%
50%
t
DBLH
t
DALH
t
DAHL
t
DBHL
t
DCLH
t
DCHL
Figure 2-26 •
Module Delays
Sample Macrocell Library Listing
Table 2-47 •
Worst-Case Military Conditions
1
V
DD
= 2.3 V, T
J
= 70º C, T
J
= 70°C, T
J
= 125°C for Military/MIL-STD-883
Std.
Cell Name
NAND2
AND2
NOR3
MUX2L
OA21
XOR2
LDL
2-Input NAND
2-Input AND
3-Input NOR
2-1 MUX with Active Low Select
2-Input OR into a 2-Input AND
2-Input Exclusive OR
Active Low Latch (LH/HL)
CLK-Q
t
setup
t
hold
DFFL
Negative Edge-Triggered D-type Flip-Flop (LH/HL)
CLK-Q
t
setup
t
hold
Notes:
1. Intrinsic delays have a variable component, coupled to the input slope of the signal. These numbers assume an input slope typical of
local interconnect.
2. LH and HL refer to the Q transitions from Low to High and High to Low, respectively.
LH
2
Description
Max
0.5
0.7
0.8
0.5
0.8
0.6
LH
2
HL
2
0.9
0.8
Min
Units
ns
ns
ns
ns
ns
ns
ns
ns
0.7
0.1
0.9
0.8
0.6
0.0
ns
ns
ns
ns
ns
ns
HL
2
v5.9
2-51
ACTEL [ Actel Corporation ]
